AN/B-25

SIMPLE INTERFACES TO SIMPLE SYSTEMS

INTRODUCTION
Data Device Corporation recognizes that a typical 1553 bus contains a mixture of terminals with varying degrees of complexity. One of the prominent architectural features of 1553 is that it allows complex computer systemstransferring large amounts of datato coexist with "simple systems" transferring relatively small amounts of data. A "simple system" is defined as one that does not require a processor, refer to Figure 1. Many applications, such as pressure transducers, gauges, displays, switches, D/A converters, synchro converters, etc., do not require a microprocessor to perform their intended task. So why add a processor just to satisfy the 1553 interface requirement? DDC offers a full line of "simple system" 1553 components that provide a complete 1553 interface with no processor. Think about the cost savings by eliminating the processor, both recurring and non-recurring costs. Eliminating the CPU and its support components will reduce
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the bill of material cost of the system, will reduce the complexity of the board making it easier to build and troubleshoot, and will eliminate the need to develop expensive software and all the documentation that goes along with it (MIL-STD2167 and ADA). DDC offers a trio of "simple system" Remote Terminals. The BUS-65153 STIC (Small Terminal Interface Circuit) leads the pack as the smallest, complete low cost 1553 interface. The BUS-65142 is built using a radiation hardened SOS (Silicon-on sapphire) CMOS digital protocol chip and two bipolar analog transceivers making it especially well suited for space applications. The BUS-65149 incorporates a dual sinusoidal transceiver with full multi-protocol remote terminal logic (MIL-STD-1553A and 1553B) meeting the various McAir protocols. The remainder of this discussion will be centered around the STIC (BUS-65153). Both the STIC and the BUS-65149 are built using the same digital monolithic,

BUS-65153 STIC

SENSORS

GAUGES

1553

SWITCHES

therefore, their functional operation is the same. The BUS-65142 is based on a different digital protocol chip but is very similar in operation to the STIC.

DEVICE INITIALIZATION
The STIC provides a system with a truly autonomous Remote Terminal Interface. The STIC contains no internal registers, pointers or Lookup tables that must be initialized. The STIC is ready to begin processing messages immediately following a power-up reset. No action is required by the subsystem to initialize this device. The "stand alone" operation of a 1553 Remote Terminal device is a crucial requirement for systems with no processor.

SIMPLE INTERFACES TO SIMPLE SYSTEMS

LATCHED BUS-65153 STIC DISCRETE OUTPUTS LATCHES

BUFFERED DISCRETE INPUTS CONTROL LOGIC BUFFERS

FIGURE 1. ST TO SIMPLE SYSTEM INTERFACE

DMA INTERFACE
All three of the components described make use of a DMA interface with a fixed address map (no lookup tables or other types of indirect addressing). The STIC will assert the signal DBREQ to indicate to the subsystem that a data transfer to or from the subsystem is required. The subsystem must "grant" access to the STIC within the specified time (see data sheet for specific value). You may wonder why a request/grant handshake mechanism is required for a simple system interface. Consider the case where the STIC is reading a data word directly from the output of an analog to digital (A/D) converter. Many A/D converters require a trigger to begin the conversion and provide a flag that indicates when the conversion is complete and the output data is ready. In this case the DBREQ signal may be connected to an active low conversion start signal and the conversion complete output of the A/D may be connected to the DTGRT input of the STIC. However, conversion time must be less than the maximum allowable request-to-grant time (refer to STIC data sheet for more details). Data Device Corporation www.ddc-web.com

Once the grant is received, the STIC will write or read data to or from the subsystem. The first word that is transferred is always the Command Word. The 16 bit value of the Command Word is written to the subsystem. Most simple system applications do not make use of the command word. The command word may be ignored by using address bit A6 (COMMAND WORD TRANSFER) as a qualifier in the subsystem's address decoding logic.

RECEIVE COMMANDS
Upon receipt of a valid receive command to the programmed RT address, the STIC will begin processing the message by transferring the received command word to the subsystem. The Data Words will be written to the subsystem as they are received off the incoming serial 1553 data bus. This creates a gap of approximately 20s between word transfers. Ensuring data consistency places an extra burden on a Remote Terminal. Paragraph 4.4.3.6 of MIL-STD-1553B states that if any data word within a message is invalid, the entire message shall be considered invalid. This requires that receive data be "double buffered" until the entire message is validated to ensure data consistency. Suppose the STIC was processing a command to receive 30 words and a noise burst on the 1553 bus caused the STIC to miss the last data word. According to MIL-STD-1553B, the 29 other words that were received properly in that message must be considered invalid.

SUBADDRESS
Every 1553 command provides a 5-bit address field referred to as a subaddress. The subaddress field is used to map data in the subsystem. The STIC's address outputs A11-A7 provide the subaddress field. There are 30 valid data subaddresses (subaddress 0 and 31 are reserved for mode commands) and each message may contain up to 32 data words. This allows for a linear address space of 960 transmit data words and 960 receive words. The address space may be expanded using logical addressing methods but most simple system applications do not exceed the bounds of the linear address space.

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SIMPLE INTERFACES TO SIMPLE SYSTEMS

D15 . . D0 ADDRESS DECODER STIC A13 . . A1 W0 W1

vcc
0

STORAGE LATCH
0 0

OUTPUT LATCH

Wn CS

NBGRT GBR LATCHED DISCRETE OUTPUTS STORAGE LATCH

0 0 0

vcc

OUTPUT LATCH

NBGRT GBR

NBGRT

GBR

ADDR_ENA DBGRT vcc

0 0 0

STORAGE LATCH

OUTPUT LATCH

NBGRT

GBR

FIGURE 2. RECEIVE DATA DOUBLE BUFFERING

The STIC provides an output signal called Good Block Received (GBR) to flag to the subsystem that a valid, legal, non-mode receive command with the correct number of data words has been received without a message error and successfully transferred to the subsystem. Figure 2 illustrates a receive data double buffering mechanism. Each 16-bit received data word is first clocked into a storage latch. Each latch contains a Set/Reset (S/R) latch to mark the fact that new data has been placed into the storage latch. The Good Block Received

(GBR) signal is then used to clock the stored data into the output latches. At first glance, one might think that the S/R latch and logic gate may be eliminated. Why not use GBR to clock all the output latches, not just the ones that were modified? A message prior to the current command may have been a receive message to a different subaddress with one invalid data word. If the Bus Controller did not "retry" the failed message the "invalid" data would still be stored in the temporary latches. This data should not be clocked to the output latches. The S/R latch, therefore serves to maintain data consistency by selectively clocking only

the output latches that were written to. Note that the S/R latch is not required if only one receive subaddress is implemented. Figure 3 illustrates a buffering scheme similar to the one shown in Figure 2, except the S/R latch has been eliminated. An assumption is made that the word count of the command word is the same as the number of latches associated with that subaddress. Based on this assumption the GBR pulse is passed to all latches for the current subaddress. To guarantee this assumption a PROM is used to implement command illegalization.

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AN/B-25 12/02-0

SIMPLE INTERFACES TO SIMPLE SYSTEMS

D15 . . D0 CS WC 0

STIC

A5 . . A1

WC 1

STORAGE LATCH

OUTPUT LATCH

WORD COUNT DECODER RXSA1 A13 . . A6 RXSA2 SUBADDRESS DECODER

LATCHED DISCRETE OUTPUTS

STORAGE LATCH ILLEGALIZATION PROM ILLCMD GBR ADDR_ENA DBGRT STORAGE LATCH

OUTPUT LATCH

OUTPUT LATCH

WC 0 = (WORD COUNT = 0) WC 1 = (WORD COUNT = 1) RXSA1 = (BROADCAST = 0) ( T /R = 0 ) (SUBADDRESS = 1) (DATA / COMMAND = 1) RXSA2 = (BROADCAST = 0) ( T /R = 0 ) (SUBADDRESS = 2) (DATA / COMMAND = 1)

FIGURE 3. ADDRESS DECODERS

Figure 3 shows two separate address decoders for the purpose of illustration. The first address decoder is used to indicate which word within the current message is being transferred (based on word count outputs A5..A1). The second address decoder generates two select outputs: receive subaddress #1 (RXSA1) and receive subaddress #2 (RXSA2). These select outputs will remain valid while the GBR output pulse is asserted. This allows the GBR pulse to clock the output latches for the current subaddress. Note that all or most of the interface logic shown may be combined into a single programmable logic device (PLD). Also note that Figures 2 or 3 do not use the STIC's write (WRT) output signal. Data Device Corporation www.ddc-web.com

This is because the direction of the data word transfers is known from address bit 12 (Transmit/Receive) and is included as a term in the address decoding equations Transmit messages will always read data from the subsystem and receive messages will always write data to the subsystem. Figure 4 illustrates an interface between the STIC and two DSC-11524s. A DSC11524 is a 16-Bit digital to synchro converter (DSC) from DDC. The concepts used in this example apply to any receive interface circuit. The DSC-11524 input has 16-bit double buffered transparent latches built in. The first latch will be used to hold the 16-bit data value until the receive message is validated.

The address decoder used in this example generates three outputs: subaddress #1 select (SEL1), write pulse #O (WRO), and write pulse #1 (WR1). The circuit is designed to receive two data words to non-broadcast subaddress 1. Upon detecting a valid receive command, the STIC will begin processing the incoming message. The address lines A13..A7 will be updated to reflect the current command (based on broadcast/non-broadcast, transmit/receive, and subaddress). Address lines A6..A1 will clear to logic 0 for the first subsystem transfer (the 16-bit command word). This example ignores the Command Word by using address line A6 (data/command) as a qualifier in the address decoder.

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LM D 15 . . D 0 LL CS STIC A 13 . . A 1 W0 W1 LA DSC- 11524 SYNCHRO OUTPUT D/S CONV

SEL 1 ADDRESS DECODER GBR ADDR_ENA DBGRT PLD LL LA DSC- 11524 SYNCHRO OUTPUT LM D/S CONV

WR0 = SEL1 ( DATA / COMMAND = 1 ) (WORD COUNT = 0) WR0 = SEL1 ( DATA / COMMAND = 1 ) (WORD COUNT = 1) SEL1 = ( BROADCAST = 0 ) ( T / R = 0 ) ( SUBADDRESS = 1 )

FIGURE 4. STIC & DSC-11524 INTERFACE

After completion of the Command Word transfer, the STIC will set address line A6 (data/command) to logic 1 indicating that the next transfer will be a Data Word. The STIC will present the first received Data Word with a value on address lines A5..A1 (the word count) of 0. The value of the address bus during the first Data Word transfer will cause the address decoder to use the WRO select line. The STIC's Chip Select (CS) output provides a pulse during the data transfer used to strobe the data into the selected latch. Following each data word transfer, the value on address lines A5..A1 will increment by 1, preparing for the next data word transfer. At the end of a valid, legal receive message, the STIC will use the Good Block Received signal (GBR). GBR is gated with the subaddress #1 select line (SEL1) to generate a latch update pulse to the converters. If there was an error in the message, the GBR pulse

would be suppressed and the latches in the converter would not be updated.

TRANSMIT COMMANDS
Transmit command circuitry is slightly simpler than that required for receive commands. Figure 5 makes use of a simple address decoder to generate output enable signals to the appropriate tri-state buffer as the transmit data words are required (approximately every 20s during a transmit message). The tri-state buffers enable the subsystem's 16-bit data words onto the parallel data bus. The STIC in turn reads these values and transmits them over the 1553 serial bus. The use of a latching tri-state buffer to drive the subsystem data onto the STIC's data bus will provide stable parallel data during the transfer. The latched interface will meet the STIC's transfer timing specifications, and preclude any problems associated with metastability. Figure 5 makes use of 74LS373 buffers. Note that

output enable and the latch control inputs to the '373 are tied together. This does not eliminate all time problems but does prevent the data from changing while the STIC is reading it. This requirement is very application dependent (e.g., not a problem for switch closures but could be a problem reading an 8-bit or 16-bit binary number). Many devices, such as analog to digital (A/D) converters require an input trigger before data may be read. The delay times on some of these devices may be very large. Figure 6 shows the STIC's data bus request output (DBREQ) being used to initiate a conversion by asserting the ENCODE input on an ADC-0300 A/D converter. The data ready output signal from the A/D is used as the data bus grant (DBGRT) input to the STIC. The STIC provides several signals that may be used to synchronize subsystem activity to the 1553 bus. New Bus Grant AN/B-25 12/02-0

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SIMPLE INTERFACES TO SIMPLE SYSTEMS

D 15 . . D 0 OEG RD0 STIC A 13 . . A 1 RD1 RDn OEG CS ADDRESS DECODER BUFFER BUFFER

BUFFERED DISCRETE INPUTS

ADDR_ENA

DBGRT

OEG BUFFER

FIGURE 5. TRANSMIT COMMAND CIRCUITRY

(NBGRT) is an active low output pulse asserted to indicate that the STIC is beginning to process a new command. In Command (INCMD) is an active low output that indicates that the STIC is currently processing a message. INCMD is driven low after the receipt of a valid command to the STIC and remains low until after the STIC has responded to the command. Figure 7 shows an interface between the STIC and two SDC-14620s. An SDC14620 is a dual 16-Bit synchro-to-digital converter (SDC) from DDC. The SDC14620's specifications state the output data is not valid for a minimum of 500 ns after the inhibit lines are asserted low. To meet this timing criteria an approach similar to that used in Figure 6 could be used, in which the DBREQ output would inhibit the converters. This method would, however, require an external circuit to generate the delay from DBREQ to DBGRT. This interface uses the signal INCMD to inhibit the synchro converters during the Data Device Corporation www.ddc-web.com

entire message. This has the added effect of inhibiting all four SDC channels simultaneously, providing the same sampling time, which may be useful in some applications. The address decoder used in Figure 7 is similar to those discussed in the previous examples. The read outputs (RD3..RD0) are generated based on the value of the address bus and are only driven active during data transfers (when CS is low). The SDC-14620 provides four control signals for use in enabling its built-in data buffers. EM is used to enable the Most Significant Byte, while EL is used to enable the Least Significant Byte. There are separate EM and EL signals for each of the two independent converters contained within the SDC-14620. The worst case propagation delay from EM and EL going low to the parallel output data valid is 150 ns maximum. Running at 16 MHz, the STIC allows for a propagation delay from going low until read data must be valid of 240 ns maxi-

mum. The propagation delay through the address decoder must be (240 ns - 150 ns) = 90 ns or less.

STATUS BITS
The STIC allows the subsystem to set or clear certain bits in the remote terminal status response. The subsystem flag (SSFLAG) bit is used to indicate that there is a failure within the subsystem. The SSFLAG input may be driven by the output of a built-in-test circuit. The service request (SERVREQ) bit is used to indicate to the bus controller that an asynchronous event has occurred or that further processing is required. The bus controller will normally follow a service request with a mode transmit vector word. Therefore, implementation of the SERVREQ bit requires implementation of a vector word. The BUSY bit may be set by the subsystem to indicate to the bus controller that the remote terminal is currently unable to process messages. MIL-STD-1553B Notice 2 discourages use of the Busy bit. AN/B-25 12/02-0

SIMPLE INTERFACES TO SIMPLE SYSTEMS

D 15 . . D 0

CS ENABLE STIC A 13 . . A 1 ANALOG ADDRESS DECODER INPUT RD0 DATA

DBGRT DATA READY DBREQ ENCODE

ADDR_ENA

ADC-00300

FIGURE 6. STIC & ADC-00300 INTERFACE

COMMAND ILLEGALIZATION
The STIC has the ability to implement command illegalization through the use of an external PROM or PLD. Upon receipt of an "illegal" command, the STIC will respond with the Message Error bit set in the Status Word, indicating to the bus controller that the command was illegal. The primary purpose of illegal commands is in the area of system integration to help troubleshoot bus controller software. Most remote terminals are designed to accept a limited number of commands. If a bus controller sends a command to a remote terminal that the terminal was not designed to process, the terminal would then respond with a Status Word indicating that the command was illegal. An illegal command response is normally an indication of an error in the bus controller message.

circuitry. All terminal related mode commands such as transmit last command, transmit status word, inhibit terminal flag, inhibit transmitter, etc are all handled internally by the STIC. Subsystem dependent mode commands such as mode transmit vector word may be implemented by the designer, if these functions are required.

tinguishing between broadcast and nonbroadcast messages. The STIC has address line A13 high to indicate a broadcast message. MIL-STD-1553B Notice 2 paragraph 30.7 states that a remote terminal is required to implement a data wraparound subaddress. Subaddress 30 (11110) is recommended as the wraparound subaddress. The wraparound subaddress must be designed such that N number of data words may be received to that subaddress and then the same data words may be transmitted from that same subaddress, where N is the maximum word count defined by the remote terminal. The wraparound subaddress requires that N readback latches be mapped into the address space of the remote terminal. To minimize the amount of circuitry required, it is desirable to keep the maximum word count as low as possible. A simple system may make use of 29 single word subaddresses (remember 00000 and 11111 are reserved for mode commands and 11110 is reserved for wraparound). The use of single word subaddresses will require only a single 16-bit read/write latch for wraparound. AN/B-25 12/02-0

SELF TEST
The STIC performs a continuous on-line loopback self test. The transmitter and receiver sections of the STIC are completely independent. While the STIC is actively transmitting on the 1553 bus, the receiver section is still active. The loopback test consists of a validity check (encoding, bit count, parity) on every word that is transmitted on the 1553 bus by the STIC, and a full 16-bit comparison of the last transmitted word with the last received word at the end of every nonbroadcast message.

MODE COMMANDS
But what about mode commands? It must require additional logic to implement mode commands, right? No, the STIC implements all required dual redundant 1553 mode codes with no external Data Device Corporation www.ddc-web.com

COMPLIANCE TO MIL-STD-1553B NOTICE 2

MIL-STD-1553B Notice 2 requires a remote terminal that implements the broadcast function have the ability of dis-

SIMPLE INTERFACES TO SIMPLE SYSTEMS

ADDRESS DECODER STIC A 13 . . A 1 RDO RD1 RD2 RD3 CS INH - A INH - B SDC-14620 EM - A EL - A EM - B EL - B

SYNCHRO INPUT # 1

SYNCHRO INPUT # 2

INCMD

DBGRT

SYNCHRO INPUT # 3 EM - A EL - A EM - B EL - B SYNCHRO INPUT # 4

INH - A INH - B SDC-14620 RD0 = ( BROADCAST = 0 ) ( T/R =1 ) ( SUBADDRESS = 2 ) ( DATA/COMMAND = 1) ( WORD COUNT = 0 ) RD1 = ( BROADCAST = 0 ) ( T/R =1 ) ( SUBADDRESS = 2 ) ( DATA/COMMAND = 1) ( WORD COUNT = 1 ) RD2 = ( BROADCAST = 0 ) ( T/R =1 ) ( SUBADDRESS = 2 ) ( DATA/COMMAND = 1) ( WORD COUNT = 2 ) RD3 = ( BROADCAST = 0 ) ( T/R =1 ) ( SUBADDRESS = 2 ) ( DATA/COMMAND = 1) ( WORD COUNT = 3 )

FIGURE 7. STIC & SDC-14620 INTERFACE

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AN/B-25 12/02-0

The information in this application note is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice.

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AN/B-25 12/02-0

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FI

RM

REG