Xilinx ISE Version 12 - Downloading to the FPGA - The final stage!

Target Harware Once the logical behaviour of the VHDL code has been verified through simulation then the design can then be progressed through to Synthesis. Up to now the development has been carried out purely in a "Soft" environment.

Real devices come in different packages with each package having a number of input/output pins, VDD & VSS (Power and Ground) pins, and what are called JTAG pins that allow the device to be configured to fit the design in question. Packages in turn go on Printed Circuit Boards (PCBs) to form an overall system. Some pins may route to LEDs - Some may be connected to switches - others may provide an input clock.

The Board shown here is the Digilent Spartan-3.

Making sure that the "implementation" button is selected in the Hierarchy View And that the correct top level entity is also selected Then using the "Project > New Source" wizard Select Implementation Constraints File And enter a File Name... (Normally the file name is the same as the system, or top level, entity for the design being implemented) And then click "Next >" and then "Finish" in the final window to confirm.

Selecting the "UCF" file in the Hierarchy Window and double clicking "Edit Constraints" in the Processes window will open an empty text edit window: Link Signal names to Pins (UCF) So that the design being created may function correctly on the hardware then the Signal names, or NETS, defined and used within the VHDL may be linked to specific Pins on the device. This may be achieved in various ways according to the version of WebPack being used - but in general the pin mapping information is entered into the "User Constraints File" (.UCF) as a source file within the Project For pin assignments to specific resources on the board such as Switches, Buttons, LEDs, and the Seven Segment Display, please refer to the Spartan 3 Reference Manual.

Page 1 of 3

Xilinx ISE Version 12 - Downloading to the FPGA - The final stage!

"Translate", "Map" and "Place and Route" Device
The remaining tasks of :

Synthesize... Convert the VHDL model into a hardware logic netlist - ie gates and wires, Translating the design netlist into a form that may be then go through Mapping onto the Logic Blocks found on the device. The location of the actual blocks that will be used and interconnected is achieved for an FPGA based design through the use of Place and Route software.

Making sure that the Top Level entity is selected in the Hierarchy window and that "implementation" is also selected in the "Processes" window.... if you Click the '+' sign next to Implement Design then subcommands appear... Double click "Synthesize" - After a short time a green tick should appear. (If there are any Errors then they need to be corrected before proceeding.) Next, Double click "Implement Design" - Further green ticks should appear next to "Translate", "Map" and "Place & Roure". (Again if there are any errors [such as a mistake in the UFC file] then these will need correction and the "implement Design" process repeated. A Double click on "Generate Programming File" creates a .BIT file that holds the configuration data for the FPGA. Configure the FPGA

First make sure that the Power Supply and the Serial Cable to the Programming Port is correctly connected to the FPGA board - and then switch on the power supply. Double Click "Manage Configuration" to open the iMPACT window. The software first needs to detect the FPGA on the board Double click "Boundary Scan" and an empty window opens

Page 2 of 3

Xilinx ISE Version 12 - Downloading to the FPGA - The final stage!

Next "right click" in the empty Boundary Scan window and on the pop-up menu that appears select "Intialize Chain" The systems will then communicate with the Board via the programming cable and identify any devices connected. On the Spartan 3 board two devices should be detected The FPGA and a Serial Prom (not used) The system will then ask if you wish to continue and assign a configuration file. Click "Yes" to continue For the FPGA In the "Assign New Configuration File" prompt select the top_level_name.bit (You may need to navigate to the correct location to find the active Project Folder on your N: Drive) and click Open The "Assign New Configuration File" prompt will appear for the second device - Click "Bypass" to ignore the SPROM. (The System may ask to confirm the device properties Click OK to continue)

FinallyClick the FPGA package symbol in the boundary scan window (it should turn green) And then "Right Click" and select "Program"

A "Program Succeeded" message should appear. (Sometimes the configuration file does not download correctly where one then gets "Program Fail". If this occurs try another "Program" command.) The FPGA will automatically detect any configuration data so there is no need to reset the device to download a new configuration file.

Page 3 of 3