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Ex.No:1 Date:
AIM:

IMPLEMENTATION OF 8 BIT ALU IN FPGA

To design and implement vhdl code for 8 bit alu using FPGA.

ALGORITHM:

Step1: Start the program Step2: Declare the input and output ports Step3: Begin the architectural behaviour Step4: If op=000, perform logical and operation, op=100, perform logical nand operation, op=001, perform logical or operation, op=101, perform logical nor operation, op=011, perform addition operation, op=110, perform subtraction operation. Step5: Assign logical and arithmetic operation results to temp. Step6: Check whether if temp="00000000" , display zero=1 otherwise zero=0 Step7: Stop the program.

PROGRAM:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity alu is Port ( a,b : in STD_LOGIC_VECTOR (7 downto 0); op : in STD_LOGIC_VECTOR (2 downto 0); zero : out STD_LOGIC; f : out STD_LOGIC_VECTOR (7 downto 0)); end alu; architecture Behavioral of alu is begin process(op) variable temp:STD_LOGIC_VECTOR (7 downto 0); begin case op is when "000"=>temp:=a and b; when "100"=>temp:=a nand b;

when "001"=>temp:=a or b; when "101"=>temp:=a nor b; when "010"=>temp:=a + b; when "110"=>temp:=a - b; when "111"=>if a<b then temp:="11111111"; else temp:="00000000"; end if; when others=>temp:=a-b; end case; if temp="00000000" then zero<='1'; else zero<='0'; end if; f<=temp; end process; end Behavioral;

RTL SCHEMATIC:

OUTPUT WAVEFORM:

RESULT:

Thus the vhdl code for 8 bit ALU was verified and implemented using FPGA.

Ex.No:2 Date:
AIM:

8 BIT MULTIPLIER USING VHDL

To design and test the VHDL code for 8 bit multiplier.

ALGORITHM:

Step1: Start the program Step2: Declare the input ports Step3: Declare the components of multiplier Step4: Declare signal a 7 downto 0 Step5: Declare signal b 7 downto 0 Step6: If a<=00000011 b<=00000010 then wait Step7: Stop the program

PROGRAM

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity multiplier is end multiplier; architecture Behavioral of multiplier is --component declaration for the unit under test COMPONENT mul Port ( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0) ; mult_out : out STD_LOGIC_VECTOR(15 downto 0)); end component; signal a:std_logic_vector(7 downto 0):=(others=>'0'); signal b:std_logic_vector(7 downto 0):=(others=>'0'); --outputs; signal mult_out:std_logic_vector(15 downto 0);

begin --instantiate the unit under test(UUT) uut:mul PORT MAP(a=>b,b=>b,mult_out=>mult_out); tb:PROCESS begin a<="00000011"; b<="00000010"; --wait 10ns for global reset to finish --wait for 10ns; a<="00000010"; b<="00000010"; --wait for 10ns; wait; --will wait forever end PROCESS; end Behavioral;

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RESULT: Thus the VHDL code for 8 bit multiplier was designed and tested.

Ex.No:3 Date:
AIM:

256 SRAM MEMORY USING VHDL

To design and test the 256 SRAM memory in VHDL.

ALGORITHM:

Step1: Start the program Step2: Declare input ports Step3: Begin architectural behavior Step4: when wr_en=0, then assign processor<=memory(addr); Step5: If clk=1, then memory(addr)<=processor Step6: Stop the program

PROGRAM:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- Any Xilinx primitives in this code.

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--library UNISIM; --use UNISIM.VComponents.all; entity sram is

entity sram is generic(bits:integer:=8; words:integer:=256); Port ( clk : in STD_LOGIC; wr_en : in STD_LOGIC; addr : in integer range 0 to words -1; processor : inout STD_LOGIC_VECTOR (bits 1 downto 0)); end sram;

architecture Behavioral of sram is type vector_array is array(0 to 1)of std_logic_vector(bits 1 downto 0); signal memory:vector_array; begin process(clk,wr_en) begin if(wr_en='0')then processor<=memory(addr); else processor<=(others<='z'); if(clk'event and clk='1')then memory(addr)<=processor; end if; end if; end process;

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end Behavioral;

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RESULT: Thus the 256 SRAM memory using VHDL was designed and tested.

Ex.No:4 Date:

IMPLEMENTATION OF 4 BIT SLICED PROCESSOR IN FPGA

AIM: To design and implement the vhdl code for 4 bit sliced processor using FPGA.

ALGORITHM:

Step1: Start the program Step2: Declare the input ports for bit processor Step3: Declare the output ports for bit processor Step4: Component declaration of tristate buffer, registers, 2 to 4 decoder, 1 to 2 decoder, upcounter Step5: Declare the ports Step6: Assign the specific operations for the pins Step7: Stop the program

PROGRAM:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sliced is Port (data: in STD_LOGIC_VECTOR (3 downto 0) ; reset,w : in STD_LOGIC; clock,sel,rx,ry : in STD_LOGIC; f : in STD_LOGIC_VECTOR (1 downto 0); done : inout STD_LOGIC; buswires : inout STD_LOGIC_VECTOR (3 downto 0)); end sliced; architecture Behavioral of sliced is signal rin,rout:STD_LOGIC_VECTOR (0 to 1); signal clear,high,addsub:STD_LOGIC; signal extern,ain,gin,gout,frin:STD_LOGIC; signal count,zero:STD_LOGIC_VECTOR (1 downto 0); signal t,i:STD_LOGIC_VECTOR (0 to 3); signal x,y:STD_LOGIC_VECTOR (0 to 1); signal r0,r1:STD_LOGIC_VECTOR (3 downto 0); signal a,sum,g:STD_LOGIC_VECTOR (8 downto 0); signal func,funcreg:STD_LOGIC_VECTOR (1 to 4); signal clk:STD_LOGIC; component tristate generic(n:integer:=4); port(x:in STD_LOGIC_VECTOR (n-1 downto 0);

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e:in STD_LOGIC; f:out STD_LOGIC_VECTOR (n-1 downto 0)); end component; component regn generic(n:integer:=4); port(r:in STD_LOGIC_VECTOR (n-1 downto 0); rin,clk:in STD_LOGIC; q:out STD_LOGIC_VECTOR (n-1 downto 0)); end component; component dec2to4 port(w:in STD_LOGIC_VECTOR (1 downto 0); en:in STD_LOGIC; y:out STD_LOGIC_VECTOR (3 downto 0)); end component; component dec1to2 port(b:out STD_LOGIC_VECTOR (1 downto 0); a,en:in STD_LOGIC); end component;

component upcount port(clear,clk:in STD_LOGIC; q:inout STD_LOGIC_VECTOR (1 downto 0)); end component; begin zero<="00"; high<='1'; clk<=clock and sel;

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clear<=reset or done or (not w and t(0)); counter:upcount port map(clear,clk,count); dect:dec2to4 port map(count,high,t); func<=f&rx&ry; frin<=w and t(0); functionreg:regn generic map(n=>4) port map(func,frin,clk,funcreg); deci:dec2to4 port map(funcreg (1 to 2),high,i); decx:upcount port map(funcreg (3),high,x); decy:upcount port map(funcreg (4),high,y); extern<=i(0) and t(1); done<=((i(0) or i(1)) and t(1)) or ((i(2) or i(3)) and t(3)); ain<=(i(2) or i(3)) and t(1); gin<=(i(2) or i(3)) and t(2); gout<=(i(2) or i(3)) and t(3); addsub<=i(3); regent: for k in 0 to 1 generate rin(k)<=((i(0) or i(1)) and t(1) and x(k)) or ((i(2) or i(3)) and t(3) and x(k)); rout(k)<=((i(1) or t(1)) and y(k)) or ((i(2) or i(3)) and ((t(1) and x(k)) or (t(2) and y(k)))); end generate regent; tri_extern:tristate port map(data,extern,buswires); reg0:regn port map(buswires,rin(0),clk,r0); reg1:regn port map(buswires,rin(1),clk,r1); tri0:tristate port map(r0,rout(0),buswires); tri1:tristate port map(r1,rout(1),buswires); rega:regn port map(buswires,ain,clk,a);

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alu: with addsub select sum<= a + buswires when '0',a - buswires when others; regg:regn port map(sum,gin,clk,g); trig:tristate port map(g,gout,buswires); end Behavioral;

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RESULT:

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Thus the vhdl code for Sliced Processor was verified and implemented using FPGA.

Ex.No:5 Date:

IMPLEMENTATION OF ELEVATOR CONTROLLER

AIM: To design and implement the vhdl code for elevator controller.

ALGORITHM:

Step1: Start the program Step2: Declare the input ports for bit processor Step3: Begin the architectural behaviour Step4: If (stbevent&stb=0) then flr<=f Step5: else if(clkevent & clk=1) then at_flr<=here; Step6: Stop the program.

PROGRAM:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

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---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity elevator is Port ( f : in STD_LOGIC_VECTOR (4 downto 0); clk,here,stb : in STD_LOGIC; flr : out STD_LOGIC_VECTOR (4 downto 0); at_flr,nr_flr : out STD_LOGIC); end elevator; architecture shaft_logic of elevator is begin process(stb,f,clk,here)begin if(stb'event and stb='0')then flr<=f;end if; --note that the flr flipflops are clocked by a negative. --transition of stb with a PAL you can have only one, --positive edge-triggered clock with CPLDS you may have --several clocks. if(clk'event and clk='1')then at_flr<=here; --at_flr is just a synchronised version of "here" if stb='0'then nr_flr<='1'; else if here<='1' then nr_flr<='0'; end if; --the signal nr_flr is set when the elevator nears a floor --(as determined by the STB signal) and is cleared when it reaches --the floor(as indicated by the "here" signal). end if;end if;

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end process; end shaft_logic; RTL SCHEMATIC:

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OUTPUT WAVEFORM:

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RESULT:

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Thus the vhdl code for Elevator Controller was verified and implemented using FPGA.

Ex.No:6 Date:

STUDY OF PHASE LOCKED LOOP

AIM: Study of Phase Locked Loop.

THEORY:

A Phase-Locked Loop or phase lock loop (PLL) is a control system that tries to generate an output signal whose phase is related to the phase of the input reference signal. Phase-locked loop circuits compares the phases of the input signal with the phase signal derived from its output oscillator signal and adjust the frequency of its oscillator to keep the phases matched.

Frequency is the derivative of the phase. Keeping the input and output phase in lock step implies keeping the input and output frequencies in lock step. Consequently, a phase locked loop can track an input frequency, or it can generate a frequency that is a multiple of input frequency. The former property is used for demodulation, and the latter property is used for indirect frequency synthesis.

Phase-locked loops are widely used in radio, telecommunication, computer and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or

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distribute clock timing pulses in a digital logic designs such as microprocessors. Since a single integrated circuit can provide a complete phase-locked loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many giga hertz.

STRUCTURE AND FUNCTION:

Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure.

A both analog and digital PLL circuit includes three basic elements: A phase detector A variable electronic oscillator, and A feedback path (which often includes a frequency divider).

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DIGITAL PHASE LOCKED LOOP (DPLL):

A digital phase-locked loop operates similarly to an analog phase locked loop, but is implemented entirely using digital circuits. In place of a voltage controlled oscillator (VCO), a DPLL uses local reference clock and a variable dividing counter under digital control to create equivalent oscillator function.

DPLLs are easier to design and implement, and are less sensitive to voltage noise than the analog PLLs, however they typically suffer from higher phase noise due to the quantization error of using non analog oscillator. For this reason digital phase-locked loops are not well suited to the synthesizing higher frequencies are handling higher frequency reference signal. DPLLs are sometimes used for data recovery.

ANALOG PHASE-LOCKED LOOP:

BASIC DESIGN:

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Phase-locked loop Block Diagram A phase detector compares two input signals and produces an error signal which is proportional to their phase difference. The error signal is then low pass filtered and used to derive a voltage controlled oscillator (VCO) which creates an output frequency. The output frequency is feed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the error signal will increase, deriving the VCO frequency in the opposite direction has to reduce error. Thus the output is locked to the frequency at the other input. This input is called the reference and is often derived from a crystal oscillator, which is very stable in frequency.

Analog phase-locked loops are generally built with the phase detector, low pass filter and the voltage controlled oscillator (VCO) placed in a negative feedback closed loop configuration. They may be a frequency divider in a feedback path or in a reference path or both, in order to make the PLLs output signal frequency an integer multiple of the reference. A non integer multiple of the reference frequency can be created by replacing the simple divide-by-N counter in the feedback path with the programmable

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pulse swallowing counter. This technique is usually referred to as fractionalN synthesizer or fractional-N PLL.

The oscillator generates a periodic output signal. Assume that initially the oscillator is at nearly the same frequency as the reference signal. Then, if the phase from the oscillator falls behind that of the reference, the phase detector changes the control voltage of the oscillator, so that it speeds up. Likewise, if the phase creeps ahead of the reference, phase detector changes the control voltage to slow down the oscillator. Since initially the oscillator may be far from the reference frequency, practical phase detectors may also respond to frequency differences, so as to increase the lock-in range of allowable inputs.

The block commonly called a low pass filter generally has two distinct functions.

The primary function is to determine loop dynamics, also called stability. This is how the loop responds to disturbances, such as changes in the reference frequency, changes of feedback divider, or at startup. Common considerations are the range over which the loop can achieve lock (pull-in range or lock range), how fast the loop achieves the lock (lock time or lockup time) and overshoot (damping). Depending on the application, this may require one or more of the following: a simple proportion (gain or attenuation), an integral (low pass filter) and/or derivative(high pass filter). Loop parameters commonly examine for this are the loop gain margin and phase margin. Common concepts in a control theory are used to design this function and are covered in the control system section.

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The second common consideration is limiting the amount of reference frequency energy (ripple) appearing at the phase detector output that is then applied to VCO controlled input. This frequency modulates the VCO and produces FM sidebands called reference spurious. The low pass characteristics of this block can be used to attenuate this energy, but at times a band reject notch may also be needed.

The design of this block can be dominated by either of this considerations or can be complex process juggling the interactions of the two.

Depending on the application, either the output of the controlled oscillator, or the control signal to the oscillator, provides the useful output of the PLL system.

It should also be noted that the feedback is not limited to a frequency divider. This element can be other elements such as a frequency multiplier, as mixer. The multiplier will make the VCO output a sub-multiple (rather than multiple) of the reference frequency. A mixer can translate the VFO frequency by a fixed offset. It may also be combination of these. An example being a divider following a mixer; this allows the divider to operate at a much lower frequency than the VCO without losses in loop gain.

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RESULT: Thus the Phase-Locked Loop was studied.