EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

VERIFICATION OF LOGIC GATES AIM: To develop VHDL code for the verification of Logic Gates, simulate it and verify the output using XILINX ISE 7.

ALGORITHM: Declare the name of design, entity and architecture body. Write the source code in VHDL. Compile the code and check for the errors. Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE: AND GATE: LOGIC DIAGRAM: TRUTH TABLE:

Input A 0 0 1 1 y<= a and b;

Input B 0 1 0 1

Output Y 0 0 0 1

EX No: NAME: SAGAYA GINOLIYA FERNANDO VHDL SOURCE CODE : --Design:AND GATE (ENTITY AND ARCHITECTURE). --Filename:andgate.vhd --Description:to implement AND gate. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3 AND GATE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity andgate is Port (a: in std_logic; b: in std_logic; y: out std_logic); end andgate; architecture Behavioral of andgate is begin y<= a and b; end Behavioral; SIMULATION REPORT:

REG No: 2913183 DATE:

SYNTHESIS REPORT:

EX No: NAME: SAGAYA GINOLIYA FERNANDO OR GATE: LOGIC DIAGRAM:

REG No: 2913183 DATE:

TRUTH TABLE:

Input A 0 0 1 y<= a or b; 1

Input B 0 1 0 1

Output Y 0 1 1 1

VHDL SOURCE CODE: --Design:OR GATE (ENTITY AND ARCHITECTURE). --Filename:orgate.vhd --Description:to implement OR gate. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3 OR GATE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity orgate is Port ( a : in std_logic; b : in std_logic; y : out std_logic); end orgate; architecture Behavioral of orgate is begin y<=a or b; end Behavioral;

EX No: NAME: SAGAYA GINOLIYA FERNANDO SIMULATION REPORT:

REG No: 2913183 DATE:

SYNTHESIS REPORT:

NOT GATE: LOGIC DIAGRAM: TRUTH TABLE:

Input A Output Y 0 1 y<= not a; 1 0

VHDL SOURCE CODE: --Design:NOT GATE (ENTITY AND ARCHITECTURE). --Filename:notgate.vhd --Description:to implement NOT gate. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3

EX No: NAME: SAGAYA GINOLIYA FERNANDO NOT GATE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity notgate is Port ( a: in std_logic; y: out std_logic); end notgate; architecture Behavioral of notgate is begin y<= not a; end Behavioral; SIMULATION REPORT:

REG No: 2913183 DATE:

SYNTHESIS REPORT:

NAND GATE: LOGIC DIAGRAM: TRUTH TABLE: Input A Input B Output Y 0 0 1 1 y<= a nand b; 0 1 0 1 1 1 1 0

EX No: NAME: SAGAYA GINOLIYA FERNANDO VHDL SOURCE CODE: --Design:NAND GATE (ENTITY AND ARCHITECTURE). --Filename:nandgate.vhd --Description:to implement NAND gate. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3 NAND GATE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL entity NANDGATE is Port ( a : in std_logic; b : in std_logic; y : out std_logic); end NANDGATE; architecture Behavioral of NANDGATE is begin y <=a nand b; end Behavioral; SIMULATION REPORT:

REG No: 2913183 DATE:

SYNTHESIS REPORT:

EX No: NAME: SAGAYA GINOLIYA FERNANDO NOR GATE: LOGIC DIAGRAM:

REG No: 2913183 DATE:

TRUTH TABLE:

Input A Input B Output C 0 0 1 y<= a nor b; 1 0 1 0 1 1 0 0 0

VHDL SOURCE CODE: --Design:NOR GATE (ENTITY AND ARCHITECTURE). --Filename:norgate.vhd --Description:to implement NOR gate. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3 NOR GATE:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity norgate is Port ( a : in std_logic; b : in std_logic; y : out std_logic); end norgate; architecture Behavioral of norgate is begin y<= a nor b; end Behavioral;

EX No: NAME: SAGAYA GINOLIYA FERNANDO SIMULATION REPORT:

REG No: 2913183 DATE:

SYNTHESIS REPORT:

XOR GATE:

LOGIC DIAGRAM:

TRUTH TABLE: Input A Input B Output Y 0 0 1 0 1 0 1 0 1 1 0

y<= a xor b;

VHDL SOURCE CODE: --Design:XOR GATE (ENTITY AND ARCHITECTURE). --Filename:xorgate.vhd --Description:to implement XOR gate. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3

EX No: NAME: SAGAYA GINOLIYA FERNANDO XOR GATE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xorgate is Port ( a : in std_logic; b : in std_logic; y : out std_logic); end xorgate; architecture Behavioral of xorgate is begin y<= a xor b; end Behavioral; SIMULATION REPORT:

REG No: 2913183 DATE:

SYNTHESIS REPORT:

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

XNOR GATE: LOGIC DIAGRAM: TRUTH TABLE: Input A Input B Output Y 0 0 1 1 y<= a xnor b; 0 1 0 1 1 0 0 1

VHDL SOURCE CODE: --Design:XNOR GATE (ENTITY AND ARCHITECTURE). --Filename:xnorgate.vhd --Description:to implement XNOR gate. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3 XNOR GATE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity XNORgate is Port ( a : in std_logic; b : in std_logic; y : out std_logic); end XNORgate; architecture Behavioral of XNORgate is begin y<= a xnor b; end Behavioral;

10

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SIMULATION REPORT:

SYNTHESIS REPORT:

RESULT: Thus the VHDL codes for the different logic gates were written, simulated. Synthesized and the outputs verified

11

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

HALF ADDER AND FULL ADDER AIM: To develop VHDL code for Half adder and Full adder, simulate it and verify the output using XILINX ISE 7.1i

ALGORITHM: Declare the name of design, entity and architecture body. Write the source code in VHDL. Compile the code and check for the errors. Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

HALF ADDER:

12

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE:

Input A 0 0 1 1

Input B 0 1 0 1

Output SUM 0 1 1 1

Output CARRY 0 0 0 1

VHDL SOURCE CODE: --Design:HALF ADDER(ENTITY AND ARCHITECTURE). --Filename:halfadder.vhd --Description:to implement HALF ADDER circuit using XOR and AND gates. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3 HALF ADDER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfadder is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end halfadder; architecture Behavioral of halfadder is begin sum<= a xor b; carry <= a and b; end Behavioral;

13

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SIMULATION REPORT:

SYNTHESIS REPORT:

FULL ADDER: LOGIC DIAGRAM:

14

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE:

Input A 0 0 0 0 1 1 1 1

Input B 0 0 1 1 0 0 1 1

Input C 0 1 0 1 0 1 0 1

Output SUM 0 1 1 0 1 0 0 1

Output CARRY 0 0 0 1 0 1 1 1

VHDL SOURCE CODE: --Design:FULL ADDER(ENTITY AND ARCHITECTURE). --Filename:fulladder.vhd --Description:to implement full adder using XOR and AND gates. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3

15

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

FULL ADDER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladder is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fulladder; architecture Behavioral of fulladder is signal p,q,r,s: std_logic; begin p <= a xor b; q <= a and b; r <= b and c; s <= c and a; sum <= p xor c; carry<= q or r or s; end Behavioral; SIMULATION REPORT:

16

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SYNTHESIS REPORT:

RESULT: Thus the VHDL codes for Half adder and Full adder were written, simulated, synthesized and the outputs verified.

17

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

HALF SUBTRACTOR AND FULL SUBTRACTOR AIM: To develop VHDL code for Half adder and Full Subtractor, simulate it and verify the output using XILINX ISE 7.1i

ALGORITHM: Declare the name of design, entity and architecture body. Write the source code in VHDL. Compile the code and check for the errors. Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM. Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE: HALF SUBTRACTOR:

18

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE:

Input A 0 0 1 1 VHDL SOURCE CODE:

Input B 0 1 0 1

Output DIFF 0 1 1 0

Output BORR 0 1 0 0

--Design:HALF SUBTRACTOR(ENTITY AND ARCHITECTURE). --Filename:halfsub.vhd --Description:to implement HALF SUBTRACTOR circuit using NOT,XOR and AND gates. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3 HALF SUBTRACTOR: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity halfsub is Port ( a : in std_logic; b : in std_logic; diff : out std_logic; borr : out std_logic); end halfsub; architecture Behavioral of halfsub is signal p:std_logic; begin p <= not a; diff <= a xor b; bor <= p and b; end Behavioral;

19

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SIMULATION REPORT:

SYNTHESIS REPORT:

20

EX No: NAME: SAGAYA GINOLIYA FERNANDO FULL SUBTRACTOR: LOGIC DIAGRAM:

REG No: 2913183 DATE:

TRUTH TABLE:

Input A 0 0 0 0 1 1 1 1

Input B 0 0 1 1 0 0 1 1

Input C 0 1 0 1 0 1 0 1

Output DIFF 0 1 1 0 1 0 0 1

Output BORR 0 1 1 1 0 0 0 1

21

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

VHDL SOURCE CODE: --Design:FULL SUBTRACTOR(ENTITY AND ARCHITECTURE). --Filename:fullsub.vhd --Description:to implement FULL SUBTRACTOR circuit using NOT,XOR,OR and AND gates. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3 FULL SUBTRACTOR:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fullsub is Port ( a : in std_logic; b : in std_logic; c : in std_logic; diff : out std_logic; borr : out std_logic); end fullsub; architecture Behavioral of fullsub is begin diff <= a xor b xor c; borr <= (not a and b) or (b and c) or (not a and c); end Behavioral;

22

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SIMULATION REPORT:

SYNTHESIS REPORT:

RESULT: Thus the VHDL codes for Half subtractor and Full subtractor were written, simulated, synthesized and the outputs verified.

23

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

ENCODER AND DECODER

AIM: To develop VHDL code for Encoder (8 x 3) and Decoder (2 x 4), simulate it and verify the output using XILINX ISE 7.1i

ALGORITHM: Declare the name of design, entity and architecture body. Write the source code in VHDL. Compile the code and check for the errors. Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM. Verify the output for all the combination of the input values.

24

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

LOGIC DIAGRAM & TRUTH TABLE: ENCODER:

TRUTH TABLE

D0 1 0 0 0 0 0 0 0

D1 0 1 0 0 0 0 0 0

D2 0 0 1 0 0 0 0 0

D3 0 0 0 1 0 0 0 0

D3 0 0 0 0 1 0 0 0

D4 0 0 0 0 0 1 0 0

D5 0 0 0 0 0 0 1 0

D6 0 0 0 0 0 0 0 1

X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1

Z 0 1 0 1 0 1 0 1

25

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

VHDL SOURCE CODE: --Design:3 to 8 LINE ENCODER(ENTITY AND ARCHITECTURE). --Filename:encoder.vhd --Description:to implement 3 to 8 LINE ENCODER using OR gates. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3

3 to 8 LINE ENCODER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder is Port ( d : in std_logic_vector(0 to 7); x : out std_logic; y : out std_logic; z : out std_logic); end encoder; architecture Behavioral of encoder is begin z <= d(1) or d(3) or d(5) or d(7); y <= d(2) or d(3) or d(6) or d(7); x <= d(4) or d(5) or d(6) or d(7); end Behavioral;

26

EX No: NAME: SAGAYA GINOLIYA FERNANDO SIMULATION REPORT:

REG No: 2913183 DATE:

SYNTHESIS REPORT:

27

EX No: NAME: SAGAYA GINOLIYA FERNANDO DECORDER: LOGIC DIAGRAM:

REG No: 2913183 DATE:

28

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE:

A 0 0 1 1

B 0 1 0 1

Enable 1 1 1 1

Z(0) 0 1 1 1

Z(1) 1 0 1 1

Z(2) 1 1 0 1

Z(3) 1 1 1 0

VHDL SOURCE CODE: --Design:3 to 8 LINE DECODER(ENTITY AND ARCHITECTURE). --Filename:decoder.vhd --Description:to implement 3 to 8 LINE DECODER using NOT and AND gates. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 :--Version:3.3 3 to 8 LINE DECODER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder is Port ( a : in std_logic; b : out std_logic; e : out std_logic; z : out std_logic_vector(0 to 3); end decoder; architecture archdec of decoder is signal abar,bbar : std_logic; begin Z(0) <= (abar and bbar nad e); Z(1) <=(abar and b and e); Z(2) <=(a and bbar abd e); Z(3)<=(a and b and e); end archdec;

29

EX No: NAME: SAGAYA GINOLIYA FERNANDO SIMULATION REPORT:

REG No: 2913183 DATE:

SYNTHESIS REPORT:

RESULT: Thus the VHDL codes for encoder and decoder were written, simulated, synthesized and the outputs verified.

30

EX No: NAME: SAGAYA GINOLIYA FERNANDO MULTIPLEXER AND DE-MULTIPLEXER AIM:

REG No: 2913183 DATE:

To develop VHDL code for Multiplexer (4 x 1) and De-Multiplexer (1 x 4), simulate it and verify the output using XILINX ISE 7.1i ALGORITHM: Declare the name of design, entity and architecture body. Write the source code in VHDL. Compile the code and check for the errors. Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE: MULTIPLEXER:

31

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE: SELECT INPUT S0 0 0 1 1 S1 0 1 0 1 OUTPUT Y D(0) D(1) D(2) D(3)

VHDL SOURCE CODE: --Design:MULIPLEXER(ENTITY AND ARCHITECTURE). --Filename:multiplexer.vhd --Description:to implement MULTIPLEXER circuit . --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3 MULTIPLEXER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( d0 : in std_logic; d1 : in std_logic; d2 : in std_logic; d3 : in std_logic; s0 : in std_logic; s1 : in std_logic; y : out std_logic); end mux; architecture Behavioral of mux is begin y<=((d0 and (not s0)and (not s1))or (d1 and (not s0) and s1)or (d2 and s0 and(not s0)) or (d3 and s0 and s1)); end Behavioral;

32

EX No: NAME: SAGAYA GINOLIYA FERNANDO SIMULATION REPORT:

REG No: 2913183 DATE:

SYNTHESIS REPORT:

33

EX No: NAME: SAGAYA GINOLIYA FERNANDO DE-MULTIPLEXER: LOGIC DIAGRAM:

REG No: 2913183 DATE:

TRUTH TABLE:

INPUT Din 1 1 1 1 S0 0 0 1 1 S1 0 1 0 1 Y0 1 0 0 0

OUTPUT Y1 0 1 0 0 Y2 0 0 1 0 Y3 0 0 0 1

34

EX No: NAME: SAGAYA GINOLIYA FERNANDO VHDL SOURCE CODE: --Design:DEMULIPLEXER(ENTITY AND ARCHITECTURE). --Filename:demux.vhd --Description:to implement DEMULTIPLEXER circuit . --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 :--Version:3.3 DEMULTIPLEXER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux is Port ( e : in std_logic; s0 : in std_logic; s1 : in std_logic; din : in std_logic; y0 : out std_logic; y1 : out std_logic; y2 : out std_logic; y3 : out std_logic); end demux; architecture Behavioral of demux is begin y0<=(din and (not s0)and (not s1)and e); y1<=(din and s0 and(not s1)and e); y2<=(din and (not s0)and s1 and e); y3<=(din and s0 and s1 and e); end Behavioral;

REG No: 2913183 DATE:

35

EX No: NAME: SAGAYA GINOLIYA FERNANDO SIMULATION REPORT:

REG No: 2913183 DATE:

SYNTHESIS REPORT:

RESULT: Thus the VHDL codes for multiplexer and de-multiplexer were written, simulated, synthesized and the outputs verified.

36

EX No: NAME: SAGAYA GINOLIYA FERNANDO DESIGN OF CODE CONVERTERS AIM:

REG No: 2913183 DATE:

To develop VHDL code for Code Converters, simulate it and verify the output using XILINX ISE 7.1i ALGORITHM: Declare the name of design, entity and architecture body. Write the source code in VHDL. Compile the code and check for the errors. Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM Verify the output for all the combination of the input values.

CODE CONVERTER (BCD TO GRAY): LOGIC DIAGRAM:

37

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE:

BCD B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

GRAY G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

VHDL SOURCE CODE: --Design:CODE CONVERTOR(ENTITY AND ARCHITECTURE). --Filename:convertor.vhd --Description:to implement CODE CONVERTOR using XOR gate. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3

38

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

CODE CONVERTER (BCD TO GRAY):

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity converter is Port ( b : in std_logic_vector(0 to 3); g: out std_logic_vector(0 to 3)); end converter; architecture Behavioral of converter is begin g(0) <= b(0); g(1) <=b(1) xor b(0); g(2) <=b(2) xor b(1); g(3) <=b(3) xor b(2); end Behavioral;

SIMULATION REPORT:

39

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SYNTHESIS REPORT:

CODE CONVERTER (GRAY TO BINARY): LOGIC DIAGRAM:

40

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE:

GRAY G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 B0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

BCD B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

VHDL SOURCE CODE: --Design:CODE CONVERTOR(ENTITY AND ARCHITECTURE). --Filename:convertor.vhd --Description:to implement CODE CONVERTOR using XOR gate. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3

41

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

CODE CONVERTER (GRAY TO BINARY): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity graytobinary is Port (b : inout std_logic_vector(0 to 3); g: in std_logic_vector(0 to 3)); end binarytoexcess; architecture Behavioral of graytobinary is begin b(0) <= g(0) xor b(1); b(1) <=g(1) xor b(2); b(2) <=g(2) xor b(3); b(3) <=not g(3); end Behavioral;

SIMULATION REPORT:

42

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SYNTHESIS REPORT:

RESULT: Thus the VHDL codes for Code Converters were written, simulated, synthesized and the outputs verified.

43

EX No: NAME: SAGAYA GINOLIYA FERNANDO DESIGN OF FILP FLOPS AIM:

REG No: 2913183 DATE:

To develop VHDL code for Flip Flops (SR, JK, D,T), simulate it and verify the output using XILINX ISE 7.1i ALGORITHM: Declare the name of design, entity and architecture body. Write the source code in VHDL. Compile the code and check for the errors. Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

SR FLIP FLOP:

44

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE:

Q (t) 0 0 0 0 1 1 1 1

S 0 0 1 1 0 0 1 1

R 0 1 0 1 0 1 0 1

Q (t+1) 0 0 1 X 1 0 1 X

SR FLIPFLOP: VHDL SOURCE CODE : --Design:SR FLIPFLOP (ENTITY AND ARCHITECTURE). --Filename:srff.vhd --Description:to implement NAND gate. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3

45

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SR FLIPFLOP: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity srff is Port (s: in std_logic; r: in std_logic; rst: out std_logic clk: out std_logic; q:inout std_logic; qbar: inout std_logic); end srff; architecture Behavioral of srff is begin process(s,r,rst,clk) begin if(rst=1) then q<=0; qbar<=1; elsif (clk=1 and clkevent) then if(s=0 and r=0) then q<= q; qbar<=qbar; elsif(s=0 and r=1) then q<= 0; qbar<=1; elsif(s=1 and r=0) then q<= 1; qbar<=0; else q<=X; qbar<=X; end if; end if; end process; end Behavioral;

46

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SIMULATION REPORT:

SYNTHESIS REPORT:

47

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

JK FLIP FLOP: LOGIC DIAGRAM:

TRUTH TABLE:

Q (t) 0 0 0 0 1 1 1 1

J 0 0 1 1 0 0 1 1

K 0 1 0 1 0 1 0 1

Q (t+1) 0 0 1 1 1 0 1 0

48

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

VHDLSOURCE CODE: --Design:JK FLIPFLOP(ENTITY AND ARCHITECTURE). --Filename:jkff.vhd --Description:to implement JK FLIPFLOP using OR, NOT and AND gates. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3

JK FLIP FLOP:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff is Port ( j : in std_logic; k : in std_logic; rst : in std_logic; clk : in std_logic; q : inout std_logic; qbar : inout std_logic); end jkff; Architecture Behavioral of srff is begin process(j,k,rst,clk) begin if(rst=1) then q<=0; qbar<=1; elsif (clk=1 and clkevent) then if(j=0 and k=0) then q<= q; qbar<=qbar;

49

EX No: NAME: SAGAYA GINOLIYA FERNANDO elsif(j=0 and k=1) then q<= 0; qbar<=1; elsif(j=1 and k=0) then q<= 1; qbar<=0; else q<=not q; qbar<=not qbar; end if; end if; end process; end Behavioral;

REG No: 2913183 DATE:

SIMULATION REPORT:

50

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SYNTHESIS REPORT:

D FLIP FLOP: LOGIC DIAGRAM:

TRUTH TABLE: Q(t) 0 0 1 1 D 0 1 0 1 Q(t+1) 0 1 0 1

51

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

VHDL SOURCE CODE: --Design:D FLIPFLOP(ENTITY AND ARCHITECTURE). --Filename:dff.vhd --Description:to implement D FLIPFLOP using OR, NOT and AND gates. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3 D FLIP FLOP: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is Port ( d : in std_logic; rst : in std_logic; clk : in std_logic; q : out std_logic; qbar : out std_logic); end dff; architecture Behavioral of dff is signal qt,qbart:std_logic; begin p1:process(d,clk,rst) begin if(rst='1') then qt <= '0'; qbart <= '0'; elsif (clk='1' and clk'event) then qt <=((not clk) and qt) or (clk and d); qbart <= not qt; end if;

end process p1; q <= qt; qbar <= qbart; end Behavioral;

52

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SIMULATION REPORT:

SYNTHESIS REPORT:

53

EX No: NAME: SAGAYA GINOLIYA FERNANDO T FLIP FLOP: LOGIC DIAGRAM:

REG No: 2913183 DATE:

TRUTH TABLE:

Q(t) 0 0 1 1

T 0 1 0 1

Q(t+1) 0 1 1 0

VHDL SOURCE CODE: --Design:T FLIPFLOP(ENTITY AND ARCHITECTURE). --Filename:tff.vhd --Description:to implement T FLIPFLOP using OR, NOT and AND gates. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3

54

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

T FLIP FLOP: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is Port ( t : in std_logic; rst : in std_logic; clk : in std_logic; q : out std_logic; qbar : out std_logic); end tff; architecture Behavioral of tff is signal qt,qbart:std_logic; begin q<= qt; qbar<=qbart; p1:process(t,clk,rst) begin if(rst='1') then qt <= '0'; qbart <= '0'; elsif (clk='1' and clk'event) then qt <=(qt and (not t)) or ((not clk) and qt) or(clk and t and (not qt)); qbart <= not qt; end if; end process p1; end Behavioral;

SIMULATION REPORT:

55

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SYNTHESIS REPORT:

RESULT: Thus the VHDL codes for Flip Flops were written, simulated, synthesized and the outputs verified.

56

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SHIFT REGISTERS AIM: To develop source code for shift register circuit by using VHDL and obtain the simulation,synthesis using XILINX ISE 7.1i

ALGORITHM: Declare the name of design, entity and architecture body. Write the source code in VHDL. Compile the code and check for the errors. Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

57

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE:

INPUT Si 0 1 1 1 1 0 0 0 Q1 0 0 0 0 1 1 1 1 Q2 0 0 0 1 1 1 1 0

OUTPUT Q3 0 0 1 1 1 1 0 0 Q4 0 1 1 1 1 0 0 0 S0 0 0 0 0 1 1 1 1

VHDL SOURCE CODE: --Design:SHIFT REGISTER (ENTITY AND ARCHITECTURE). --Filename:shift.vhd --Description:to implement SHIFT REGISTER using D FLIPFLOP. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3

58

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SHIFT REGISTER:(SISO): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity siso is Port ( si : in std_logic; rst : in std_logic; clk : in std_logic; so : out std_logic; end siso; architecture Behavioral of siso is signal x: std_logic_vector(7 downto 0); begin process(si,clk,rst) begin if(rst=1)then so<=x; else if(clk=1 and clkevent)then so<=x(0); x(0)<=x(1); x(1)<=x(2); x(2)<=x(3); x(3)<=x(4); x(4)<=x(5); x(5)<=x(6); x(6)<=x(7); x(7)<=si; end if; end process; end behavioral;

59

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SIMULATION REPORT:

SHIFT REGISTER SERIAL INPUT PARALLEL OUTPUT: LOGIC DIAGRAM:

60

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SHIFT REGISTER:(SIPO): library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sipo is Port ( si : in std_logic; rst : in std_logic; clk : in std_logic; q : inout std_logic_vector(7 downto 0); end sipo; architecture Behavioral of sipo is begin process(si,rst,clk) begin if(rst=1)then q<=ZZZZZZZZ; else if(clk=1 and clkevent)then q(0)<=si; q(1)<=q(0); q(2)<=q(1); q(3)<=q(2); q(4)<=q(3); q(5)<=q(4); q(6)<=q(5); q(7)<=q(6); end if; end process; end behavioral;

61

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE: CLK Din 1 0 1 0 Q0 1 0 1 0 Q1 0 1 0 1 Q2 0 0 1 0 Q3 0 0 0 1

RESULT: Thus the VHDL program is simulated and the output waveform and the corresponding RTL schematic is obtained.

62

EX No: NAME: SAGAYA GINOLIYA FERNANDO COUNTERS AIM:

REG No: 2913183 DATE:

To develop source code for up/down counter circuit by using VHDL and obtain the simulation,synthesis using XILINX ISE 7.1i

ALGORITHM: Declare the name of design, entity and architecture body. Write the source code in VHDL. Compile the code and check for the errors. Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

63

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE:

UP COUNTING Direction HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH OUTPUT 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

DOWN COUNTING Direction LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW OUTPUT 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000

64

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

VHDL SOURCE CODE: --Design:UP/DOWN COUNTER (ENTITY AND ARCHITECTURE). --Filename:up/downcounter.vhd --Description:to implement COUNTER using OR, NOT and AND gates. --Limitation:NONE. --System:Model Sim 3.3 --Author:Sagaya Ginoliya Fernando --Rollno:29SEC327 --regno:2913183 --Version:3.3

Up/ Down COUNTER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity count is Port ( clk : in STD_LOGIC; dir : in STD_LOGIC; output : out STD_LOGIC_VECTOR (3 downto 0)); end count; architecture Behavioral of count is signal a: STD_LOGIC_VECTOR (3 downto 0):="0000"; begin process (clk) begin if clk='1' and clk'event then if dir='1' then a <= a + 1; else a <= a - 1; end if; end if; end process; output<=a; end Behavioral;

65

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SIMULATION REPORT:

RESULT: Thus the VHDL program is simulated and the output waveform and the corresponding RTL schematic is obtained.

66

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

RIPPLE CARRY ADDER AIM: To develop source code for ripple carry adder circuit by using VHDL and obtain the simulation,synthesis using XILINX ISE 7.1i

ALGORITHM: Declare the name of design, entity and architecture body. Write the source code in VHDL. Compile the code and check for the errors. Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

67

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

TRUTH TABLE:

INPUT A0 0 0 0 0 0 0 0 1 A1 0 0 0 0 1 1 1 1 A2 0 0 1 1 0 0 1 1 A3 0 1 0 1 0 1 0 1 B0 0 0 0 0 0 0 1 1 B1 0 0 0 0 1 1 1 1 B2 0 0 1 1 0 1 1 1 B3 0 1 0 1 1 1 0 1 CIN 0 0 0 0 0 0 1 1 S0 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 1 1 1

OUTPUT S2 0 1 0 1 1 1 0 1 S3 0 0 0 0 0 1 1 1 COUT 0 0 0 0 0 0 1 1

FULL ADDER:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity onebit is Port (a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; s : out STD_LOGIC; cout : out STD_LOGIC); end onebit; architecture Behavioral of onebit is begin

68

EX No: NAME: SAGAYA GINOLIYA FERNANDO s<=a xor b xor cin; cout<=(a and b) or (a and cin) or (b and cin); end Behavioral;

REG No: 2913183 DATE:

4-BIT ADDER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fourbit is Port ( clk : in STD_LOGIC; a4 : in STD_LOGIC_VECTOR (3 downto 0); b4 : in STD_LOGIC_VECTOR (3 downto 0); cin4 : in STD_LOGIC; s4 : out STD_LOGIC_VECTOR (3 downto 0); cout4 : out STD_LOGIC); end fourbit; architecture Behavioral of fourbit is component onebit Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; s : out STD_LOGIC; cout : out STD_LOGIC); end component; SIGNAL c : STD_LOGIC_VECTOR(3 downto 1); begin FA0: onebit PORT MAP ( FA1: onebit PORT MAP ( FA2: onebit PORT MAP ( FA3: onebit PORT MAP (

a4(0), b4(0), cin4, s4(0), c(1)); a4(1), b4(1), c(1), s4(1), c(2)); a4(2), b4(2), c(2), s4(2), c(3)); a4(3), b4(3), c(3), s4(3), cout4);

end Behavioral;

69

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

SIMULATION REPORT:

SYNTHESIS REPORT:

RESULT:
Thus the VHDL codes for Ripple Carry Adder was written, simulated, synthesized and the outputs verified.

70

EX No: NAME: SAGAYA GINOLIYA FERNANDO

REG No: 2913183 DATE:

71