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DIFFERENTIAL QUADRATURE AMPLITUDE MODULATION TECHNIQUE

 

OBJECTIVE:

ƒ

Study of carrier modulation technique by differential Quadrature amplitude Modulation method.

EQUIPMENT:

ƒ

Experimentor Kit ADCL-05.

ƒ

Connecting Chords.

ƒ

Power supply.

ƒ

e-Lab.

THEORY:

FIG. 1 BASIC DQAM MODULATION

FIG. 1 BASIC DQAM MODULATION

FIG. 2 BASIC DQAM DEMODULATION

FIG.3 DIFFERENTIAL DECODER

In DQAM or 8-differential QAM modulation, the phase of the sine carrier is changed as function of the pair of data bit (I and Q bit). The modulator is same used for QAM. Before entering the modulator the data are coded so to generate two "differential" signals namely Id and Qd. These consider the variation of the bit pairs, in respect to the pair just before. The block diagram of DQAM is shown in fig.1 and fig. 2:

The differential coding of data to be transmitted makes the "bit pair" to be

FIG.3 DIFFERENTIAL DECODER In DQAM or 8-differential QAM modulation, the phase of the sine carrier is

transformed into phase variation of the carrier. In this way the receiver recognizes the pair each time it detects a phase shift of the modulated carrier, independently from its absolute phase. The ambiguity of the QPSK modulation, which can take to the demodulated data inversion, is solved in this way.

The procedure for generating the DQAM signal is same as QAM, but in DQAM the I and Q bits are differentially encoded using separate differential encoder as shown in fig 4.2A While C bit remains same. The concept of differential encoding is same as explained in experiment no 3. After differential encoding the encoded data is fed to control inputs of carrier modulator. The four phase shifted carrier is also fed to the carrier modulator. The output of the carrier modulator is DQAM modulated signal

At the output of differential decoder we get the original I and Q bits. These I
At the output of differential decoder we get the original I and Q bits. These I and
Q bits then applied to the data decoder along with decoder clock to recovered the
original NRZ-L data.
1
SW1
SW2
0
SW3
0
SF1
SI N1
IN 1
OFF
1
1
24
1
SI N2
IN 2
ON
M
CARR IER
C
ADCL-05
O
GENER ATOR
SI N3
IN 3
SWITCH FAULTS
A
D
MOD
SI N4
IN 4
R
U
OUT
R
DAT
DAT
L
C1
I BIT
A IN
A
I
S CLOCK
CLK
A
DIFFERE NTIAL
ENCOD ER 1
OUT
IN
E
CLOCK &
T
Q
DATA
DATA
IN
DIFFE REN TIAL
ENC ODE R 2
R
DATA
DATA TRIBIT
OUT
R
BIT
C2
O
DATA
DATA
S
DATA
GEN ERATOR
NR Z-L
IN
CODER
IN
OUT
C
CODER
BIT
C3
MOD
I BIT
OUT
DATA IN
I
BIT
IN
DATA OUT
SAMPL ING
SQUARER
SQUARER
IN
DIFFEREN TIAL
CL OC K
SAMPLER
F/4
D
2
1
EO1
GENER ATOR
VCO
DECODER 1
A
ADDER
DATA IN
Q
BIT OUT
PLL
DATA OUT
180
Q BIT
IN
T
DIFFEREN TIAL
DECODE R 2
EO2
DATA OUT
A
C
BIT
C
BI
T IN
EO3
QAM
/ DQAM
DEMODU
LATOR
D
OUT
I
E
2
C
CLK
O
QAM
DQAM
Q CLK
C CLK
D
DECODER TI MING
LOGIC
SF2
E
OFF
R
ON
PHASE
RST
ADCL-06
SYNC

SWITCH FAULTS

BLOCK DIAGRAM FOR DIFFERENT IAL QUADRATURE AMPLITUDE

MODULATION TECHNIQUE

 

PROCEDURE:

ƒ

Refer to the block diagram and carry out the following connections and

ƒ

switch settings. Connect power supply in proper polarity to the kit ADCL-05 and ADCL-06

ƒ

switch it on. Select Data pattern of simulated data using switch SW1, SW2, SW3.

ƒ

Connect SDATA generated to DATA IN of NRZ-L CODER.

At the output of differential decoder we get the original I and Q bits. These I

ƒ

Connect the NRZ-L coded data at DATA OUT to the DATA IN of the

ƒ

TRIBIT CODER. Connect the clock generated SCLOCK to CLK IN of TRIBIT CODER.

ƒ

Connect I BIT to DATA IN of differential encoder 1 and Q BIT to DATA IN of differential encoder 2.

ƒ Connect the NRZ-L coded data at DATA OUT to the DATA IN of the ƒ

ƒ

Connect DATA OUT of differential encoder 1 to C1 and DATA OUT of differential encoder 2 to C2 of CARRIER MODULATOR.

ƒ Connect the NRZ-L coded data at DATA OUT to the DATA IN of the ƒ

ƒ

Connect C BIT

of

tribit

coder

to

control

input

C3

of

CARRIER

ƒ

MODULATOR. Connect sine carrier to input of CARRIER MODULATOR as follows:

ƒ

SIN 1 to IN 1.

ƒ Connect the NRZ-L coded data at DATA OUT to the DATA IN of the ƒ

ƒ

SIN 2 to IN 2.

ƒ SIN 2 to IN 2. ƒ SIN 3 to IN 3. ƒ SIN 4 to
ƒ SIN 3 to IN 3. ƒ SIN 4 to IN 4. ƒ Connect QAM modulated
ƒ
SIN 3 to IN 3.
ƒ
SIN 4 to IN 4.
ƒ
Connect QAM modulated signal MOD OUT on ADCL-05 to the MOD IN Of
the QAM DEMODULATOR on ADCL-06.
ƒ Connect I BIT to DATA IN of differential decoder 1 and Q BIT to DATA

ƒ

Connect I BIT to DATA IN of differential decoder 1 and Q BIT to DATA IN of differential decoder 2.

ƒ Connect I BIT to DATA IN of differential decoder 1 and Q BIT to DATA

ƒ

Connect DATA OUT of differential decoder 1 to I BIT IN and DATA OUT of differential decoder 2 to Q BIT IN of DATA DECODER.

ƒ Connect I BIT to DATA IN of differential decoder 1 and Q BIT to DATA

ƒ

Connect C BIT of QAM Demodulator to C BIT IN of DATA DECODER.

ƒ ƒ Put switch SW1 on ADCL-06 to DQAM mode. Observe the decoded data at DATA
ƒ ƒ Put switch SW1 on ADCL-06 to DQAM mode. Observe the decoded data at DATA
ƒ
ƒ
Put switch SW1 on ADCL-06 to DQAM mode.
Observe the decoded data at DATA OUT post of data decoder. Compare
the decoded data with SDATA on ADCL-05.

OBSERVATIONS:

ƒ ON KIT ADCL-05. ƒ Input NRZ-L coded Data at DATA OUT of NRZ-L coder. ƒ
ƒ
ON KIT ADCL-05.
ƒ
Input NRZ-L coded Data at DATA OUT of NRZ-L coder.
ƒ
Tribit coded data I BIT, Q BIT & C BIT at the output of tribit coder.
ƒ Carrier signal SIN 1 to SIN 4. ƒ QAM modulated signal at MOD OUT of
ƒ Carrier signal SIN 1 to SIN 4. ƒ QAM modulated signal at MOD OUT of
ƒ
Carrier signal SIN 1 to SIN 4.
ƒ
QAM modulated signal at MOD OUT of carrier modulator.
ƒ Carrier signal SIN 1 to SIN 4. ƒ QAM modulated signal at MOD OUT of

ON KIT ADCL-06.

ƒ

Output of first squarer at SQUARER 1.

ƒ Output of second squarer at SQUARER 2. ƒ Recovered carrier of 2MHz at PLL. ƒ
ƒ Output of second squarer at SQUARER 2. ƒ Recovered carrier of 2MHz at PLL.
ƒ
Output of second squarer at SQUARER 2.
ƒ
Recovered carrier of 2MHz at PLL.
ƒ Output of second squarer at SQUARER 2. ƒ Recovered carrier of 2MHz at PLL. ƒ

ƒ

Four sampling clocks at the output of SAMPLING CLOCK GENERATOR.

ƒ Two added outputs at the output of ADDER. ƒ Recovered data bits (I, Q &
ƒ Two added outputs at the output of ADDER. ƒ Recovered data bits (I, Q &
ƒ
Two added outputs at the output of ADDER.
ƒ
Recovered
data
bits
(I,
Q
&
C
bits)
at
the
output of
ENVELOPE
DETECTORS.
ƒ Receiver decoding clocks at DECODER TIMING LOGIC. ƒ Recovered NRZ-L data from I & Q
ƒ Receiver decoding clocks at DECODER TIMING LOGIC. ƒ Recovered NRZ-L data from I & Q
ƒ
Receiver decoding clocks at DECODER TIMING LOGIC.
ƒ
Recovered NRZ-L data from I & Q bits at the output of DATA DECODER.
ƒ Receiver decoding clocks at DECODER TIMING LOGIC. ƒ Recovered NRZ-L data from I & Q

CONCLUSION:

The differential coding of I & Q bit data to be transmitted makes the “bit pair” to be transformed into phase variation of the carrier. In this way the receiver recognizes the pair each time it detects a phase shift of the modulated carrier, independently from its absolute phase. The ambiguity of the QAM modulation, which can take to the demodulated data inversion, is solved in this way.