Vedic multiplier

SYNOPSIS Objective of the project

To design an efficient and fast hardware multiplier based on the Vedic mathematics (Urdhva Tiryakbhyam sutra) for DSPs.

Area of Specialization: Mathematics, Verilog Abstract:

Vedic mathematics is the name given to the ancient system of mathematics based on 16 sutras. Vedic mathematics provides an easier method to produce quicker mathematical results from easier problems to the complicated ones. This Vedic math can be implemented efficiently for multiplier architecture and can be used in digital signal processors for fast processing. In this project we implement this Vedic math to realize 16X16 multiplier architecture for fast multiplication for DSP systems. The multiplier and multiplicand each are grouped as 4 bit numbers so that it decomposes into 4X4 multiplication modules. After decomposition vertical and crosswire algorithm is applied to carry out the multiplication on the first 4X4 multiply modules. The results of first 4X4 multiplication module are utilized after getting the sub product bits in parallel from the subsequent module to generate the final 32 bit product. Hence any complex NXN multiplication can be efficiently implemented by using small 4X4 multiplier using the proposed architecture where N is a multiple of 4 such as 8, 12, 16. , 4N. Therefore efficient multiplication algorithm implementation with small numbers such as 4 bits can be easily extended and embedded for implementing efficient NXN multiply operation. This project emphasizes that further hierarchical decomposition of 4X4 modules into 2X2 modules will not have a significant effect in improvement of multiplier efficiency in terms of area and speed. In this project we intend to design a high performance, high throughput and an efficient architecture of multiplier for the Field Programmable Gate Array. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswire structure of Vedic Mathematics. Using several technical papers and Vedic mathematics books as our resources and references we implement this project and will also improve the previous versions of the project in terms of speed, area and the power consumption of the multiplier.

BLOCK DIAGRAM:

Fig1. Implementation of 16x16 multiplier using 8x8 multiplier

Fig 2. Implementation of 8x8 multiplier using 4x4 multiplier

PROJECT REQUIREMENTS: This project require software coding in VHDL or Verilog, Hardware include FPGA kit for testing the codes.

Conclusion
Advantages The FPGA implementation result shows that the delay and the area required in the proposed design is far less than the conventional booth and array multiplier designs, making this efficient for the use in various DSP applications. Urdhva Tiryakbhyam, being general mathematical formula, is equally applicable to all cases of multiplication.

Disadvantages This architecture requires an array of adders is required to arrive at the final product. Due to its structure, it suffers from carry propagation delay in case of multiplication of large numbers.

Applications Vedic multiplier can be used as basic multiplier unit in ALU. This can be used in MAC unit in processors. This can be used in DSPs for mobile computing devices such as cell phones, Tablets where small size multipliers are highly required. This can be used in highly time constrained applications and in time critical operations.

TEAM MEMBERS: 1) ARUN G (1DA09EC014) 2) ADARSH N (1DA09EC002) 3) AJIT S HEGDE (1DA09EC004) 4) ABRAR AHAMED (1DA09EC001) We would be very much obliged if we are guided in every step throughout this project in achieving our goal.

Thank you