OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

OFDM transceiver design with FPGA and DEMO on DE2-70 board

Advisor: Ali Akansu By: Zhi Yong Li Date: 9/7/2008

Content:
1. 2. Project of OFDM transceiver FPGA design of OFDM transceiver a, OFDM transceiver design b, OFDM demo program design c. Special notes for the Demo program

3, OFDM transceiver demo on DE2-70 board 4, Reference

Attachment: VHDL program

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

1.

Project of OFDM transceiver

Orthogonal frequency-division multiplexing (OFDM), is identical to Coded OFDM (COFDM) and Discrete multi-tone modulation (DMT), is a frequency-division multiplexing (FDM) scheme utilized as a digital multi-carrier modulation method. Many of closely-spaced orthogonal sub-carriers are used to carry data. The data are divided into several parallel data streams or channels, one for each sub-carrier. Each sub-carrier is modulated with a conventional modulation scheme (such as quadrature amplitude modulation or phase shift keying) at a low symbol rate, keeping the total data rates similar to conventional single-carrier modulation schemes in the same bandwidth. OFDM has developed into a popular scheme for wideband digital communication, whether wireless or over copper wires, used in applications such as digital television and audio broadcasting, wireless networking and broadband internet access. The primary advantage of OFDM over single-carrier schemes is its ability to cope with severe channel conditions , for example, attenuation of high frequencies in a long copper wire, narrowband interference and frequency-selective fading due to multipath, without complex equalization filters. Channel equalization is simplified because OFDM may be viewed as using many slowly-modulated narrowband signals rather than one rapidly-modulated wideband signal. The low symbol rate makes the use of a guard interval between symbols affordable, making it possible to handle time-spreading and eliminate intersymbol interference (ISI). This mechanism also facilitates the design of single-frequency networks, where several adjacent transmitters send the same signal simultaneously at the same frequency, as the signals from multiple distant transmitters may be combined constructively, rather than interfering as would typically occur in a traditional single-carrier system. In this project, The OFDM transeiver will be designed with VHDL language and implemented in Cyclone 2 FPGA device on DE2-70 board, which in cludes the OFDM transmitter(16 QAM modulator and length N IDFT) and receiver( length N DFT and 16 QAM demodulator). Transmitter An OFDM carrier signal is the sum of a number of orthogonal sub-carriers, with baseband data on each sub-carrier being independently modulated commonly using some type of quadrature amplitude modulation (QAM) in this project, This composite baseband signal is typically used to modulate a main RF carrier. Input signal of OFDM transmitter s[n] is a serial stream of binary digits. By inverse multiplexing, these are first demultiplexed into parallel streams, and each one
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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

mapped to a complex symbol stream using 16-QAM modulation. An inverse FFT is computed on each set of symbols, delievering a set of complex symbols. These symbols are then quadrature-mixed to passband by the DAC components outside of FGPA device in the standard way. The real and imaginary components are first converted to the analogue domain using digital-to-analogue converters (DACs); the analogue signals are then used to modulate cosine and sine waves at the carrier frequency, fc, respectively. These signals are then summed to give the transmission signal, s(t).

Receiver In the receiver direction, antenner picks up the signal r(t), which is then quadrature-mixed down to baseband using cosine and sine waves at the carrier frequency. This also creates signals centered on 2fc, so low-pass filters are used to reject these. The baseband signals are then sampled and digitised using analogue-to-digital converters (ADCs) and then pass to the OFDM receiver in FPGA, inside the FPGA, a forward FFT is used to convert back to the frequency domain. This returns parallel streams, each of which is converted to a binary stream using an 16-QAM demodulator. These streams are then re-combined into a serial stream, , which is an estimate of the original binary stream at the transmitter

Goal of the project The goal of the project is to design the OFDM transmitter(16 QAM modulator and
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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

length N IDFT) and receiver( length N DFT and 16 QAM demodulator) on Cyclone 2 device of DE2_70 board ultilizing the Quartus 2 FPGA developing tool and then demonstrate its function on DE2_70 board by utilizing the LCD and 7 segment display. In the demonstration, the input bit stream test vectors will be converted from the serial to parallel, pass to 16-QAM modulation, IFFT. Then these complex symbols will directly be converted from parallel to serial again and pass to OFDM receiver inside the FGPA. The receiver will convert the I, Q data back to the original binary data by going through the process of serail to paraller, FFT, 16-QAM demodulation, and parallel to serial conversion.

2. FPGA design of OFDM transceiver a, OFDM transceiver design The OFDM transceiver block diagram is as follows.

In our design implementation, due to the need of changeable length N of DFT, we will use the length N DFT and IDFT depicted another project paper ECE698 Length N DFT designs of OFDM for FPGA implementation instead of using real FFT and IFFT modules. OFDM transmitter will be activated when trans_chipen signal is high, the input bit stream Qam_in will be mapped to complex symbols every 4 bits in 16-qam
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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

modulator which has the constellation map as follows.

The complex symbols amplitude of QAM output could be adjust by am generic constant of the VHDL program, in our program, the default value of am is set to 16, e.g., for 0101 input, the output of 16_QAM is (-1+j)*16. The default length of IFFT in our design is 16, the IFFT is actually the length N IDFT program, not the IFFT. It needs N clocks delays for the transforms. The Transmitter will send out the trans_oe as the enable signals to the next level component as well as the ifft_real_out and ifft_img_out for DAC which is real and imagine part of the IDFT results. OFDM receiver will be activated by the rec_chipen when it is high, the input of fft_img_in and fft_real_in is the imagine and real part of complex number from ADC, the receiver will pick up N=16 complex symbols every frame and converter to another batch of 16 complex symbols by length 16 DFT, then map them back to 4 bit binary signals in serial by 16-QAM demodulation. If we loop the transmitter output back to receiver input, we will get the original bit stream back. It is demonstrated in the function and timing simulation as follows. Also, it will be demonstrated on DE2-70 Demo board later. In the function simulation, bit stream input qam_in to transmitter is set 0 to 15 repeatedly, we will get the 0, -18-14j, 0, -1-8j, -8+24j, -5, 0, -3-2j, 0, -3+2j, 0, -5, 8+24j, -1+8j, 0, -14+18j 16 sets of complex symbols on ifft_real_out and ifft_img_out buses repeatedly after 18 clocks
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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

delays. For the loop test, we need to set the fft_img_in and fft_real_in of receiver input signals to the same value of transmitter output, which you will see as follows in the vector wave form input files for the function simulation.

We are expecting the get 0 to 15 repeatedly from output of receiver, check the function simulation results as follows, the simulation is correct.

Before the timing simulation, we should check what the speed of our design is when it is implemented on Cyclone 2 devices, the timing analysis report as follows says the maximum register clock is 79.99MHZ, we will use iCLK_50=50MHZ for the timing
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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

simulation and 25MHZ for the demo program on DE2-70 board later.

As we find out in the following timing simulation report, our design is correct in the simulation since we are getting back the original bit stream back on the output signal dqam_out of receiver which is from 0 to 15 while the output of transmitter is looped back to receiver.

Above all, all the simulation demonstrated that the design is correct. We will precede the demonstration on the real board in the next step.

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

Also, we could notice that when DFT and IDFT length is 16, we have used up 96 embedded multipliers out of 300 as follows; this means that 32 is our maximum length for transceiver if we still use embedded multiplier for transform calculation on this Cyclone part.

b, OFDM demo program design The Block diagram for the OFDM demo VHDL program is as follows.

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

Comparing with the transceiver, the size 256 ROM is added for input test vectors storage in the demo program. Also, 3 sets of size 256 RAM are added for IFFT, FFT, QAM demodulation results storage. In this way, we could display the results easily by utilizing the slow clock instead of 25MHZ on LCD and 7 segment display. As you could see from the diagram, iSW16 and iSW15 is used to select which RAM we want to check. When iSW16=0, iSW15=0, it is for IFFT results check. When iSW16=1, iSW15=0, it is for FFT results check. When iSW16=0, iSW15=1, it is for QAM demodulation results check, when both of them are 1, it is used for loop back.

c. Special notes for the Demo program The resource taking summary of this demo program is as follows.

From the OFDM transceiver report, we could see that the clock speed is around 79.99MHZ. In the actual design, 25MHZ for transceiver data processing clock is selected for the transceiver; this should be OK from the function point. Also, we will use length 16 DFT in our OFDM transceiver DEMO program; test vectors size will use 16 too to simplify the Demo process. More test vectors could be added by changing the vectno generic constant and the size of ROM in the ofdmdemo.vhd file.

3, OFDM transceiver demo on DE2-70 board

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

In the demonstration on DE2-70 board, first, we set the first 16 address content of qrom256.mif from 0 to 15 which is used as initialization file of ROM storing the 4 bit stream of QAM input. After compilation, download the demoofdm.sof or demoofdm.pof to the Cyclone 2 device. Then start the demo procedures as follows: First of all, Set SW16=1 and SW15=1(both in the up position) and then power it on, make sure that Led 14, 15, 16 light up.

Check the IFFT results:

1, Set SW16=0 and SW15=0(both in the low position) and then Press Key0, LEDR17 should light up and the LCD says IFFT RAM.. as follows .

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

2, Press Key2, LEDR17 should be off as follows,

3, Now it is ready to start the display of RAM contents.

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

Press key0 for 16 times, at every press, the sequence no. of n will be displayed on the LCD, the real part of IFFT output is on the left 4 7-segement displayers, the imagine part of IFFT output Y(n) is on the right 4 7-segement displayers as follows.

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

4, When the display is done, set SW16=1 and SW15=1 again (both in the up position) and press key1 to reset, the LCD and 7 segment display should return to power on state.

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

Check the FFT results:

1, Set SW16=1 and SW15=0 and then Press Key0, LEDR17 should light up and the LCD says FFT RAM.. as follows.

2, Press Key2, LEDR17 should be off as follows,

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

3, Now it is ready to start the display of RAM contents. Press key0 for 16 times, at every press, the sequence no. of n will be displayed on the LCD, the real part of FFT output is on the left 4 7-segement displayers, the imagine part of FFT output Y(n) is on the right 4 7-segement displayers as follows.

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

4, When the display is done, set SW16=1 and SW15=1 again (both in the up position) and press key1 to reset, the LCD and 7 segment display should return to power on state.

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

Check the QAM demodulation results:

1, Set SW16=0 and SW15=1 and then Press Key0, LEDR17 should light up and the LCD says DQAM RAM.. as follows.

2, Press Key2, LEDR17 should be off as follows,

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

3, Now it is ready to start the display of RAM contents. Press key0 for 16 times, at every press, the sequence no. of n will be displayed on the LCD, the real part of DQAM output is on the left 4 7-segement displayers, the imagine part of IFFT output Y(n) is on the right 4 7-segement displayers as follows.

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

4, When the display is done, set SW16=1 and SW15=1 again (both in the up position) and press key1 to reset, the LCD and 7 segment display should return to power on state.

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OFDM transceiver design with FPGA and Demo on DE2-70 board By: Zhi Yong Li, NJIT

4, Reference
* Ali N. Akansu, Xueming lin Othogonal transmultiplexers in Communication: A review * http://en.wikipedia.org/wiki/OFDM * Uwe Meyer_Baese Digital signal processing with FPGAs

5, VHDL code program:

PLS. contact Author for the VHDL program if you need. -------------------End of Document------------------------

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