Beruflich Dokumente
Kultur Dokumente
February 2008
General Description
The MM74HC14 utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well as the capability to drive 10 LS-TTL loads. The 74HC logic family is functionally and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Ordering Information
Order Number
MM74HC14M MM74HC14SJ MM74HC14MTC MM74HC14N
Package Number
M14A M14D MTC14 N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Logic Diagram
Top View
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Symbol
VCC VIN VOUT IIK, IOK IOUT ICC TSTG PD Supply Voltage DC Input Voltage DC Output Voltage Clamp Diode Current DC Output Current, per pin
Parameter
Rating
0.5 to +7.0V 1.5 to VCC+1.5V 0.5 to VCC+0.5V 20mA 25mA 50mA 65C to +150C 600mW 500mW 260C
DC VCC or GND Current, per pin Storage Temperature Range Power Dissipation Note 2 S.O. Package only Lead Temperature (Soldering 10 seconds)
TL
Notes: 1. Unless otherwise specified all voltages are referenced to ground. 2. Power Dissipation temperature derating plastic N package: 12mW/C from 65C to 85C.
Symbol
VCC VIN, VOUT TA Supply Voltage DC Input or Output Voltage
Parameter
Min.
2 0 55
Max.
6 VCC +125
Units
V V C
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DC Electrical Characteristics(3)
TA = 25C Symbol
VT+
TA = 40C to 85C
1.0 2.0 3.0 1.5 3.15 4.2 0.3 0.9 1.2 1.0 2.2 3.0 0.2 0.4 0.5 1.0 1.4 1.5 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 20
Parameter
Positive Going Threshold Voltage
VCC (V)
2.0 4.5 6.0 2.0 4.5 6.0
Conditions
Minimum
Typ.
1.2 2.7 3.2 1.0 2.0 3.0 1.5 3.15 4.2 0.3 0.9 1.2 1.0 2.2 3.0 0.2 0.4 0.5 1.0 1.4 1.5 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 2.0
Guaranteed Limits
Maximum
VT
Minimum
Maximum
VH
Hysteresis Voltage
Minimum
Maximum
VOH
VIN = VIL, |IOUT| = 20A VIN = VIL, |IOUT| = 4.0mA VIN = VIL, |IOUT| = 5.2mA VIN = VIH, |IOUT| = 20A VIN = VIH, |IOUT| = 4.0mA VIN = VIH, |IOUT| = 5.2mA VIN = VCC or GND VIN = VCC or GND, IOUT = 0A
VOL
IIN ICC
6.0 6.0
Note: 3. For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
1983 Fairchild Semiconductor Corporation MM74HC14 Rev. 1.4.0 www.fairchildsemi.com 3
AC Electrical Characteristics
VCC = 5V, TA = 25C, CL = 15pF, tr = tf = 6ns
Symbol
tPHL, tPLH
Parameter
Maximum Propagation Delay
Conditions
Typ.
12
Guaranteed Limit
22
Units
ns
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50pF, tr = tf = 6ns (unless otherwise specified)
TA = 25C Symbol
tPHL, tPLH
TA = 40C to 85C
156 31 26 95 19 16
Parameter
Maximum Propagation Delay
VCC (V)
2.0 4.5 6.0 2.0 4.5 6.0
Conditions
Typ.
60 13 11 30 8 7 125 25 21 75 15 13
Guaranteed Limits
tTLH, tTHL
CPD CIN
(per gate)
27 5 10 10 10
pF
Note: 4. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC .
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Typical Applications
Low Power Oscillator
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Physical Dimensions
8.75 8.50 7.62
14 8 B A
0.65
1.27 (0.33)
0.51 0.35
0.25
M
1.27
SEE DETAIL A
0.25 0.10
0.25 0.19
R0.10 R0.10
8 0
0.50 X 45 0.25
A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13
SEATING PLANE
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specications do not expand the terms of Fairchilds worldwide terms and conditions, specically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
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Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specications do not expand the terms of Fairchilds worldwide terms and conditions, specically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
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0.43 TYP
0.65
1.65
0.45
6.10
& BOTTOM
A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6
1.00
R0.09min
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specications do not expand the terms of Fairchilds worldwide terms and conditions, specically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
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14
8 6.60 6.09
3.81 3.17
0.58 0.35
2.54
8.82
NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specications do not expand the terms of Fairchilds worldwide terms and conditions, specically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
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TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. ACEx Build it Now CorePLUS CROSSVOLT CTL Current Transfer Logic EcoSPARK EZSWITCH *
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Rev. I33
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
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