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A Design Hierarchy

A Design Hierarchy
Modules can reference other modules to form a hierarchy. Here w e see a 2:1 multiplexer w ith an inverting data path consisting of an AOI gate and a pair of inverters.

Module Instances

The MUX_2 module contains references to each of the low er level modules, and describes the interconnections betw een them. In Verilog jargon, a reference to a low er level module is called a module instance. Each instance is an independent, concurrently active copy of a module. Each module instance consists of the name of the module being instanced (e.g. AOI or INV), an instance name (unique to that instance w ithin the current module) and a port connection list. The module port connections can be given in order (positional mapping), or the ports can be explicitly named as they are connected (named mapping). Named mapping is usually preferred for long connection lists as it makes errors less likely.
Verilog: 2-input multiplexer module

/ /V e r i l o gc o d ef o r2 i n p u tm u l t i p l e x e r m o d u l eI N V( i n p u tA ,o u t p u tF ) ; / /A ni n v e r t e r a s s i g nF=~ A ; e n d m o d u l e m o d u l eA O I( i n p u tA ,B ,C ,D ,o u t p u tF ) ; a s s i g nF=~ ( ( A&B )|( C&D ) ) ; e n d m o d u l e m o d u l eM U X 2( i n p u tS E L ,A ,B ,o u t p u tF ) ; / /2 : 1m u l t i p l e x e r / /w i r e sS E L Ba n dF Ba r ei m p l i c i t / /M o d u l ei n s t a n c e s . . . I N VG 1( S E L ,S E L B ) ; A O IG 2( S E L B ,A ,S E L ,B ,F B ) ; I N VG 3( . A ( F B ) ,. F ( F ) ) ; / /N a m e dm a p p i n g e n d m o d u l e / /e n do fV e r i l o gc o d e

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A Design Hierarchy

Yes, it's time to dissect the code line by line again, but w e'll concentrate on the new lines as the module interface has been covered before (see A Simple Design).

Implicit Wires
/ /w i r e sS E L Ba n dF Ba r ei m p l i c i t The w ires used in continuous assignments MUST be declared. How ever, one-bit w ires connecting component instances together do not need to be declared. Such w ires are regarded as implicit w ires. Note that implicit w ires are only one bit w ide, if a connection betw een tw o components is a bus, you must declare the bus as a w ire.

Module Instances
A O IG 2( S E L B ,A ,S E L ,B ,F B ) ; In a module instance, the ports defined in the module interface are connected to w ires in the instantiating module through the use of port mapping. For the instance of AOI, the first w ire in the port list is SELB. In the module header for the AOI gate, A is the first port in the port list, so SELB is connected to A. The second port in the module header is B, the second w ire in the port list is A, thus the w ire A in MUX2 is connecyted to the port B of the AOI gate instance. I N VG 3( . A ( F B ) ,. F ( F ) ) ; The second INV instance, G3, uses named mapping rather than positional mapping. In the port list for the G instance, the w ire FB is connected to the input port, A, of the INV instance. The period character is follow ed by the name of the module header port; in brackets follow ing the formal port, the name of the w ire is entered. Prev Next Copyright 2005-2012 Doulos. All rights reserved.

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