INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT534 Octal D-type flip-flop; positive edge-trigger; 3-state; inverting

Product specication Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Apr 10

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

FEATURES 3-state inverting outputs for bus oriented applications 8-bit positive, edge-triggered register Common 3-state output enable input Output capability: bus driver ICC category: MSI. GENERAL DESCRIPTION The 74HC/HCT534 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns

74HC/HCT534

The 74HC/HCT534 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 534 is functionally identical to the 374, but has inverted outputs.

TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz. fo = output frequency in MHz. (CL VCC2 fo) = sum of outputs. CL = output load capacitance in pF. VCC = supply voltage in V. 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC 1.5 V. ORDERING INFORMATION TYPE NUMBER 74HC534 74HC534 74HCT534 74HCT534 PACKAGE NAME SO20 DIP20 SO20 DIP20 DESCRIPTION plastic small outline package; 20 leads; body width 7.5 mm plastic dual in-line package; 20 leads (300 mil) plastic small outline package; 20 leads; body width 7.5 mm plastic dual in-line package; 20 leads (300 mil) VERSION SOT163-1 SOT146-1 SOT163-1 SOT146-1 PARAMETER propagation delay CP to Qn maximum clock frequency input capacitance power dissipation capacitance per ip-op notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 12 61 3.5 19 HCT 13 40 3.5 19 ns MHz pF pF UNIT

1998 Apr 10

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

PIN DESCRIPTION PIN NO. 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 OE Q0 to Q7 D0 to D7 GND CP VCC SYMBOL 3-state outputs data inputs ground (0 V) clock input (LOW-to-HIGH, edge-triggered) positive supply voltage

74HC/HCT534

NAME AND FUNCTION 3-state output enable input (active LOW)

fpage

OE 1 Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9 GND 10
MGM954

20 VCC 19 Q7 18 D7 17 D6
page

fpage

1 11

EN C1 2 5 6 9 12 15 16 19
MGM956

11 CP 3 4 7 8 13 14 D0 D1 D2 D3 D4 D5 D6 D7 OE 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19

3 4 7 8 13 14 17

1D

534

16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP

17 18

MGM955

18

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

1998 Apr 10

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

74HC/HCT534

handbook, halfpage

3 4 7 8 13 14 17 18

D0 D1 D2 D3 D4 D5 D6 D7 FF1 to FF8 3-STATE OUTPUTS

Q0 Q1 Q2 Q3

2 5 6 9

Q4 12 Q5 15 Q6 16 Q7 19

11 CP 1 OE
MGM957

Fig.4 Functional diagram.

FUNCTION TABLE INPUTS OPERATING MODES OE load and read register load register and disable outputs L L H H Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = high impedance OFF-state; = LOW-to-HIGH clock transition. CP Dn l h l h L H L H INTERNAL FLIP-FLOPS Q0 to Q7 H L Z Z OUTPUTS

1998 Apr 10

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

74HC/HCT534

D0 handbook, full pagewidth

D1

D2

D3

D4

D5

D6

D7

CP FF 1 CP

CP FF 2

CP FF 3

CP FF 4

CP FF 5

CP FF 6

CP FF 7

CP FF 8

OE

Q0

Q1

Q2

Q3

Q4

Q5

Q6
MGM958

Q7

Fig.5 Logic diagram.

1998 Apr 10

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

DC CHARACTERISTICS FOR 74HC

74HC/HCT534

For the DC characteristics see chapter 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: bus driver ICC category: MSI. AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 40 to +85 max. 205 41 35 190 38 33 190 38 33 75 15 13 100 20 17 75 15 13 5 5 5 4.8 24 28 120 24 20 90 18 15 5 5 5 4.0 20 24 MHz ns ns 40 to +125 min. max. 250 50 43 225 45 38 225 45 38 90 18 15 ns ns ns ns ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 Fig.8 Fig.8 Fig.6 Fig.6 Fig.7 Fig.7 Fig.6 UNIT V WAVEFORMS CC (V) TEST CONDITIONS

min. typ. max. min. tPHL/ tPLH propagation delay nCP to nQn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time 41 15 12 tPZH/ tPZL 33 12 10 41 15 12 14 5 4 tW clock pulse width HIGH or LOW 80 16 14 tsu set-up time Dn to CP hold time Dn to CP maximum clock pulse frequency 60 12 10 th 5 5 5 fmax 6.0 30 35 19 7 6 6 2 2 3 1 1 18 55 66 165 33 28 150 30 26 150 30 26 60 12 10

tPHZ/ tPLZ

tTHL/ tTLH

1998 Apr 10

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

DC CHARACTERISTICS FOR 74HCT

74HC/HCT534

For the DC characteristics see chapter 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: bus driver ICC category: MSI. Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT OE CP Dn AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF

UNIT LOAD COEFFICIENT 1.25 0.90 0.35

Tamb (C) 74HCT SYMBOL PARAMETER +25 40 to +85 40 to +125 min. max. 45 45 45 18 35 18 5 15 ns ns ns ns ns ns ns MHz UNIT

TEST CONDITIONS VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 WAVEFORMS

min. typ. max min. max. tPHL/ tPLH tPZH/ tPZL tPHZ/ tPLZ tTHL/ tTLH tW tsu th fmax propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time clock pulse width HIGH or LOW set-up time Dn to CP hold time Dn to CP maximum clock pulse frequency 23 12 5 22 16 16 18 5 14 4 1 36 30 30 30 12 29 15 5 18 38 38 38 15

Fig.6 Fig.7 Fig.7 Fig.6 Fig.6 Fig.8 Fig.8 Fig.6

1998 Apr 10

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

AC WAVEFORMS

74HC/HCT534

dbook, full pagewidth

1/fmax

CP INPUT

VM(1) tW tPHL

tPLH

Qn OUTPUT

VM(1)

tTHL

tTLH

MGM959

(1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.6

Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency.

andbook, full pagewidth

tr 90% OE INPUT 10% tPLZ Qn OUTPUT LOW-to-OFF OFF-to-LOW tPHZ Qn OUTPUT HIGH-to-OFF OFF-to-HIGH outputs enabled 90% VM(1)

tf

tPZL

VM(1) 10% tPZH

VM(1) outputs enabled

MGM961

outputs disabled

(1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.7 Waveforms showing the 3-state enable and disable times.

1998 Apr 10

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

74HC/HCT534

handbook, full pagewidth

CP INPUT

VM(1)

tsu th

tsu th

Dn INPUT

VM(1)

Qn OUTPUT

VM(1)
MGM960

The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.8 Waveforms showing the data set-up and hold times for Dn input.

1998 Apr 10

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

PACKAGE OUTLINES DIP20: plastic dual in-line package; 20 leads (300 mil)

74HC/HCT534

SOT146-1

D seating plane

ME

A2

A1

c Z e b1 b 20 11 MH w M (e 1)

pin 1 index E

10

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)

(1)

e 2.54 0.10

e1 7.62 0.30

L 3.60 3.05 0.14 0.12

ME 8.25 7.80 0.32 0.31

MH 10.0 8.3 0.39 0.33

w 0.254 0.01

Z (1) max. 2.0 0.078

26.92 26.54 1.060 1.045

6.40 6.22 0.25 0.24

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC EIAJ SC603 EUROPEAN PROJECTION

ISSUE DATE 92-11-17 95-05-24

1998 Apr 10

10

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

74HC/HCT534

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

A X

c y HE v M A

Z 20 11

Q A2 A1 pin 1 index Lp L 1 e bp 10 w M detail X (A 3) A

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)

0.9 0.4 0.035 0.016

0.012 0.096 0.004 0.089

0.019 0.013 0.014 0.009

0.419 0.043 0.055 0.394 0.016

8o 0o

Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013AC EIAJ EUROPEAN PROJECTION

ISSUE DATE 95-01-24 97-05-22

1998 Apr 10

11

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

74HC/HCT534

Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow. The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.

1998 Apr 10

12

Philips Semiconductors

Product specication

Octal D-type ip-op; positive edge-trigger; 3-state; inverting

DEFINITIONS Data sheet status Objective specication Preliminary specication Product specication Limiting values

74HC/HCT534

This data sheet contains target or goal specications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains nal product specications.

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specication is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specication. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

1998 Apr 10

13