TL850 Preliminary Register Manual July, 1999: Teralogic Confidential - Do Not

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TL850 Preliminary Register Manual Version 2.0 July, 1999
TERALOGIC CONFIDENTIAL - DO NOT COPY
Copyright 1999, 1998, 1997 TeraLogic, Inc. All rights reserved worldwide. This register manual contains information that is confidential to TeraLogic, Inc. and is subject to the terms and conditions, including confidentiality obligations, set forth in the applicable Nondisclosure Agreement and/or License Agreement between Teralogic, Inc. and User. Information herein is subject to change without notice. TeraLogic, Inc. assumes no responsibility for any use of, or reliance on, the information contained herein. THIS REGISTER MANUAL AND ALL INFORMATION CONTAINED HEREIN IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE. TERALOGIC, INC. AND ITS SUPPLIERS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. TeraLogic and the TeraLogic logo are trademarks of TeraLogic, Inc. All other trademarks are the properties of their respective owners.
TeraLogic, Inc. 1240 Villa Street Mountain View CA 94041-1124 Tel. : (650) 526-2000 Fax. : (650) 526- 2006 Doc#PD-850-PM-001-02
Document Revisions
The following table enlists the sections in the following document that have been edited/ added/ deleted/ w.r.t. the previous version of the same document. Note that the section numbers might have changed from the previous version of the document. The sections referred to in the table correspond to the sections in the respective documents. If section numbers have changed but the contents of the section are the same as the previous document version then such sections are not listed in the table.
Table 1: Document Revisions Document Revision Version 1.0 Version 2.0 Release Date N/A July, 1999 Sections in respective version changed w.r.t. previous version N/A Entire document edited Type of Change Internal Document Edited
TeraLogic Confidential
July 1999
This material is confidential and is provided under an existing NDA
TL850 Register Manual
The following document is the TL850 Register Manual which is provided as a reference for a programmer using the TL850 IC from Teralogic Inc. The interface through which the TL850 can be programmed is through the device drivers and Application Programmers Interface (API) provided by Teralogic Inc. It is recommended that a programmer gets familiarized with the device drivers and the API before attempting to modify the TL850 software. Developing device drivers using only the Register Manual is not recommended. Some features of the TL850 are only accessible through the device driver and API, since this provides the only framework in which Teralogic Inc. can ensure compliance of end-product to digital TV standards. If an application, which requires non-standard driver functionality, needs to be developed, contact Teralogic Inc. before attempting the change.
July 1999 Rev.2.0
Doc#PD-850-PM-001-02
1.0
PCI CONFIGURATION REGISTERS

PCI configuration registers within the TL850 are implemented according to the PCI Specification 2.2 They are accessed by the Host bridge PCI master. The PCI Specification (Revision 2.2) describes the Configuration Space used by the system to identify and configure each device attached to the bus. The Configuration Space contains a 256-byte address space for each device and has sufficient information for the system to identify the capabilities of the device. The software executes a special configuration cycle to allow access to these registers. Certain values in the configuration register must be loaded by an external NVRAM. On powerup, some default settings might be reprogrammable. The following chart shows whether the register value must be loaded by NVRAM (NV), or have a hard coded (HC) value, or is reprogrammable (REP) during system operation. Values loaded by NVRAM must be available prior to system BIOS boot-up.
Table 1.1:
PCI Configuration Registers - HIF

Bits 15:0 31:16 R/W R R Vendor ID Device ID Description Default (HEX) 035f544C
Register Location Volatility HEX HC 0x00000 0x00001 0x00002 0x00003 0x00004 0x00005
REP
15:0
R/W
0x00006 0x00007 HC NV NV NV REP NV NV HC REP NV NV 0x00008 0x00009 0x0000A 0x0000B 0x0000C 0x0000D 0x0000E 0x0000F 0x00010 0x00013 0x00014 0x0001B 0x0001C 0x0001F
31:16 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 31:0 31:0 31:0
R/W R R R R R R/W R R R/W
Status Initialize to 0000 0010 0011 0000b. Set bit 4 to 1, thus indicating that New Capabilities are supported. Bits 10, 9, 7:0 are RO. Write a 1 to clear. See PCI 2.1 Specification for details. Command Revision ID Class Code Sub Class Base Class Cache Line Size Initialize to 0 after Reset Latency Timer Header Type BIST (not Implemented) Base Address for MIF (Memory Interface) Bits [31:26] programmable Reserved Additional Base Address Registers
2300000
4800001
80000000 0 40000000
R/W
Base Address for HIF (Host Interface) Bits [31:20] programmable
July 1999 Rev.2.0
Table 1.1:
NV
PCI Configuration Registers - HIF (cont.)

0x00020 0x00023 0x00024 0x00027 0x00028 0x0002B 0x0002C 0x0002D 15:0 R 31:0 R/W Base Address for TSD (Transport Stream Demultiplexer) Bits [31:16] programmable Reserved Additional Base Address Registers Reserved Subsystem Vendor ID This value is initialized to 0. Optionally it can be set from NVRAM prior to any read from the system BIOS accessing PCI Configuration Space. If there is no NVRAM available the value remains set to 0. Subsystem ID (Same as Subsystem Vendor ID above) NOT USED (Expansion ROM Address) Capabilities Pointer Reserved Reserved Interrupt Line Interrupt Pin A alue of 1 indicates INTA#. Min_Gnt Thiz is used for specifying how long of a burst period the device needs assuming a clock rate of 33 MHz. Max Lat This is used for specifying how often the device needs to gain access to the PCI bus. TRDY Timeout Value Retry Timeout Value R R Reserved Reserved 0 8080 0 4040100 0 48 10000000
NV NA NV
31:0
0 0 0
NV HC HC HC HC REP REP NV
0x0002E 0x0002F 0x00030 0x00033 0x00034 0x00035 0x00037 0x00038 0x0003B 0x0003C 0x0003D 0x0003E
31:16 31:0 7:0 31:08 31:0 7:0 15:8 23:16
R R R R R R/W R R
NV
0x0003F
31:17
REP REP
0x00040 0x00041 0x00042 0x00043 0x00044 0x00047
7:0 15:8 31:16 31:0
July 1999 Rev.2.0
Table 1.1:
HC HC HC
PCI Configuration Registers - HIF (cont.)

0x00048 0x00049 0x0004A 0x0004B 7:0 15:8 31:16 R R R Capabilities ID Next Item Pointer Only power management function is supported PMC Power Management Capabilities Set to 0000 0000 0010 0010b Bits 15:11 with 00000b PME# is not supported Bit 10 to a 0 D2 Power State is not supported Bit 09 to a 0 D1 Power State is not supported Bits 08:06 to a 000b (these bits are reserved) Bit 05 to a 1 Device Specific. Device must be initialized after entering D0. Bit 04 to a 0 (ignore this bit) External Strap is specific to supporting PME#. Bit 03 to a 0 Related to a PME Clock. Ignore this bit. Bit 02:00 to a 010b The TL850 is compliant to Rev 1.1 of the PCI Power Management Interface Specification. PMCSR Power Management Control/Status1 Set to 00000000000000xxb Bit 15 to a 0; PME_status is irrelevant. Bits 14:13 to a 00b The Data Register is not required. Bits 12:09 to a 0000b The Data Register is not required. Bit 08 to a 0 PME is not supported. Bits 7:2 to 000000b (these bits are reserved) Bits 01:00 depend on current state of the TL850. If AWAKE (D0) set bits 01:00 to 00b If Sleeping (D3) set bits 01:00 to 11b D1 and D2 are not supported. PMCSR PCI to PCI Bridge Support Extension indicates PCI to PCI bridge is not supported Data Register is not supported. Software Reset If bit 1 =1, assert chip reset; if = 0, no reset (default). When asserted, the TL850 is reset identically to the effect of RSTn pin, with the exception of PLLs, DLL, PCI infc. NVRAM Programming Enable If bit 1 = 1, NVRAM programming enabled; if = 0, not enabled (default). When enabled, the NVRAM can be programmed through the NVRAM register. 0 220001
REP
0x0004C 0x0004D
15:0
R/W
HC HC REP
0x0004E 0x0004F 0x00050 0x00053
23:16 31:24 31:0
R R
00 00 0
REP
0x00054 0x00057
31:0
1.
This value is initialized to the value indicated in the chart; but it is re-initialized to the value stored in the External NVRAM prior to normal operation.
July 1999 Rev.2.0
1.1
HOST BUS REGISTER MAP

The TL850 has eight address spaces selected by separate internal bank selects. There are separate address space for main memory through MIF, internal RAM testing and for the configuration registers. The first 40 Kword location are reserved for TL850 Registers and internal RAM space.
Table 1.2:
Host Bus Register Map

Target Module HIF VSC Note1 APU BLT PLL/DLL Note1 Note1 Note1 DPC Note1 TSD MIF Size (32-Bit Word) 1024 1024 1024 1024 1024 1024 1024 1024 8192 8192 8192 8192 8192 Decode 0000 0000 XXXX XXXX XXXX 0000 0001 XXXX XXXX XXXX 0000 0010 XXXX XXXX XXXX 0000 0011 XXXX XXXX XXXX 0000 0100 XXXX XXXX XXXX 0000 0101 XXXX XXXX XXXX 0000 0110 XXXX XXXX XXXX 0000 0111 XXXX XXXX XXXX 0000 1XXX XXXX XXXX XXXX 0001 0XXX XXXX XXXX XXXX 0001 1XXX XXXX XXXX XXXX 0010 0XXX XXXX XXXX XXXX 0010 1XXX XXXX XXXX XXXX
PCI ADDR[19:0] 0x000000x00FFF 0x010000x01FFF 0x020000X02FFF 0x030000x03FFF 0x040000x04FFF 0x050000x05FFF 0x060000x06FFF 0x070000x07FFF 0x080000x0FFFF 0x100000x17FFF 0x180000x1FFFF 0x200000X27FFF 0x280000X28FFF
1. Access to these registers is through device drivers and API provided by Teralogic Inc.
July 1999 Rev.2.0
2.0
REGISTER MAP
The following table is a summary of all the registers in the TL850 IC. The addresses mentioned in the Base + Offset Address column are absolute byte addresses. The Base Address in the Register Name column are provided for completeness. Reserved registers are not mentioned in the table. Hence, consecutive registers in the table may not have consecutive addresses.
Register Name
Base + Offset Address
Page #
HIF Registers (Base Address : 0x00000)

HIF Interrupt Status Register (HIF_INT0_STAT_REG) HIF Interrupt Mask Register (HIF_INT0_MASK_REG) HIF RAM Test Register (HIF_RAM_TEST_REG) HIF Hinted Address Register (HIF_HINTED_ADDR_REG) HIF Hinted Address Register (HIF_HINTED_ADDR_REG) HIF DMA Source Address Register (HIF_DMA_SRCADDR_REG) HIF DMA Destination Address Register (HIF_DMA_DSTADDR_REG) HIF DMA Count Register (HIF_DMA_COUNT_REG) HIF DMA Control Register (HIF_DMA_CTRL_REG) HIF Reserved Registers 0x00000 0x00004 0x00010 0x00014 0x0001C 0x00020 0x00024 0x00028 0x0002C 0x000300x000FF page 13 page 14 page 15 page 16 page 16 page 18 page 19 page 20 page 21 page 22
VSC Registers (Base Address : 0x01000)

Video Channel Control Register (VSC_CTRL_REG) Video Channel Status Register (VSC_STAT_REG) VSC Interrupt Enable Register (VSC_INT_EN_REG) VSC Interrupt Status Register (VSC_INT_STAT_REG) VSC Memory Interface Control Register (VSC_MIF_REG) VSC Horizontal DDA Control Register (VSC_DDA_REG) VSC Horizontal Scaler Control Register (VSC_HS_REG) VSC Field 0 VBI Data Capture Control Register (VSC_VBI0_REG) VSC Field 1 VBI Data Capture Control Register (VSC_VBI1_REG) VSC VBI Data Buffer Start Address (VSC_VBUF_SADR_REG) VSC VBI Data Buffer Write Address (VSC_VBUF_WADR_REG) VSC Software Reset Register (VSC_SW_RESET_REG) 0x01000 0x01004 0x01008 0x0100C 0x01010 0x01014 0x01018 0x0101C 0x01020 0x01024 0x01030 0x01030 page 24 page 25 page 26 page 27 page 28 page 29 page 30 page 31 page 32 page 33 page 34 page 35
APU Registers (Base Address : 0x03000)

Input, Output and Clock Configuration Register (APU_IOC_CONFIG_REG) 0x03000 page 37
July 1999 Rev.2.0
Register Name Capture and Playback Configuration Register (APU_CPB_CONFIG_REG) IEC-958 Configuration Register (APU_IEC_CONFIG_REG) IEC958 Channel Status Buffer 1 Registers (APU_IEC_CSB1_REG) IEC958 Channel Status Buffer 2 Registers (APU_IEC_CSB2_REG) Interrupt Configuration Register (APU_INT_CONFIG_REG) Interrupt Status Register (APU_INT_STATUS_REG) Capture/Playback Begin Address Register (APU_CPB_CBA_REG) Capture/Playback End Address Register (APU_CPB_CEA_REG) Capture/Playback Write Address Register (APU_CPB_CWA_REG) Capture/Playback Read Address Register (APU_CPB_CRA_REG) Capture/Playback Match Address Register (APU_CPB_CMA_REG) Internal Audio 0 Begin Address Registers (APU_IAU_IBA0_REG) Internal Audio 0 Read Address Registers (APU_IAU_IRA0_REG) Internal Audio 0 End Address Registers (APU_IAU_IEA0_REG) Internal Audio 1 Begin Address Registers (APU_IAU_IBA1_REG) Internal Audio 1 Read Address Registers (APU_IAU_IRA1_REG) Internal Audio 1 End Address Registers (APU_IAU_IEA1_REG) Internal Audio 2 Begin Address Registers (APU_IAU_IBA2_REG) Internal Audio 2 Read Address Registers (APU_IAU_IRA2_REG) Internal Audio 2 End Address Registers (APU_IAU_IEA2_REG) Mix Configuration Register (APU_MIX_CONFIG_REG) Cross-fade Coefficient Registers (APU_MIX_XFCn_REG; n=0 to 8)
Base + Offset Address 0x03004 0x03008 0x0300C 0x03010 0x03014 0x03018 0x03020 0x03024 0x03028 0x0302C 0x03030 0x03034 0x03038 0x0303C 0x03040 0x03044 0x03048 0x0304C 0x03050 0x03054 0x03058 0x0305C0x0307C
Page # page 38 page 39 page 40 page 41 page 42 page 43 page 44 page 45 page 46 page 47 page 48 page 49 page 50 page 51 page 52 page 53 page 54 page 55 page 56 page 57 page 58 page 59
BLT Registers (Base Address : 0x04000)

Channel S0 Configuration Register (BLT_CHAN_S0_REG) S1 Channel Configuration Register (BLT_CHAN_S1_REG) Destination Channel Configuration Register (BLT_CHAN_D_REG) BitBlt Command Register (BLT_CMD_REG) Mode Register (BLT_MODE_REG) Interrupt Status Register (BLT_INTR_STAT_REG) Channel S0, Left Address Register of First Line Address Processed (BLT_LEFT_ADDRESS_S0_REG) Channel S0, Right Address Register of First Line Address Processed (BLT_RIGHT_ADDRESS_S0_REG) 0x04000 0x04004 0x04008 0x0400C 0x04010 0x04014 0x04018 0x0401C page 61 page 62 page 63 page 64 page 65 page 66 page 67 page 68
July 1999 Rev.2.0
Register Name Channel S1 Left Address Register of First Line Processed (BLT_LEFT_ADDRESS_S1_REG) Channel S1 Right Address Register of First Line Processed (BLT_RIGHT_ADDRESS_S1_REG) Channel D Left Address Register of First Line Processed (BLT_LEFT_ADDRESS_D_REG) Channel D Right Address Register of First Line Processed (BLT_RIGHT_ADDRESS_D_REG) Pitch Size for Channel S0 (BLT_S0_PITCH_SIZ_REG) Pitch Size for Channel S1 (BLT_S1_PITCH_SIZ_REG) Pitch Size For Channel D (BLT_D_PITCH_SIZ_REG) Bitmap Size (BLT_H_W_REG) Link List Address (BLT_LINK_ADDR_REG) Foreground Register S0 (BLT_S0_FG_COLOR_REG) Background Register S0 (BLT_S0_BG_REG) Foreground Register S1 (BLT_S1_FG_COLOR_REG) Background Register S1 (BLT_S1_BG_REG) Alpha Parameters (BLT_ALPHA_REG) BLT Programmable Register (BLT_PROG_REG) BLT Pace Line Register (BLT_PACE_LINE_REG)
Base + Offset Address 0x04020 0x04024 0x04028 0x0402C 0x04030 0x04034 0x04038 0x0403C 0x04040 0x04044 0x04048 0x0404C 0x04050 0x04054 0x04058 0x0405C
Page # page 69 page 70 page 71 page 72 page 73 page 74 page 75 page 76 page 77 page 78 page 79 page 80 page 81 page 82 page 83 page 84
PLL Registers (Base Address : 0x05000)

System Clock PLL Register (PLL_SYSCLK_REG) Memory Clock PLL Register (PLL_MIFCLK_REG) Display Processor Clock PLL Register (PLL_DPCCLK_REG) 0x05000 0x05400 0x05800 page 86 page 87 page 88
DLL Registers (Base Address : 0x05000)

DLL Instruction RAM (DLL_IRAM_REG) DLL Fine Offset Delay Registers (DLL_FN_OFST_REG ) DLL Fine Delay Registers (DLL_FN_REG) DLL Gross Delay Registers (DLL_GR_REG) DLL Offset Delay Registers (DLL_OFST_REG) DLL Reset Registers (DLL_RST_REG) DLL PCLK Delay Registers (DLL_PCLK_DLY_REG) DLL SCLK Offset Registers (DLL_SCLK_OFST_REG) 0x05C00 0x05D00 0x05D04 0x05D08 0x05D0C 0x05D10 0x05D18 0x05D18 page 91 page 92 page 93 page 94 page 95 page 96 page 97 page 98
DPC Registers (Base Address : 0x10000)
July 1999 Rev.2.0
Register Name DPC Configuration Register (DPC_CONFIG_REG) DPC Status (DPC_STATUS_REG) DPC Interrupt Enable (DPC_INT_EN_REG) DPC Interrupt Status Register (DPC_INT_STAT_REG) DPC Display Count (DPC_DISP_COUNT_REG) DPC Sync Parameter 1 (DPC_SYNC_PARAM1_REG) DPC Sync Parameter 2 (DPC_SYNC_PARAM2_REG) DPC Sync Parameter 3 (DPC_SYNC_PARAM3_REG) DPC Sync Parameter 4 (DPC_SYNC_PARAM4_REG) DPC Sync Delay 1 (DPC_SYNC_DELAY1_REG) DPC Sync Delay 2 (DPC_SYNC_DELAY2_REG) DPC Background Accumulated Luma Register (DPC_BG_CUMLUMA_REG) DPC Overlay Accumulate Luma Register (DPC_OVL_CUMLUMA_REG) DPC Background Configuration Register (DPC_BG_CONFIG_REG) DPC Background Color Register (DPC_BG_COLOR_REG) DPC Background Video Source Configuration Register (DPC_BVDOSRC_CFG1_REG) DPC Background Video Source Configuration Register (DPC_BVDOSRC_CFG2_REG) DPC Background Video Window Configuration 1 Register (DPC_BVDOWIN_CFG1_REG) DPC Background Video Window Configuration 2 Register (DPC_BVDOWIN_CFG2_REG) DPC Background Video SC Configuration 1 Register (DPC_BVDO_SC_CFG1_REG) DPC Background Video SC Configuration 2 Register (DPC_BVDO_SC_CFG2_REG) DPC Background Video HS Control 1 Register (DPC_BVDO_HS_CTL1_REG) DPC Background Video HS Control 2 Register (DPC_BVDO_HS_CTL2_REG) DPC Background Video VS Control 1 Register (DPC_BVDO_VS_CTL1_REG) DPC Background Video VS Control 2 Register (DPC_BVDO_VS_CTL2_REG)
Base + Offset Address 0x10000 0x10004 0x10008 0x1000C 0x10010 0x10014 0x10018 0x1001C 0x10020 0x10024 0x10028 0x1002C 0x10030 0x10040 0x10044 0x10048 0x1004C 0x10050 0x10054 0x10058 0x1005C 0x10060 0x10064 0x10068 0x1006C
Page # page 102 page 104 page 105 page 106 page 107 page 108 page 109 page 110 page 111 page 112 page 113 page 114 page 115 page 116 page 118 page 119 page 120 page 121 page 122 page 123 page 124 page 125 page 126 page 127 page 128
July 1999 Rev.2.0
Register Name DPC Background Video Initial V Phase Register (DPC_BVDO_IVPH_REG) DPC Overlay Configuration Register (DPC_OVL_CONFIG_REG) DPC Overlay Display List Start Address Register (DPC_OVL_DLIST_SA_REG) DPC Overlay Plane Start Address Register (DPC_OVL_SA_REG) DPC Overlay Size Register (DPC_OVL_SIZE_REG) DPC Overlay Position Register (DPC_OVL_POS_REG) DPC Global Alpha Register (DPC_GALPHA_IBASE_REG) DPC Overlay Maximum Color Key Register (DPC_OVL_MAX_KEY_REG) DPC Overlay Minimum Color Key Register (DPC_OVL_MIN_KEY_REG) DPC Overlay Filter Co-efficients Register (DPC_OVL_FLTR_COEF_REG) DPC Overlay Display List 1 Register (DPC_OVL_DLIST1_REG) DPC Overlay Display List 2 Register (DPC_OVL_DLIST2_REG) DPC Auxiliary Display Configuration Register (DPC_AUX_CONFIG_REG) DPC Auxiliary Display Position Register (DPC_AUX_POS_REG) DPC Auxiliary Display Horizontal Size Control Register (DPC_AUX_HS_CTL_REG) DPC Auxiliary Display Vertical Size Control Register (DPC_AUX_VS_CTL_REG) DPC Auxiliary Display Programmable 1 Timing Register (DPC_AUX_PROG1_REG) DPC Auxiliary Display Programmable 2 Timing Register (DPC_AUX_PROG2_REG) DPC Auxiliary Display Programmable 3 Timing Register (DPC_AUX_PROG3_REG) DPC Cursor Start Address Register (DPC_CURS_SA_REG) DPC Cursor Position Register (DPC_CURS_POS_REG) DPC CUrsor Offset Register (DPC_CURS_OFFSET_REG) DPC Cursor Color Look UP Table (DPC_CURSCLUTn_REG; n = 0 to 15) DPC Memory Address Register (DPC_MEM_ADDR_REG) DPC Memory Data Register (DPC_MEM_DATA_REG)
Base + Offset Address 0x10070 0x10080 0x10084 0x10088 0x1008C 0x10090 0x10094 0x10098 0x1009C 0x100A0 0x100A4 0x100A8 0x100C0 0x100C4 0x100C8 0x100CC 0x100D0 0x100D4 0x100D8 0x10100 0x10104 0x10108 0x101400x1017C 0x10180 0x10184
Page # page 129 page 130 page 132 page 133 page 134 page 135 page 136 page 137 page 138 page 139 page 140 page 142 page 143 page 144 page 145 page 146 page 147 page 148 page 149 page 150 page 151 page 152 page 153 page 154 page 155
10
July 1999 Rev.2.0
Register Name DPC GPIO Enable Register (DPC_GPIO_EN_REG) DPC GPIO Output Enable Register (DPC_GPIO_OUT_EN_REG) DPC GPIO Output Data Register (DPC_GPIO_OUTDATA_REG) DPC GPIO Input Data Register (DPC_GPIO_INDATA_REG) DPC Sync Pulse Generator Configuration 1 Register (DPC_SPG_CONFIG1_REG) DPC Sync Pulse Generator Configuration 2Register (DPC_SPG_CONFIG2_REG) DPC Sync Pulse Generator Configuration 3 Register (DPC_SPG_CONFIG3_REG) DPC_SPG_PCONFIG_REG
Base + Offset Address 0x10190 0x10194 0x10198 0x1019C 0x101A0 0x101A4 0x101A8 0x101AC
Page # page 158 page 159 page 160 page 161 page 162 page 163 page 164 page 165
TSD Registers (Base Address : 0x20000)

TSD DMA Read and TSD DMA Configuration Register (TSD_DMA_RD_CONFIG_REG) TSD DMA Write Address High/Low Register (TSD_DMA_WR_ADD_REG) TSD Byte Stop and Byte Limit Register (TSD_IO_BYTELIM_CNT_REG) STC Counter Low and Middle Register (TSD_STC_CNT_LM_REG) STC Counter High Register (TSD_STC_CNT_H_REG) TSD IO Configuration and VCXO Register (TSD_CON_VCXO_REG) TSD Interrupt Status Register (TSD_INT_STATUS_REG) TSD IO Status Register (TSD_IO_STATUS_REG) TSD MPEG and Byte Count Register (TSD_MPEG_BYTECNT_REG) 0x27000 0x27004 0x27800 0x27804 0x27808 0x27810 0x27814 0x27820 0x27824 page 167 page 168 page 169 page 170 page 171 page 172 page 173 page 174 page 175
MIF Registers (Base Address : 0x28000)

MIF Configuration Register (MIF_CONFIG_REG) Macroscheduler Internal State Select (MIF_MAC_STATE_REG) MIF Field Buffer #n (MIF_FLD_DSCR_n_REG; n = 0 to 15) MIF Status for Client #n (MIF_STATUS_REG) 0x28000 0x2803C 0x280400x2807C 0x280800x280DC page 177 page 179 page 181 page 183
July 1999 Rev.2.0
11
3.0
HIF REGISTERS
HIF internal registers can be accessed by external PCI master. Table 3.3: HIF Register Map
Base + Offset Address Page #
Register Name HIF Registers (Base Address : 0x00000)

HIF Interrupt Status Register (HIF_INT0_STAT_REG) HIF Interrupt Mask Register (HIF_INT0_MASK_REG) HIF RAM Test Register (HIF_RAM_TEST_REG) HIF Hinted Address Register (HIF_HINTED_ADDR_REG) HIF EEPROM Access Register (HIF_EEPROM_REG) HIF DMA Source Address Register (HIF_DMA_SRCADDR_REG) HIF DMA Destination Address Register (HIF_DMA_DSTADDR_REG) HIF DMA Count Register (HIF_DMA_COUNT_REG) HIF DMA Control Register (HIF_DMA_CTRL_REG) HIF Reserved Registers
0x00000 0x00004 0x00010 0x00014 0x0001C 0x00020 0x00024 0x00028 0x0002C 0x000300x000FF
page 13 page 14 page 15 page 16 page 17 page 18 page 19 page 20 page 21 page 22
12
July 1999 Rev.2.0
HIF Interrupt Status Register (HIF_INT0_STAT_REG) Address: 0x00000

31 Reserved 16
15 Reserved
10
hif_mcu hif_hpip hif_vpip hif_mce hif_hif_i hif_vsc_i hif_dpc_ hif_mif_ hif_blt_ hif_apu_ _intr _intr _intr _intr ntr ntr intr intr intr intr
Bits 0 1 2 3 4 5 6 7 8 9 31:10
Mode R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -
Field Name hif_apu_intr hif_blt_intr hif_mif_intr hif_dpc_intr hif_vsc_intr hif_hif_intr hif_mce_intr hif_vpip_intr hif_hpip_intr hif_mcu_intr -
Description APU Interrupt Pending. BLT Interrupt Pending. MIF Interrupt Pending. DPC Interrupt Pending. VSC Interrupt Pending. HIF Interrupt Pending. MCE interrupt Pending VPIP interrupt Pending HPIP interrupt Pending MCU interrupt Pending Reserved
Default 0 0 0 0 0 0 0 0 0 0 0
July 1999 Rev.2.0
13
HIF Interrupt Mask Register (HIF_INT0_MASK_REG) Address: 0x00004

31 Reserved 16
15 Reserved
10
hif_mask hif_mask hif_mask hif_mask hif_mask hif_mask hif_mask hif_mask hif_mask hif_mask _mcu_int _hpip_ _vpip_ _mce_ _mif_ _blt_ _apu_ _hif_intr _vsc_intr _dpc_intr intr intr r intr intr intr intr
Bits 0 1 2 3 4 5 6 7 8 9 31:10
Mode R/W R/W R/W R/W R/W R/W R/W R/W RW R/W
Name hif_mask_apu_intr hif_mask_blt_intr hif_mask_MIF_intr hif_mask_dpc_intr hif_mask_vsc_intr hif_mask_hif_intr hif_mask_mce_intr hif_mask_vpip_intr hif_mask_hpip_intr hif_mask_mcu_intr
Description 1 = Enable apu interrupts. 0 = disable. 1 = Enable blt interrupts. 0 = disable. 1 = Enable MIF interrupts. 0 = disable. 1 = Enable dpc interrupts. 0 = disable. 1 = Enable vsc interrupts. 0 = disable. 1 = Enable hif interrupts. 0 = disable. 1 = Enable mce interrupts. 0 = disable. 1 = Enable vpip interrupts. 0 = disable. 1 = Enable hpip interrupts. 0 = disable. 1 = Enable mcu interrupts. 0 = disable. Reserved
Default 1 1 1 1 1 1 1 1 1 1 0
14
July 1999 Rev.2.0
HIF RAM Test Register (HIF_RAM_TEST_REG) Address: 0x00010

31 Reserved 16
15
10
9 Reserved
1 hif_mem_test_reg
Bits 2:0 31:3
Mode R/W
Field Name hif_mem_test_reg
Description 000 - Normal mode. 001-111 Internal RAM test. Reserved
Default 0 0
July 1999 Rev.2.0
15
HIF Hinted Address Register (HIF_HINTED_ADDR_REG) Address: 0x00014

31 HintAddr 16
15
10
8 HintAddr
Reservedr
Bits 1:0 31:2
Mode R RW
Field Name Reserved HintAddr
Description Reserved. A write to this register will cause a prefetch operation of the cache line into the memory read buffer.
Default 0 0
16
July 1999 Rev.2.0
HIF EEPROM Access Register (HIF_EEPROM_REG) Address: 0x0001C

31 Reserved 16
15 Reserved
10
7 hif_ eeprom_ ow
6 Reserved
hif_ hif_ hif_ hif_ eeprom_ eeprom_ eeprom_ eeprom_ sk cs do di
Bits 0 1 2 3 6:4 7 31:8
Mode R/W R/W R R/W R R/W
Field Name hif_eeprom_cs hif_eeprom_sk hif_eeprom_di hif_eeprom_do Reserved hif_eeprom_ow Reserved
Description EEPROM CS pin, chip output. EEPROM SK, chip output. EEPROM DIN, chip output. EEPROM DOUT, chip input Reserved. When set, the bitfields [3:0] go directly to pin outputs eeprom_cs/sk/di/do. Reserved
Default 0 0 0 0 0 0 0
July 1999 Rev.2.0
17
HIF DMA Source Address Register (HIF_DMA_SRCADDR_REG) Address: 0x00020

31 SrcAddr 16
15
10
8 SrcAddr
Reservedr
Bits 1:0 31:2
Mode R RW
Field Name Reserved SrcAddr
Description Reserved. All bits set to 0. Write has no effect. The address that the DMA controller reads data from.
Default 0 0
18
July 1999 Rev.2.0
HIF DMA Destination Address Register (HIF_DMA_DSTADDR_REG) Address: 0x00024

31 DstAddr 16
15
10
8 DstAddr
Reservedr
Bits 1:0 31:2
Mode R RW
Field Name Reserved DstAddr
Description Reserved. All bits set to 0. Write has no effect. The address that the DMA controller writes data to.
Default 0 0
July 1999 Rev.2.0
19
HIF DMA Count Register (HIF_DMA_COUNT_REG) Address: 0x00028

31 Reserved 16
15
10
8 Count
Reserved
Bits 1:0 15:2
Mode R RW
Field Name Reserved Count
Description Reserved. All bits set to 0. Write has no effect. The number of words that are left in DMA transfers. Note that in video DMA mode, this number must be a multiple of 8; if it is not, the TL850 transfers 16 32-bit words back to the external destination address. Reserved. All bits set to 0. Write has no effect.
Default 0 0
31:16
Reserved
20
July 1999 Rev.2.0
HIF DMA Control Register (HIF_DMA_CTRL_REG) Address: 0x0002C

31 Reserved 16
15
12
11
4 DMA_ VIDEO
3 DMAAct St
2 DMA_ EN
1 DMA_ ERR
0 DMA_ DIR
End_Byte_En
Start_Byte_En
DMA_ DMA_ DMA_ FAKE_ VDO_ ENDIAN VDO_ RESET _EN DMA
Bits 0 1 2 3 4 5 6
Mode
Field Name DMA_DIR DMA_ERR DMA_EN DMAActSt DMA_VIDEO DMA_FAKE_VDO_DMA DMA_ENDIAN_EN
Description DMA transfer direction. 1: PCI to TL850; 0: TL850 to PCI. DMA transfer error indication. 1: an error has occured. DMA enable. 0: DMA disabled; 1: DMA enabled. DMA activity status (read only). 0: Channel is not active; 1: Channel is currently active. DMA video channel enable. 0: MIF DMA channel; 1: AUX video DMA channel. 0: Normal DMA; 1: Fake video DMA operation (only read from AUX FIFO and no PCI transaction takes place). Endian Switch enable. 0: disable Endian switch; 1: enable Endian switch (byte 0 to byte 3, byte 1 to byte 2, byte 2 to byte 1, byte 3 to byte 0). 0: no action; 1: reset DPC AUX FIFO and clear the previous video DMA operation even if it is unfinished. Byte enables for the first DMA word. This is not applicable in video DMA mode. Byte enables for the last DMA word. This is not applicable in video DMA mode. Reserved.
Default 0 0 0 0 0 0 0
7 11:8 15:12 31:16
DMA_VDO_RESET Start_Byte_En End_Byte_En Reserved
0 F F 0
July 1999 Rev.2.0
21
HIF Reserved Registers Address: 0x000300x000FF
31 Reserved
Bits 31:0
Mode
Field Name Reserved
Description Reserved.
Default 0
22
July 1999 Rev.2.0
4.0
VSC REGISTERS
Table 4.4: VSC Register Map
Register Name VSC Registers (Base Address : 0x01000)

Video Channel Control Register (VSC_CTRL_REG) Video Channel Status Register (VSC_STAT_REG) VSC Interrupt Enable Register (VSC_INT_EN_REG) VSC Interrupt Status Register (VSC_INT_STAT_REG) VSC Memory Interface Control Register (VSC_MIF_REG) VSC Horizontal DDA Control Register (VSC_DDA_REG) VSC Horizontal Scaler Control Register (VSC_HS_REG) VSC Field 0 VBI Data Capture Control Register (VSC_VBI0_REG) VSC Field 1 VBI Data Capture Control Register (VSC_VBI1_REG) VSC VBI Data Buffer Start Address (VSC_VBUF_SADR_REG) VSC VBI Data Buffer Write Address (VSC_VBUF_WADR_REG) VSC Software Reset Register (VSC_SW_RESET_REG)
0x01000 0x01004 0x01008 0x0100C 0x01010 0x01014 0x01018 0x0101C 0x01020 0x01024 0x01030 0x01030
page 24 page 25 page 26 page 27 page 28 page 29 page 30 page 31 page 32 page 33 page 34 page 35
July 1999 Rev.2.0
23
Video Channel Control Register (VSC_CTRL_REG) Address: 0x01000 This register specifies the operation of Video Port.
31 reserved 15 vsc_vline_icnt 6 5 vsc_ ctype 4 3 2 1 0 16
vsc_vact vsc_vbi_ vsc_vbi_ vsc_vbi_ vsc_en _polarity vact_on en1 en0
Bits 0
Mode RW
Field Name vsc_en
Description VSC enable. This bit enables or disable the VSC. The VSC and its output turns on and off only on the frame boundaries. 0: VSC off; 1: VSC on VSC VBI data capture enable. This bit enables or disable the VSC VBI data capture feature during F==0. The VBI data capture function turns on and off only on the frame boundaries. 0: VSC VBI data capture off; 1: VSC VBI data capture on VSC VBI data capture enable. This bit enables or disable the VSC VBI data capture feature during F==1. The VBI data capture function turns on and off only on the frame boundaries. 0: VSC VBI data capture off ; 1: VSC VBI data capture on VSC VBI VACT on. This bit indicates whether VACT signal is used for VBI data capture. Note: VACT is always used for active video region. 0: VSC VBI VACT off; 1: VSC VBI VACT on VSC VACT polarity. This bit indicates whether VACT signal is active high or active low. This applies to both active video and VBI region. 0: VSC VACT active low; 1: VSC VACT active high VSC chroma type. This bit indicates whether the chroma is signed or unsigned. 0: chroma is unsigned; 1: chroma is signed Vertical Line interrupt count. This field contains the number of the vertical line for generating an interrupt if vsc_A_VLINE_IE register is set. Valid ranges for this field are 1 to 525 for NTSC and 1 to 625 for PAL. Reserved.
Default 0
RW
vsc_vbi_en0
RW
vsc_vbi_en1
RW
vsc_vbi_vact_on
RW
vsc_vact_polarity
RW
vsc_ctype
15:6
RW
vsc_vline_icnt
0xFF
31:16
RW
Reserved
24
July 1999 Rev.2.0
Video Channel Status Register (VSC_STAT_REG) Address: 0x01004 This register provides status information on the Video port.
31 res 15 res 2 1 vsc_f_flag 0 vsc_ v_flag 16
Bits 0
Mode RO
Field Name vsc_v_flag
Description CCIR656 V Flag. This bit gives the CCIR656 V status on video channel. 0: active video line 1: vertical blanking CCIR656 F Flag. This bit gives the CCIR656 F status on video channel. 0: Field 1 (odd) 1: Field 2 (even) Reserved. These bits are reserved and must be written as zeros.
Default
RO
vsc_f_flag
31:2
RO
res
July 1999 Rev.2.0
25
VSC Interrupt Enable Register (VSC_INT_EN_REG) Address: 0x01008 This register provides the interrupt enables for the VSC.
31 res 15 Reserved 7 6 5 4 3 2 1 0 16
vsc_vbi_ vsc_f1_ vsc_f0_ vsc_vblank1_ vsc_vblank0_ vsc_vline_ vsc_ibuf ie ie ie ie ie ie _ov_ie
Bits 0
Mode RW
Field Name vsc_ibuf_ov_ie
Description Internal Scaler FIFO Overflow Interrupt Enable. This bit enables/disables interrupts on internal Scaler FIFO overflows. 0: interrupts disabled. 1: interrupts enabled Video Channel B Vertical Line Interrupt Enable. This bit enables/disables interrupts at the beginning of line n of Channel B, where n is specified by the register vsc_B_VLINE_ICNT. 0: interrupts disabled. 1: interrupts enabled Video Channel Vertical Blanking Interrupt Enable for field. This field enables/disables interrupt when the video is entering the vertical blanking interval (V->1) preceding the transition to field 0. 0: interrupts disable 1: enable interrupt Video Channel Vertical Blanking Interrupt Enable for field. This field enables/disables interrupt when the video is entering the vertical blanking interval (V->1) preceding the transition to field 1. 0: interrupt disable 1: enable interrupt Video Channel Field 0 Interrupt Enable. This field enables/ disables interrupt on field transition from 1 to 0. 0: interrupt disabled 1: enable interrupt Video Channel Field 1 Interrupt Enable. This field enables/ disables interrupt on field transition from 0 to 1. 0: interrupt disabled 1: enable interrupt VBI capture done interrupt enable. This field enables/disables when VBI capture is finished 0: interrupt disabled 1: interrupt enabled. These bits are reserved and must be written as zeros.
Default 0
RW
vsc_vline_ie
RW
vsc_vblank0_ie
RW
vsc_vblank1_ie
RW
vsc_f0_ie
RW
vsc_f1_ie
RW
vsc_vbi_ie
31:7
RW
reserved
26
July 1999 Rev.2.0
VSC Interrupt Status Register (VSC_INT_STAT_REG) Address: 0x0100C The status register is cleared when read. However, a pending interrupt occurring during the same cycle has priority and will set the corresponding status bit. All interrupts are activated only on the leading edge of the interrupt conditions. The status bits are set when their corresponding conditions occur even if the interrupt enable bits are not set.
31 res 15 res 7 6 5 4 3 2 1 0 16
vsc_ vsc_ vsc_vbi_ vsc_f1_ vsc_f0_ vsc_vline vsc_ibuf vblank1 vblank0 int int int _int _ov_int _int _int
Bits 0
Mode RO
Field Name vsc_ibuf_ov_int
Description Internal DRAM Interface scaler FIFO Overflow Status. This bit is set to one when an overflow in the internal DRAM Interface scaler FIFO occurs. Video Channel vertical line interrupt status. This bit is set to one when the VSC detects the begin of video line number X, where X is defined in the vsc_ctrl_reg. Video Channel Vertical Blanking interrupt Status. This bit is set to one when the video is entering the vertical blanking interval (V->1) during field 0. Video Channel Vertical Blanking interrupt Status. This bit is set to one when the video is entering the vertical blanking interval (V->1) during field 1. Video Channel Field 0 interrupt Status. This bit is set to one when the video enters field 0. Video Channel Field 1 interrupt Status. This bit is set to one when the video enters field 1. VBI Capture Done interrupt Status. This bit is set to one when the VBI data is written into SDRAM. This field is reserved and must be written as zeros.
Default 0
RO
vsc_vline_int
RO
vsc_vblank0_int
RO
vsc_vblank1_int
4 5 6 31:7
RO RO RO RO
vsc_f0_int vsc_f1_int vsc_vbi_int reserved
0 0 0
July 1999 Rev.2.0
27
VSC Memory Interface Control Register (VSC_MIF_REG) Address: 0x01010

31 res 15 res 12 11 vsc_base1 8 7 res 4 3 vsc_base0 0 16
Bits 3:0 7:4 11:8 31:12
Mode RW RW RW RW
Field Name vsc_base0 reserved vsc_base1 reserved
Description This is the MIF descriptor base that VSC uses when posting a buffer request for field 0 to MIF These bits are reserved and must be written as zeros. This is the MIF descriptor base that VSC will use when posting a buffer request for field 1 to MIF These bits are reserved and must be written as zeros.
Default 0 0 1
28
July 1999 Rev.2.0
VSC Horizontal DDA Control Register (VSC_DDA_REG) Address: 0x01014 This register specifies the horizontal scaling factors
31 vsc_lphase 15 vsc_hstep_reg 24 23 res 20 19 vsc_hstep_reg 0 16
Bits 19:0
Mode RW
Field Name vsc_hstep_reg
Description Horizontal Step. This field contains the 20-bit step value needed for the horizontal DDA. This value avoids a divide in the implementation. The vsc_sv_hsize is the desired horizontal line width of the scaled output video. VSC_HSTEP = ( VSC_SV_HSIZE VSC_HSIZE ) 2
19
Default 0x80000
23:20 31:24
RW RW
res vsc_lphase
These bits are reserved and must be written as zeros. Initial Luma phase. This field contains the eight-bit initial phase offset for the Luma DDA. 0
vsc_hstep
vsc_sv_hsize vsc_hsize
zoom vsc_hphase
July 1999 Rev.2.0
29
VSC Horizontal Scaler Control Register (VSC_HS_REG) Address: 0x01018

31 res 15 res 10 9 vsc_line_width 26 25 vsc_sv_hsize 0 16
Bits 9:0 15:10 25:16 31:26
Mode RW RW RW RW
Field Name vsc_line_width reserved vsc_sv_hsize reserved
Description This is the number of active pixels per video line. These bits are reserved and must be written as zeros. This is the expected number of pixel output from the horizontal scaler. These bits are reserved and must be written as zeros.
Default 720
720
30
July 1999 Rev.2.0
VSC Field 0 VBI Data Capture Control Register (VSC_VBI0_REG) Address: 0x0101C
This register defines the field 0 VBI data capture operation..
31 res 15 reserved 10 9 vsc_vbi0_voffset 25 24 vsc_vbi0_vsize 0 16
Bits 9:0
Mode RW
Field Name vsc_vbi0_voffset
Description Field 0 VBI Vertical Offset. This field contains a 10-bit signed offset -(voffset) indicating where the VBI data capture begins. The offset is referenced to the rising edge of the CCIR-656 timing reference V. These bits are reserved and must be written as zeros. Field 0 VBI Vertical Size. This field defines the number of VBI lines to be captured. The maximum VBI size is 262 for NTSC and 288 for PAL. These bits are reserved and must be written as zeros.
Default 0x3F0 (16)
15:10 24:16
RW RW
res vsc_vbi0_vsize
31:25
RW
res
CCIR V
CCIR H
voffset lines
vsc_vbi_vsize lines * vsc_vbi_voffset = -(voffset-1) where voffset is >= 0
line 4 Blanking 1
line 1 (V=1)
line 20 (V=0) VBI Data Field 1 Digital Field 1 Field 1 Active Video line 264 (V=1) Blanking 2 line 283 (V=0) VBI Data Field 2 Digital Field 2 Field 2 Active Video line 525 (V=0) NTSC (CCIR656 line numbering)
line 266
line 3
July 1999 Rev.2.0
31
VSC Field 1 VBI Data Capture Control Register (VSC_VBI1_REG) Address: 0x01020
This register defines the field 1 VBI data capture operation..
31 res 15 reserved 10 9 vsc_vbi1_voffset 25 24 vsc_vbi1_vsize 0 16
Bits 9:0
Mode RW
Field Name vsc_vbi1_voffset
Description Field 1 VBI Vertical Offset. This field contains a 10-bit signed offset -(voffset) indicating where the VBI data capture begins. The offset is referenced to the rising edge of the CCIR-656 timing reference V. These bits are reserved and must be written as zeros. Field 1 VBI Vertical Size. This field defines the number of VBI line to be captured. The maximum VBI size is 262 for NTSC and 288 for PAL. These bits are reserved and must be written as zeros.
Default 0x3f0 (16)
15:10 24:16
RW RW
res vsc_vbi1_vsize
31:25
RW
res
32
July 1999 Rev.2.0
VSC VBI Data Buffer Start Address (VSC_VBUF_SADR_REG) Address: 0x01024 This register specifies the start address of the VBI field buffer in external memory...
31 Reserved 15 vsc_vbuf_sadr 27 26 vsc_vbuf_sadr 5 4 0 0 16
Bits 4:0 26:5 31:22
Mode RO RW RW
Field Name ZERO vsc_vbuf_sadr Reserved
Description Reserved. Writes are ignored reads return 0. Start address of external VBI data field buffer. The address is in 32 bytes. Reserved. These bits are reserved and must be written as zeros.
Default 0 0x0000
VBI Data Capture field Buffer
vsc_vbuf_wadr
vsc_vbuf_sadr
July 1999 Rev.2.0
33
VSC VBI Data Buffer Write Address (VSC_VBUF_WADR_REG) Address: 0x01028 This register contains the current write address of the VBI field buffer in external memory...
31 Reserved 15 vsc_vbuf_wadr 27 26 vsc_vbuf_wadr 5 4 0 0 16
Bits 4:0 26:5 31:22
Mode RO RO RO
Field Name ZERO vsc_vbuf_wadr Reserved
Description Reserved. Writes are ignored reads return 0. Write address of external VBI data field buffer. The address is in 32 bytes. Reserved. These bits are reserved and must be written as zeros.
Default 0 0x0000
VBI Data Capture field Buffer
vsc_vbuf_wadr
vsc_vbuf_sadr
34
July 1999 Rev.2.0
VSC Software Reset Register (VSC_SW_RESET_REG) Address: 0x01030 This register contains the bit to reset the VSC module via software...
31 res 15 res 2 1 res 0 vsc_rst 16
Bits 0
Mode RW
Field Name vsc_rst
Description VSC Module Reset. When set to 1, resets the VSC module. The module stays reset till a 0 is written back to come out of reset. When set to 0 the module is out of reset. Reserved.
Default 0
31:1
RO
Reserved
July 1999 Rev.2.0
35
5.0
APU REGISTERS
The following sections contain details about APU registers. Table 5.5: APU Register Map
Register Name APU Registers (Base Address : 0x03000)

Input, Output and Clock Configuration Register (APU_IOC_CONFIG_REG) Capture and Playback Configuration Register (APU_CPB_CONFIG_REG) IEC-958 Configuration Register (APU_IEC_CONFIG_REG) IEC958 Channel Status Buffer 1 Registers (APU_IEC_CSB1_REG) IEC958 Channel Status Buffer 2 Registers (APU_IEC_CSB2_REG) Interrupt Configuration Register (APU_INT_CONFIG_REG) Interrupt Status Register (APU_INT_STATUS_REG) Capture/Playback Begin Address Register (APU_CPB_CBA_REG) Capture/Playback End Address Register (APU_CPB_CEA_REG) Capture/Playback Write Address Register (APU_CPB_CWA_REG) Capture/Playback Read Address Register (APU_CPB_CRA_REG) Capture/Playback Match Address Register (APU_CPB_CMA_REG) Internal Audio 0 Begin Address Registers (APU_IAU_IBA0_REG) Internal Audio 0 Read Address Registers (APU_IAU_IRA0_REG) Internal Audio 0 End Address Registers (APU_IAU_IEA0_REG) Internal Audio 1 Begin Address Registers (APU_IAU_IBA1_REG) Internal Audio 1 Read Address Registers (APU_IAU_IRA1_REG) Internal Audio 1 End Address Registers (APU_IAU_IEA1_REG) Internal Audio 2 Begin Address Registers (APU_IAU_IBA2_REG) Internal Audio 2 Read Address Registers (APU_IAU_IRA2_REG) Internal Audio 2 End Address Registers (APU_IAU_IEA2_REG) Mix Configuration Register (APU_MIX_CONFIG_REG) Cross-fade Coefficient Registers (APU_MIX_XFCn_REG; n=0 to 8)
0x03000 0x03004 0x03008 0x0300C 0x03010 0x03014 0x03018 0x03020 0x03024 0x03028 0x0302C 0x03030 0x03034 0x03038 0x0303C 0x03040 0x03044 0x03048 0x0304C 0x03050 0x03054 0x03058 0x0305C0x0307C
page 37 page 38 page 39 page 40 page 41 page 42 page 43 page 44 page 45 page 46 page 47 page 48 page 49 page 50 page 51 page 52 page 53 page 54 page 55 page 56 page 57 page 58 page 59
36
July 1999 Rev.2.0
Input, Output and Clock Configuration Register (APU_IOC_CONFIG_REG) Address: 0x03000

31 acr 26 25 24 23 22 21 20 bcx 19 18 17 icm 16 15 byp 14 0 11 10 owl 9 8 7 6 5 4 3 2 1 0
acx
acm
ocm
iwl2
iwl1
iwl0
idly ace ijfy
Bits 0 1 2
Mode
Field Name ijfy ace idly
Description Input audio sample justify mode. 0 = left justified; 1 = right justified BCLK active edge. 0 = rising edge, 1 = falling edge. Delay from lrclk transition to first bit cell of input audio sample. 0 = no delay, 1 = one bclk cycle delay. Audio input port-0 bits/sample. 03 = 16b, 18b, 20b, 24b. Audio input port-1 bits/sample. 03 = 16b, 18b, 20b, 24b. Audio Input port-2 bits/sample. 03 = 16b, 18b, 20b, 24b. Audio output bits/sample (ports 0,1,2). 03 = 16b, 18b, 20b, 24b. Must be written as zero. Tristate buffer enable for adatao. 0 = enable 1 = disable Bypass serial streams from input ports to output ports. Must be written as zero. Output clock (bclko/lrclko) source mode. 0 = slave 1 = aclk 2, 3 = reserved BCLK multiplier. 03 = 32x, 48x, 64x, 128x. ACLK source mode. 03=Reserved; must be written as zero. ACLK multiplier. 03 = 128x, 256x, 384x, 512x. These bits are Reserved and must be set to zeroes.
Default 0 0 0
4:3 6:5 8:7 10:9 13:11 14
iwl0 iwl1 iwl2 owl reserved adatao
0 (16b) 0 (16b) 0 (16b) 0 (16b) 0 1
15 17:16 19:18
byp reserved ocm
0 0
21:20 23:22 25:24 31:26
bcx acm acx reserved
July 1999 Rev.2.0
37
Capture and Playback Configuration Register (APU_CPB_CONFIG_REG) Address: 0x03004

31 0 22 21:20 iam2 19:18 iam1 17:16 iam0 15 0 14:13 pbm2 12:11 pbm1 10:9 pbm0 8 7 6 cmsk 1 0 cfr
pen cen
Bits 0 6:1
Mode
Field Name cfr cmsk
Description Capture FIFO reset. 0 = reset, 1 = normal Capture mask. when set, enables audio capture to memory. 0 = disable, 1 = enable. bit-1: port-0 left-channel bit-2: port-0 right-channel ... bit-6: port-3 right channel. Capture enable. when set, enables audio capture based on cmsk. 0 = disable, 1 = enable. Playback enable. when set enables audio playback from memory. 0 = disable, 1 = enable. Playback mode, stream-0. 00 = mute, 01 = memory playback, 10 = bypass (samples come from corresponding I2S input port), 11 = reserved. Playback mode, stream-1. 0011 = same as pbm0. Playback mode, stream-2. 0011 = same as pbm0. Must be written as zero. Internal audio mode, stream-0. 00 = stereo, auto repeat disabled, 01 = stereo, auto repeat enabled, 10 = mono, auto repeat disabled, 11 = mono, auto repeat enabled. Internal audio mode, stream-1. 0011:same as iam0. Internal audio mode, stream-2. 0011:same as iam0. Must be written as zero.
Default 0 0
cen
pen
10:9
pbm0
00
12:11 14:13 15 17:16
pbm1 pbm2 reserved iam0
19:18 21:20 31:22
iam1 iam2 reserved
38
July 1999 Rev.2.0
IEC-958 Configuration Register (APU_IEC_CONFIG_REG) Address: 0x03008

31 fmc 24 23 22 21 20 19 0 p v u aux 16 15 14 0 sel1 12 11 10 0 sel0 8 7
csm
6:5 mod1
4:3 mod0
2:1 owl
0 enb
Bits 0 2:1
Mode
Field Name enb owl
Description IEC enable. enable iec-958 encoding. 0 = disable, 1 = enable. IEC output word length. audio samples are padded with zero on the least significant bits, as appropriate. 03 = 16b, 18b, 20b, 24b. IEC mode, channel-0. 0 = mute, 1 = mixer output, 2 = capture audio bypass (samples come from corresponding input port) 3 = internal audio bypass (samples come from IAU buffer 2). IEC mode, channel-1. 03 = same as mod0. Channel status buffer mode. 0 = 32b, 1 = 192b. IEC data select, channel-0 05 = select audio stream 05, 67 = reserved. Must be written as zero. IEC data select, channel-1 07 = same as sel0. Must be written as zero. IEC auxiliary data. provides iec auxiliary data for iec subframes. IEC user bit. provides iec user bit for iec subframes. IEC user bit. provides iec valid bit for iec subframes. IEC parity. 0 = normal parity (even) over bits 31:4, 1 = inverted parity. Must be written as zero. IEC frame counter. counts frames within a block automatically. should not be modified by host except during initialization. this field is cleared by chip reset. 0191 = frame number within iec 958 block, 192255 = reserved.
Default 0 0
4:3
mod0
6:5 7 10:8
mod1 csm sel0
0 0
11 14:12 15 19:16 20 21 22
reserved sel1 reserved iecaux u v p
23 31:24
reserved fmc
July 1999 Rev.2.0
39
IEC958 Channel Status Buffer 1 Registers (APU_IEC_CSB1_REG) Address: 0x0300C

31 csb1 0
Bits 31:0
Mode
Field Name csb1
Description IEC channel status buffer. This register provides the source for the channel status bits of iec958 channel-1subframe words. Bits are serialized, lsb first, one bit per iec958 frame, from each register. If csm=0, channel status bits are set to 0 for fmc > 31. If csm=1, channel status bits are repeated every 32 frames. An interrupt is available to alert the CPU every 32 frames. This allows the loading of new channel status information. Note that 32b are sufficient for the entire iec958 block in case of Consumer use applications. The host must reload this register every 32 frames.
Defa ult
40
July 1999 Rev.2.0
IEC958 Channel Status Buffer 2 Registers (APU_IEC_CSB2_REG) Address: 0x03010

31 csb2 0
Bits 31:0
Mode
Field Name csb2
Description IEC channel status buffer. This register provides the source for the channel status bits of iec958 channel-2 subframe words. Bits are serialized, lsb first, one bit per iec958 frame, from each register. If csm=0, channel status bits are set to 0 for fmc > 31. If csm=1, channel status bits are repeated every 32 frames. An interrupt is available to alert the CPU every 32 frames. This allows the loading of new channel status information. Note that 32b are sufficient for the entire iec958 block in case of Consumer use applications. The host must reload this register every 32 frames.
Defa ult
July 1999 Rev.2.0
41
Interrupt Configuration Register (APU_INT_CONFIG_REG) Address: 0x03014

31 Reserved 13 12:11 iecfrm 10 iauwrp 8 7 Res 6 capunf 5 capovf 4:3 0 2 matint 0
Bits 2:0
Mode
Field Name matint
Description Interrupt on reference address match. 000 = disabled, 001 = match playback pointer, 010 = match capture pointer, 011 = match playback or capture pointers, 100 = match internal audio pointer (stream-0), 101 = match internal audio pointer (stream-1), 110 = match internal audio pointer (stream-2), Must be written as zero. Interrupt on capture buffer overflow. 0 = disable, 1 = enable. Interrupt on capture buffer underflow. 0 = disable, 1 = enable. Must be written as zero. Interrupt on internal audio buffer wrap-around. 0 = disable The three iau channels can be enabled/disabled independently (default 000 all disabled) 1 = enable. Interrupt on iec-958 frame sequence end. 00 = disable, 01 = one frame, 10 = 32 frames, 11 = 192 frames (block). Must be written as zero.
Default 000
4:3 5
reserved capovf
capunf
7 10:8
reserved iauwrp[2:0]
000
12:11
iecfrm
00
31:13
reserved
42
July 1999 Rev.2.0
Interrupt Status Register (APU_INT_STATUS_REG) Address: 0x03018

31 Reserved 12: 11 iecfrm 10 iauwrp 8 7 R 6 5 4: 0 1 0 matint
capunf capovf
All bits are cleared upon read by the Host.
Bits 0 4:1 5 6 7 10:8 11 31:12
Mode
Field Name matint reserved capovf capunf reserved iauwrp iecfrm reserved
Description Set if reference address match occurred. 0 Set if capture buffer overflow occurred. Set if capture buffer underflow occurred. 0 Set if internal audio buffer wrap-around occurred. Set if iec-958 frame sequence end occurred. 0
Default
July 1999 Rev.2.0
43
Capture/Playback Begin Address Register (APU_CPB_CBA_REG) Address: 0x03020

31 Reserved 25 24 cba 5 4 Reserved 0
Bits 4:0 24:5 31:25
Mode
Field Name reserved cba reserved
Description Must be written as zero. Capture/playback begin address, in 32-byte units. the actual DRAM word address is given by 8*cba. Must be written as zero.
Default
44
July 1999 Rev.2.0
Capture/Playback End Address Register (APU_CPB_CEA_REG) Address: 0x03024

31 Reserved 25 24 cea 5 4 Reserved 0
Bits 4:0 24:5 31:25
Mode
Field Name reserved cea reserved
Description Must be written as zero. Capture/playback end address, in 32-byte units. the actual DRAM word address is given by 8*cea + 7. Must be written as zero.
Default
July 1999 Rev.2.0
45
Capture/Playback Write Address Register (APU_CPB_CWA_REG) Address: 0x03028

31 Reserved 25 24 cwa 5 4 Reserved 0
Bits 4:0 24:5 31:25
Mode
Field Name reserved cwa reserved
Description Must be written as zero. Capture/playback write address, in 32-byte units. the actual DRAM word address is given by 8*cwa. Must be written as zero.
Default
46
July 1999 Rev.2.0
Capture/Playback Read Address Register (APU_CPB_CRA_REG) Address: 0x0302C

31 Reserved 25 24 cra 5 4 Reserved 0
Bits 4:0 24:5 31:25
Mode
Field Name reserved cra reserved
Description Must be written as zero. Capture/playback read address, in 32-byte units. the actual DRAM word address is given by 8*cra. Must be written as zero.
Default
July 1999 Rev.2.0
47
Capture/Playback Match Address Register (APU_CPB_CMA_REG) Address: 0x03030

31 Reserved 25 24 cma 5 4 Reserved 0
This register is used to generate interrupts when another capture/playback register matches the contents of this register. See APU_INT_CONFIG register.
Bits 4:0 24:5 31:25
Mode
Field Name reserved cma reserved
Description Must be written as zero. Capture/playback match address, in 32-byte units. the actual DRAM word address is given by 8*cma. Must be written as zero.
Default
48
July 1999 Rev.2.0
Internal Audio 0 Begin Address Registers (APU_IAU_IBA0_REG) Address: 0x03034

31 Reserved 25 24 iba 5 4 Reserved 0
Bits 4:0 24:5 31:25
Mode
Field Name reserved iba reserved
Description Must be written as zero. Internal audio begin address, in 32-byte units. the actual DRAM word address is given by 8*iba. Must be written as zero.
Default
July 1999 Rev.2.0
49
Internal Audio 0 Read Address Registers (APU_IAU_IRA0_REG) Address: 0x03038

31 Reserved 25 24 ira 5 4 Reserved 0
Bits 4:0 24:5 31:25
Mode
Field Name reserved ira reserved
Description Must be written as zero. Internal audio read address, in 32-byte units. the actual DRAM word address is given by 8*ira. Must be written as zero.
Default
50
July 1999 Rev.2.0
Internal Audio 0 End Address Registers (APU_IAU_IEA0_REG) Address: 0x0303C

31 Reserved 25 24 iea 2 1 0
Res
Bits 1:0 24:2 31:25
Mode
Field Name reserved iea reserved
Description Must be written as zero. Internal audio end address, in words (4 bytes). Must be written as zero.
Default
July 1999 Rev.2.0
51
Internal Audio 1 Begin Address Registers (APU_IAU_IBA1_REG) Address: 0x03040

Bits 4:0 24:5 31:25
Mode
Default
52
July 1999 Rev.2.0

Bits 4:0 24:5 31:25
Mode
Default
July 1999 Rev.2.0
53
Internal Audio 1 End Address Registers (APU_IAU_IEA1_REG) Address: 0x03048

Res
Bits 1:0 24:2 31:25
Mode
Default
54
July 1999 Rev.2.0
Internal Audio 2 Begin Address Registers (APU_IAU_IBA2_REG) Address: 0x0304C

Bits 4:0 24:5 31:25
Mode
Default
July 1999 Rev.2.0
55

Bits 4:0 24:5 31:25
Mode
Default
56
July 1999 Rev.2.0
Internal Audio 2 End Address Registers (APU_IAU_IEA2_REG) Address: 0x03054

Res
Bits 1:0 24:2 31:25
Mode
Default
July 1999 Rev.2.0
57
Mix Configuration Register (APU_MIX_CONFIG_REG) Address: 0x03058

31 mixc2 24 23 mixc1 16 15 mixc0 8 7 6 5 4 3:2 mixm1 1 0
Res
mixm2
mixm0
Mixing coefficients determine the weighting of internal audio and playback audio. The sum of weights is always 1. Each mixing coefficient applies to both left and right channels of the corresponding audio stream. A value of 0 corresponds to 100% ( dB) attenuation of the corresponding internal audio stream. Values between 1 and 195 represent attenuations of 97 to 0 dB, respectively, in 0.5 dB increments. Values above 195 are treated as 195 (0 dB).
Bits 1:0
Mode
Field Name mixm0
Description Mix mode, stream-0. 00 = pause, 01 = play, 10 = mute, 11 = reserved. Mix mode, stream-1. 0011 = same as mixm0. Mix mode, stream-2. 0011 = same as mixm0. Must be written as zero. Mix coefficient, stream-0. 0x00 = attenuation of internal audio stream-0 0x010xC3 = 97 to 0 dB attenuation. Mix coefficient, stream-1. 0x00 = attenuation of internal audio stream-1 0x010xC3 = 97 to 0 dB attenuation. Mix coefficient, stream-2. 0x00 = attenuation of internal audio stream-2 0x010xC3 = 97 to 0 dB attenuation.
Default
3:2 5:4 7:6 15:8
mixm1 mixm2 reserved mixc0
23:16
mixc1
31:24
mixc2
58
July 1999 Rev.2.0
Cross-fade Coefficient Registers (APU_MIX_XFCn_REG; n=0 to 8) Address: 0x0305C0x0307C

31 xfc11 xfc13 xfc15 xfc31 xfc33 xfc35 xfc51 xfc53 xfc55 24 23 xfc10 xfc12 xfc14 xfc30 xfc32 xfc34 xfc50 xfc52 xfc54 16 15 xfc01 xfc03 xfc05 xfc21 xfc23 xfc25 xfc41 xfc43 xfc45 8 7 xfc00 xfc02 xfc04 xfc20 xfc22 xfc24 xfc40 xfc42 xfc44 0
Cross-fade coefficients determine the contribution of each of the 6 postmixing audio channels to final audio output streams. A value of 0 corresponds to 100% ( dB) attenuation of the corresponding post-mixing audio channel. Values between 1 and 195 correspond to attenuation of 97 to 0 dB, respectively, in 0.5 dB increments. Values between 196 and 255 correspond to gain of + 0.5 to + 30 dB. Results exceeding the 24b range are clamped.
July 1999 Rev.2.0
59
6.0
BLT REGISTERS
The following is the description of the BLT registers. Table 6.6: BLT Register Map
Register Name BLT Registers (Base Address : 0x04000)

Channel S0 Configuration Register (BLT_CHAN_S0_REG) S1 Channel Configuration Register (BLT_CHAN_S1_REG) Destination Channel Configuration Register (BLT_CHAN_D_REG) BitBlt Command Register (BLT_CMD_REG) Mode Register (BLT_MODE_REG) Interrupt Status Register (BLT_INTR_STAT_REG) Channel S0, Left Address Register of First Line Address Processed (BLT_LEFT_ADDRESS_S0_REG) Channel S0, Right Address Register of First Line Address Processed (BLT_RIGHT_ADDRESS_S0_REG) Channel S1 Left Address Register of First Line Processed (BLT_LEFT_ADDRESS_S1_REG) Channel S1 Right Address Register of First Line Processed (BLT_RIGHT_ADDRESS_S1_REG) Channel D Left Address Register of First Line Processed (BLT_LEFT_ADDRESS_D_REG) Channel D Right Address Register of First Line Processed (BLT_RIGHT_ADDRESS_D_REG) Pitch Size for Channel S0 (BLT_S0_PITCH_SIZ_REG) Pitch Size for Channel S1 (BLT_S1_PITCH_SIZ_REG) Pitch Size For Channel D (BLT_D_PITCH_SIZ_REG) Bitmap Size (BLT_H_W_REG) Link List Address (BLT_LINK_ADDR_REG) Foreground Register S0 (BLT_S0_FG_COLOR_REG) Background Register S0 (BLT_S0_BG_REG) Foreground Register S1 (BLT_S1_FG_COLOR_REG) Background Register S1 (BLT_S1_BG_REG) Alpha Parameters (BLT_ALPHA_REG) BLT Programmable Register (BLT_PROG_REG) BLT Pace Line Register (BLT_PACE_LINE_REG)
0x04000 0x04004 0x04008 0x0400C 0x04010 0x04014 0x04018 0x0401C 0x04020 0x04024 0x04028 0x0402C 0x04030 0x04034 0x04038 0x0403C 0x04040 0x04044 0x04048 0x0404C 0x04050 0x04054 0x04058 0x0405C
page 61 page 62 page 63 page 64 page 65 page 66 page 67 page 68 page 69 page 70 page 71 page 72 page 73 page 74 page 75 page 76 page 77 page 78 page 79 page 80 page 81 page 82 page 83 page 84
60
July 1999 Rev.2.0
Channel S0 Configuration Register (BLT_CHAN_S0_REG) Address: 0x04000

31 Reserved 15 Reserved 11 10 9 Mask 8 7 6 Block Paint 5 Pix Format 2 1 Y_DIR 0 X_Dir 16
Reduce_Pix
Bits 0 1 5:2
Mode R/W R/W R/W
Field Name X_Dir Y_Dir Pix Format
Description When at 1, scan line from left to right, increments in X direction. When at 1, increments line number. Source S0 format: B: 1 bit of index C: 4 bits of index 7: 8 bits of index 3: alpha[8],index[8] 9: alpha[4] 6: color rgb[8] D: alpha[4]rgb[12] 5: color rgb[16] 4: color rgb[24] 0: alpha[8] rgb[24] A: CbYCr[24] E: Color RGB 15 Source S0 uses a global color register. Method used to reduce format when Source format > Destination format: 0: Truncate 1: Round off 2: Dither Default: 0 1: Keep destination untouched when S0(i1) = 0. Write result to destination when S0(i1) =1. 0: Use Foreground color or Background color as a source S0 when respectively S0(i1) = 1 or S0(i1) = 0. Reserved.
Default 1 1 0
6 8:7
R/W R/W
Block Paint Reduce_Pix
R/W
Mask
31:10
Reserved
July 1999 Rev.2.0
61
S1 Channel Configuration Register (BLT_CHAN_S1_REG) Address: 0x04004

31 Reserved 15 Reserved 9 8 7 6 Block Paint 5 Pix Format 2 1 Y_DIR 0 X_Dir 16
Reduce_Pix
Bits 0 1 5:2
Mode R/W R/W R/W
Description When at 1, scan line from left to right, increments in X direction. When at 1, increments number of lines. Source S1 format: B: 1 bit of index C: 4 bits of index 7: 8 bits of index 3: alpha[8],index[8] 9: alpha[4] 6: color rgb[8] D: alpha[4]rgb[12] 5: color rgb[16] 4: color rgb[24] 0: alpha[8] rgb[24] E: Color RGB 15 Source S1 uses a global color register. Method used to reduce format when Source format > Destination format:
Default 1 1 0
6 8:7
R/W R/W
Block Paint Reduce_ Pix

31:9 Reserved
0: Truncate 1: Round off 2: Dither
Reserved.
62
July 1999 Rev.2.0
Destination Channel Configuration Register (BLT_CHAN_D_REG) Address: 0x04008

31 Reserved 15 11 Reserved 10 9 8 7 6 5 Pix Format 2 1 Y_DIR 0 X_Dir 16
XY_Dither
Bits 0 1 5:2
Mode R/W R/W R/W
Description When at 1, scan line from left to right, increments in X direction. When at 1, increments number of lines. Destination format: 7: 8 bits of index 3: alpha[8],index[8] 6: color rgb[8] D: alpha[4]rgb[12] 5: color rgb[16] 4: color rgb[24] 0: alpha[8] rgb[24] E: Color RGB 15 Initial Matrix coefficient addresses to be applied to destination: 00: from upper left 01: from upper right 10: from lower left 11: from lower right Reserved.
Default 1 1 0
7:6
R/W
XY_Dither
31:8
Reserved
July 1999 Rev.2.0
63
BitBlt Command Register (BLT_CMD_REG) Address: 0x0400C

31 Reserved 15 BLTROP 8 7 Res 6 5 4 3 2 BLENDON 18 17 16
Bool_Sel_Alpha 1 BLTOP 0
Link Lis Enable_ Enable_ Enable_ Enablet D S1 S0
Bits 1:0
Mode R/W
Field Name BLTOP
Description Specifies the operation
Default 0

2 3 R/W R/W BLENDON Enable_S0
0: BLT is idle 1: Block transfer to DRAM 2: Block transfer to LUT,

1
Alpha Blending active. Channel Source S0 enable in the current BitBlt operation. S0 region is referred as Pattern for the M/S 256 boolean operation in terms of terminology. Channel Source S1 enable in the current BitBlt operation. Channel Destination as a source operand enable in the current BitBlt operation. BitBlt operations are chained and do not require CPU intervention. Reserved
0 0
4 5 6 7 15:8 17:16
R/W R/W R/W
Enable_S1 Enable_D Link List Enable
0 0 0
R/W R/W
BLTROP Bool_Sel_Alpha
256 Boolean operations as specified by MS window environment without translation. Select the Destination alpha when no alpha blending required or source S_alpha when alpha blending turned on.
0 0

31:18 1. Reserved
0: Select Alpha from S0 source 1: Select Alpha from S1 source 2: Select Alpha from D destination
Reserved.
A Blit operation can be performed from Source to the Palette. When it is the case, the Source region is programmed in sequential manner (Pitch = 1, Width = 32 bits, Sf = 32 bpp). The Destination address is used in order to fill the 256 words or section of the Palette with word (i.e., Df = 32bpp).
64
July 1999 Rev.2.0
Mode Register (BLT_MODE_REG) Address: 0x04010

31 Reserved 15 Reserved 8 7 6 5 End_BLT 4 BLT_ Busy 3 Mask_ Field 2 Suspend _BLT 1 0 16
Pace_BLT
Bits 1:0
Mode R/W
Field Name Pace_BLT
Description Start BitBlt after Comman register programmed and according to the following: case (Pace_BLT):
Default 0

2 3 R/W R/W Suspend_BLT Mask_Field
0: No constrains 1: Upon VSYNC 2: Upon HSYNC 3: Upon specific display line number
0
Takes effect only after current BLT is over. Any Bitblt operation is suspended as long as this bit is set. When set, the compare of the Line Pace register (address 17hex) is compared on bits 9 to 0. The msb (bit 10) is ignored. Set internally when BitBlt operation is effectively started.Cleared when current BitBlt operation completes. When in link list mode, this bit covers the time for updating register and the BitBlt operation. BitBlt operation is over. Reserved.
BLT_Busy
5 31:6
End_BLT Reserved
July 1999 Rev.2.0
65
Interrupt Status Register (BLT_INTR_STAT_REG) Address: 0x04014

31 Reserved 15 8 7 6 5 4 3 2 18 17 16
Bool_Sel_Alpha 1 0
Reserved
Mask_ BLT_End Mask_ End_ Mask_ BLT_Lat _of_ BLT_End BLT_Lat Chain_ BLT_End e Chain_ _Status e BLT Status
Bits 0 1 2
Mode R R R
Field Name BLT_End_Status BLT_End_of_Chain_ Status BLT_Late
Description When not masked an interrupt is generated when a BitBlt operation completes. When not masked, an interrupt is generated when the chain of BitBlt completes. Generates an interrupt to inform the CPU that the BLIT does not get enough memory bandwidth when in pace mode. Dynamically mask End BLT interrupt. Dynamically masks End BLT chained Interrupt This bit mask the interrupt due to BLT late when BLIT operation are paced based upon display line match. Reserved.
Default
3 4 5 31:6
R/W R/W R/W
Mask_BLT_End Mask_End_Chain_BLT Mask_BLT_Late Reserved
1 1 1
66
July 1999 Rev.2.0
Channel S0, Left Address (BLT_LEFT_ADDRESS_S0_REG) Address: 0x04018

31 Reserved 15 Word Address 28 27
Register
of
First
Line
Address
Processed
16 Word Address 8 7 6 5 4 3 2 1 Left Address 0
Byte address within work
Bits 2:0
Mode R/W
Field Name Left Address
Description Left address of the first line processed of the source region. It is a bit address: Bit 2 to 0: Bit address within Byte Note that because the left address is Byte aligned bits 2 to 0 are always 0. Bit 4 to 3: Byte address within word Bit 27 to 5: Word address
Default
4:3 27:5 31:28
R/W R/W Reserved
Reserved.
July 1999 Rev.2.0
67
Channel S0, Right Address (BLT_RIGHT_ADDRESS_S0_REG) Address: 0x0401C

31 Reserved 15 Word Address 28 27
Register
of
First
Line
Address
Processed
16 Word Address 8 7 6 5 4 3 2 1 Right Address 0
Bits 2:0
Mode R/W
Field Name Right Address
Description Right address of the first line processed of the source region. It is a bit address: Bit 2 to 0: Bit address within Byte Right = Left + (PixSiz * Width + 7) / 8 1 Bit 4 to 3: Byte address within word Bit 27 to 5: Word address
Default
4:3 27:5 31:28
R/W R/W Reserved
Reserved.
68
July 1999 Rev.2.0
Channel S1 Left Address Register of First Line Processed (BLT_LEFT_ADDRESS_S1_REG) Address: 0x04020
31 Reserved 15 Word Address 8 7 28 27 Word Address 6 5 4 3 2 1 Left Address 0 16
Bits 2:0
Mode RW
Description Left address of the first line processed of the source region. It is a bit address: Bit 2 to 0: Bit address within Byte Note that because the left address is Byte aligned the bit 2 to 0 are always 0. Byte address within word Bit 27 to 5: Word address
Default
4:3 27:5 31:28
RW R/W Reserved
Reserved.
July 1999 Rev.2.0
69
Channel S1 Right Address Register of First Line Processed (BLT_RIGHT_ADDRESS_S1_REG) Address: 0x04024
31 Reserved 15 Word Address 8 7 28 27 Word Address 6 5 4 3 2 1 Right Address 0 16
Bits 2:0
Mode RW
Description Right address of the first line processed of the source region. It is a bit address: Bit 2 to 0: Bit address within Byte Right = Left + (PixSiz * Width + 7) / 8 1 Byte address within word Bit 27 to 5: Word address
Default
4:3 27:5 31:28
RW R/W Reserved
Reserved.
70
July 1999 Rev.2.0
Channel D Left Address Register of First Line Processed (BLT_LEFT_ADDRESS_D_REG) Address: 0x04028
31 Reserved 15 Word Address 8 7 28 27 Word Address 6 5 4 3 2 1 Left Address 0 16
Bits 2:0
Mode R/W
Description Left address of the first line processed of the source region. It is a bit address: Bit 2 to 0: Bit address within Byte Note that because the left address is Byte aligned the bit 2 to 0 are always 0. Bit 4 to 3: Byte address within word
Default
4:3 27:5 31:28 R/W Reserved
Bit 27 to 5: Word address Reserved.
July 1999 Rev.2.0
71
Channel D Right Address Register of First Line Processed (BLT_RIGHT_ADDRESS_D_REG) Address: 0x0402C
31 Reserved 15 Word Address 8 7 28 27 Word Address 6 5 4 3 2 1 Right Address 0 16
Bits 2:0
Mode R/W
Description Right address of the first line processed of the source region. It is a bit address: Bit 2 to 0: Bit address within Byte Right = Left + (PixSiz * Width + 7) / 8 1 Bit 4 to 3: Byte address within word
Default
4:3 27:5 31:28 R/W Reserved
Bit 27 to 5: Word address Reserved.
72
July 1999 Rev.2.0
Pitch Size for Channel S0 (BLT_S0_PITCH_SIZ_REG) Address: 0x04030

31 Reserved 15 Pitch 0 16
Bits 15:0
Mode R/W
Field Name Pitch
Description Number of words for jumping from one line to the next (beginning to beginning). Used when Channel S0 is enabled. Reserved.
Default
31:16
Reserved
July 1999 Rev.2.0
73
Pitch Size for Channel S1 (BLT_S1_PITCH_SIZ_REG) Address: 0x04034

Bits 15:0
Mode R/W
Field Name Pitch
Description Number of words for jumping from one line to the next (beginning to beginning). Used when Channel S0 is enabled. Reserved.
Default
31:16
Reserved
74
July 1999 Rev.2.0
Pitch Size For Channel D (BLT_D_PITCH_SIZ_REG) Address: 0x04038

Bits 15:0 31:16
Mode R/W
Field Name Pitch Reserved
Description Number of words for jumping from one line to the next (beginning to beginning). Reserved.
Default
July 1999 Rev.2.0
75
Bitmap Size (BLT_H_W_REG) Address: 0x0403C

31 Height 15 Width 0 16
Bits 15:0 31:16
Mode R/W R/W
Field Name Width Height
Description Width is pixels for all valid regions. Height in number of lines for all valid regions.
Default
76
July 1999 Rev.2.0
Link List Address (BLT_LINK_ADDR_REG) Address: 0x04040

31 Reserved 15 Link Address 23 22 Link Address 0 16
Bits 22:0 31:23
Mode R/W
Field Name Link Address Reserved
Description Starting address for link list. Reserved.
Default
July 1999 Rev.2.0
77
Foreground Register S0 (BLT_S0_FG_COLOR_REG) Address: 0x04044

31 S0_FG_Col 15 S0_FG_Col 0 16
Bits 31:0
Mode R/W
Field Name S0_FG_Col
Description Specifies the Foreground color when source S0 is specified in 1bpp; else it contains the global color. When in color format, components are byte aligned and color values are left justified within the byte.
Default
78
July 1999 Rev.2.0
Background Register S0 (BLT_S0_BG_REG) Address: 0x04048

31 S0_BG 15 S0_BG 0 16
Bits 31:0
Mode R/W
Field Name S0_BG
Description Specifies the Background color when source S0 is specified in 1 bpp. When in color format, components are byte aligned and color values are left justified within the byte.
Default
July 1999 Rev.2.0
79
Foreground Register S1 (BLT_S1_FG_COLOR_REG) Address: 0x0404C

31 S1_FG_Col 15 S1_FG_Col 0 16
Bits 31:0
Mode R/W
Field Name S1_FG_Col
Description Specifies the Foreground color when source S1 is specified in 1 bpp; else it contains the global color. When in color format, components are byte aligned and color values are left justified within the byte.
Default
80
July 1999 Rev.2.0
Background Register S1 (BLT_S1_BG_REG) Address: 0x04050

31 S1_BG 15 S1_BGl 0 16
Bits 31:0
Mode R/W
Field Name S1_BG
Description Specifies the Background color when source S1 is specified in 1 bpp. When in color format, components are byte aligned and color values are left justified within the byte.
Default
July 1999 Rev.2.0
81
Alpha Parameters (BLT_ALPHA_REG) Address: 0x04054

31 Reserved 15 Glo_ALpha_D 26 25 Sel_New_Alpha_D 8 7 Glo_Alpha_S 22 21 Sel_Alpha_D 19 18 Sel_Alpha_S 0 16
Bits 7:0 15:8 18:16
Mode R/W R/W R/W
Field Name Glo_Alpha_S Glo_Alpha_D Sel_Alpha_S
Description Global alpha value for source array. Used when Blending operation is on and global alpha required. Global Alpha value for destination array. Used when blending is on and global alpha required. Select As value for the blending equation: As * Cs + Ad * Cd As = 0: 1 - S_Alpha 1: D_Alpha 2: 1 - D_Alpha 3: S_Alpha 4: S_Glo_Alpha Select Ad value for the blending equation: As * Cs + Ad * Cd Ad=
Default
21:19
R/W
Sel_Alpha_D

25:22 R/W Sel_New_Alpha_D
0: 1 - S_Alpha 1: D_Alpha 2: 1 - D_Alpha 3: S_Alpha 4: D_Glo_Alpha

6
New Alpha Values when the destination format specifies an alpha component and the Alpha operation is turned on. New_D_a = case (Sel_Alpha_New_D)

31:26 Reserved
0: 1 - S_Alpha 1: D_Alpha 2: 1 - D_Alpha 3: S_Alpha 4: D_Glo_Alpha 5: S_Glo_Alpha 6: S_Alpha + D_Alpha - S_Alpha * D_Alpha
Reserved.
82
July 1999 Rev.2.0
BLT Programmable Register (BLT_PROG_REG) Address: 0x04058

31 Reserved 15 Prog_Reg 24 23 Prog_Reg 0 16
Bits 23:0
Mode RW
Field Name Prog_Reg
Description Used when in Link List mode. Allows a variable number of registers to be programmed during chained BLT. A bit set at one specifies a write. Bit 23: Program the Prog_reg register itself from bit 21 to 0. It is set to 1 when the BitBlt gets started and cleared after the register Prog_reg is effectively written. Bit 22: Link Address register Bit 21: S0 Left Address register Bit 20: S0 Right Address register Bit 19: S1 Left Address register Bit 18: S1Right Address register Bit 17: D Left Address register Bit 16: D Right address register Bit 15: Pitch for S0 Bit 14: Pitch for S1 Bit 13: Pitch for D Bit 12: Height and Width register Bit 11: Foreground or Global Color register for S0 Bit 10: Background register for S0 Bit 9: Foreground or Global Color register for S1 Bit 8: Background register for S1 Bit 7: Alpha parameter configuration Bit 6: Channel S0 configuration Bit 5: Channel S1 configuration Bit 4: Channel D configuration Bit 3: Status register Bit 2: Interrupt status register Bit1: Program line Pace register Bit 0: Command register. When Cde register written, the BLT gets started unless the BLT status specifies a suspend BLT mode. Default value: Bit 22 at 1 Reserved.
Default
31:24
Reserved
July 1999 Rev.2.0
83
BLT Pace Line Register (BLT_PACE_LINE_REG) Address: 0x0405C

.
31 res 15 res 12 11 field_num 10 line_num 0 16
Bits 10:0
Mode RW
Field Name line_num field_num
Description Line Number. This field contains the line number to be matched. Field Number. This bit contains the field number. 0: field 0 1: field 1 Reserved.
Default 0
11
RW
31:12
Reserved
84
July 1999 Rev.2.0
6.0
PLL REGISTERS
Table 6.7: PLL Register Map
Register Name PLL Registers (Base Address : 0x05000)

System Clock PLL Register (PLL_SYSCLK_REG) Memory Clock PLL Register (PLL_MIFCLK_REG) Display Processor Clock PLL Register (PLL_DPCCLK_REG)
0x05000 0x05400 0x05800
page 86 page 87 page 88
July 1999 Rev.2.0
85
System Clock PLL Register (PLL_SYSCLK_REG) Address: 0x05000

31 reserved 15 14 reserved 13 12 sysclk_pll_rd 8 7 6 5 25 24 sysclk_pll_fd 4 3 sysclk_ pll_bp 2 sysclk_ pll_pd 1 sysclk_ pll_oen 0 sysclk_ pll_ reset 16
reserved
sysclk_pll_od
Bits 0
Mode RW
Field Name sysclk_pll_reset
Description PLL power on reset. 0: PLL normal operation 1: Reset the PLL dividers PLL output enable (active low). Controls the output enable of the PLL. 0: Output enable on 1: Output enable off PLL power down mode. 0: PLL normal operation 1: Power down mode (output clock = 0) PLL bypass mode. On chip reset, this bit is set according to the state of the pll_bp pin on the chip. The pll_bp pin is pulled down internally, so leaving this pin unconnected gives a default value of 0. 0: run PLL in clock-multiply mode 1: run PLL in bypass mode PLL output divider setting. 00: divide by 1 01: divide by 2 10: divide by 2 11: divide by 4 Reserved PLL input divider setting. Reserved. This bits is reserved and must be written as zero. PLL feedback divider setting. Reserved. These bits are reserved and must be written as zeros.
Default 0
RW
sysclk_pll_oen
RW
sysclk_pll_pd
RW
sysclk_pll_bp
5:4
RW
sysclk_pll_od
7:6 12:8 15:13 24:16 31:25
RW RW RO RW RO
reserved sysclk_pll_rd Reserved sysclk_pll_fd Reserved
0 0x0A 0 0x2E 0
To calculate the output frequency of the PLL, use the following equation: FOUT = FIN * ( (FD+2) / (RD+2) ) / output divide So, for the default values, FOUT = FIN * ( (46+2) / (10+2) ) / 1 = FIN * 4 Range of input clock frequency = 2 to 40MHz; Maximum output clock frequency = 400MHz.
86
July 1999 Rev.2.0
Memory Clock PLL Register (PLL_MIFCLK_REG) Address: 0x05400

31 reserved 15 14 reserved 13 12 mifclk_pll_rd 8 7 6 5 25 24 mifclk_pll_fd 4 3 mifclk_ pll_bp 2 mifclk_ pll_pd 1 mifclk_ pll_oen 0 mifclk_ pll_ reset 16
reserved
mifclk_pll_od
Bits 0 1
Mode RW RW
Field Name mifclk_pll_reset mifclk_pll_oen
Description PLL power on reset. 0: PLL normal operation; 1: Reset the PLL dividers PLL output enable (active low). Controls the output enable of the PLL. 0: Output enable on;1: Output enable off PLL power down mode. 0: PLL normal operation; 1: Power down mode (output clock = 0) PLL bypass mode. On chip reset, this bit is set according to the state of the pll_bp pin on the chip. The pll_bp pin is pulled down internally, so leaving this pin unconnected gives a default value of 0. 0: run PLL in clock-multiply mode; 1: run PLL in bypass mode PLL output divider setting. 0: divide by 1 1: divide by 2 2: divide by 2 3: divide by 4 Reserved PLL input divider setting. Reserved. This bits is reserved and must be written as zero. PLL feedback divider setting. Reserved. These bits are reserved and must be written as zeros.
Default 0 0
RW
mifclk_pll_pd
RW
mifclk_pll_bp
5:4
RW
mifclk_pll_od
7:6 12:8 15:13 24:16 31:25
RW RW RO RW RO
reserved mifclk_pll_rd Reserved mifclk_pll_fd Reserved
0 0x0A 0 0x2E 0
To calculate the output frequency of the PLL, use the following equation: FOUT = FIN * ( (FD+2) / (RD+2) ) / output divide To program this PLL for 125 MHz, with 27 MHz input frequency, FOUT = 27 MHz * ( (123+2) / (25+2) ) / 1 = 125 MHz Or, mifclk_pll_fd = 123 (0x7b), mifclk_pll_rd = 25 (0x19), mifclk_pll_od = 0. Range of input clock frequency = 2 to 40MHz; Maximum output clock frequency = 400MHz.
July 1999 Rev.2.0
87
Display Processor Clock PLL Register (PLL_DPCCLK_REG) Address: 0x05800

31 reserved 15 14 13 12 8 7 6 5 25 24 dpcclk_pll_fd 4 3 2 1 0 dpcclk_ pll_ reset 16
dpcclk_ dpcclk_ pll_ pll_clkin reserved clkout_ _sel sel
dpcclk_pll_rd
dpcclk_ dpcclk_ pll_gp_ pll_div2 ctrl
dpcclk_pll_od
dpcclk_ dpcclk_ dpcclk_ pll_bp pll_pd pll_oen
Bits 0
Mode RW
Field Name dpcclk_pll_reset
Description PLL power on reset. 0: PLL normal operation 1: Reset the PLL dividers PLL output enable (active low). Controls the output enable of the PLL. 0: Output enable on 1: Output enable off PLL power down mode. 0: PLL normal operation 1: Power down mode (output clock = 0) PLL bypass mode. On chip reset, this bit is set according to the state of the pll_bp pin on the chip. The pll_bp pin is pulled down internally, so leaving this pin unconnected gives a default value of 0. 0: run PLL in clock-multiply mode 1: run PLL in bypass mode PLL output divider setting. 0: divide by 1 1: divide by 2 2: divide by 2 3: divide by 4 Divide by 2 mode. When running the DPC with an external encoder in 8-bit digital output mode, the DPC pixel clock must run at half the frequency of the encoder pixel clock. 0: Normal operation 1: Divide pixel clock by 2 Pixel clock output enable (active low). This controls the direction of the pclk pin on TL850. 0: pclk pin is an output 1: pclk pin is an input PLL input divider setting. Reserved. This bits is reserved and must be written as zero. Input clock select. 0: clkin pin 1: pclk pin
Def 0
RW
dpcclk_pll_oen
RW
dpcclk_pll_pd
RW
dpcclk_pll_bp
5:4
RW
dpcclk_pll_od
RW
dpcclk_pll_div2
RW
dpcclk_pll_gp_ctrl
12:8 13 14
RW RO RW
dpcclk_pll_rd Reserved dpcclk_pll_clkin_sel
0x0A 0 0
88
July 1999 Rev.2.0
Bits 15
Mode RW
Field Name dpcclk_pll_clkout_sel
Description Output clock select. 0: Internally generated pixel clock 1: External pixel clock (pclk pin) PLL feedback divider setting. Reserved. These bits are reserved and must be written as zeros.
Def 0
24:16 31:25
RW RO
dpcclk_pll_fd Reserved
0x2E 0
To calculate the output frequency of the PLL, use the following equation: FOUT = FIN * ( (FD+2) / (RD+2) ) / output divide So, for the default values, FOUT = FIN * ( (46+2) / (10+2) ) / 1 = FIN * 4 Range of input clock frequency = 2 to 40MHz; Maximum output clock frequency = 400MHz.
July 1999 Rev.2.0
89
7.0
DLL REGISTERS
The following registers are provided for reference only. The programming of the DLL should take place through the API provided by Teralogic Inc. Please refer to the API for details.
DLL Registers
Table 7.8: Register Name
DLL Register Map

DLL Registers (Base Address : 0x05C00)

DLL Instruction RAM (DLL_IRAM_REG) DLL Fine Offset Delay Registers (DLL_FN_OFST_REG ) DLL Fine Delay Registers (DLL_FN_REG) DLL Gross Delay Registers (DLL_GR_REG) DLL Offset Delay Registers (DLL_OFST_REG) DLL Reset Registers (DLL_RST_REG) DLL PCLK Delay Registers (DLL_PCLK_DLY_REG) DLL SCLK Offset Registers (DLL_SCLK_OFST_REG) 0x05C00 0x05D00 0x05D04 0x05D08 0x05D0C 0x05D10 0x05D18 0x05D18 page 91 page 92 page 93 page 94 page 95 page 96 page 97 page 98
90
July 1999 Rev.2.0
DLL Instruction RAM (DLL_IRAM_REG) Address: 0x05C00 This register field is used to access the 64 x 10 register file resided in the DLL. A 10-bit (hif_hd_in[9:0]) programming instruction can be written to the register file from HIF through the host data bus during write access (hif_rnw = 0; hif_dll_sel = 1). For read access (hif_rnw = 1; hif_dll_sel = 1) from the register file, the contents of the addressing location (hif_dll_addr[8:2]) is driven on the host data output bus (hif_hd_out_z[9:0]) with the data ready signal (dll_hif_drdy) asserted.
15 res 9 8 dll_inst 2 1 res 0
Bits 2:0 8:2
Mode
Field Name Reserved
Description These bits are reserved. The 64 locations of the register file can be accessed through address bits (hif_dll_addr[8:2]) 0000000 to 0111111. Reserved.
Default
R/W
dll_iram
15:9
Reserved
July 1999 Rev.2.0
91
DLL Fine Offset Delay Registers (DLL_FN_OFST_REG ) Address: 0x05D00 This register stores the fine offset delay value, which can be programmed through the STORE instruction from the host to the DLL Instruction RAM. This delay is to adjust the overflow or underflow offset for the fine delay line. The delay value stored inside the fine offset registers can be accessed from HIF through the host data output (hif_hd_out_z[3:0]) for read only.
15 res 9 8 dll_fn_ofst_reg 2 1 res 0
Bits 2:0 8:2 15:9
Mode
Field Name
Description Reserved
Default
dll_fn_ofst_reg
When Address[8:2] is set at 1000000, the data stored in the fine offset registers can be accessed for read only. Reserved
92
July 1999 Rev.2.0
DLL Fine Delay Registers (DLL_FN_REG) Address: 0x05D04 This register stores the fine delay value, which can be programmed through the STORE instruction from the host to the DLL Instruction RAM. This delay value indicates the delay pointer position (in terms of number of inverter pairs being enabled) on the fine delay line. The delay value stored inside the fine delay registers can be accessed from HIF through the host data output (hif_hd_out_z[3:0]) for read only.
15 res 9 8 dll_fn_reg 2 1 res 0
Bits 2:0 8:2 15:9
Mode
Field Name Reserved
Description These bits are reserved. When Address[8:2] is set at 1000001, the delay value stored in the fine delay registers can be read to the host. These bits are reserved.
Default
dll_fn_reg Reserved
July 1999 Rev.2.0
93
DLL Gross Delay Registers (DLL_GR_REG) Address: 0x05D08 This register stores the gross delay value, which can be programmed through the STORE instruction from the host address to the DLL Instruction RAM. This delay value indicates the delay pointer position (in terms of number of delay cells being enabled) on the gross delay line. The data stored inside the gross delay registers can be accessed from HIF through the host data output (hif_hd_out_z[4:0]) for read only.
15 res 9 8 dll_gr_reg 2 1 res 0
Bits 2:0 8:2 15:9
Mode
Register Field Reserved
Description These bits are reserved. When Address[8:2] is set at 1000010, the data stored in the gross delay registers can be accessed for read only. These bits are reserved.
Default
dll_gr_reg Reserved
94
July 1999 Rev.2.0
DLL Offset Delay Registers (DLL_OFST_REG) Address: 0x05D0C This register stores the offset delay value, which can be programmed through the STORE instruction from the host address to the DLL Instruction RAM. This delay is a fixed phase offset between the internal sclk and the external SDRAM clock. The data stored inside the offset delay registers can be accessed from HIF through the host data output (hif_hd_out_z[4:0]) for read only.
15 res 9 8 dll_ofst_reg 2 1 res 0
Bits 2:0 8:2 15:9
Mode
Field Name Reserved
Description These bits are reserved. When Address[8:2] is set at 1000011, the data stored in the offset delay registers can be accessed for read only. These bits are reserved.
Default
dll_ofst_reg Reserved
July 1999 Rev.2.0
95
DLL Reset Registers (DLL_RST_REG) Address: 0x05D10 This register stores the reset value, which can be programmed through the STORE instruction from the host address to the DLL Instruction RAM. The reset value . The data stored inside the reset registers can be written from HIF through the host data bus (hif_hd_in[0]) during write access (hif_rnw = 0; hif_dll_sel = 1). For read access (hif_rnw = 1; hif_dll_sel = 1) from the reset register, the content of the register can be read through the host data output bus (hif_hd_out_z[0]) with data ready signal (dll_hif_drdy) asserted.
15 res 9 8 dll_rst_reg 2 1 res 0
Bits 2:0 8:2 15:9
Mode
Field Name Reserved
Description These bits are reserved. When Address[8:2] is set at 1000100, the data stored in the reset registers can be accessed for read/write. These bits are reserved.
Default
R/W
dll_rst_reg Reserved
96
July 1999 Rev.2.0
DLL PCLK Delay Registers (DLL_PCLK_DLY_REG) Address: 0x05D14 This register stores the pclk delay value, which can be programmed through the STORE instruction from the host address to the DLL Instruction RAM. The pclk delay value can be written to the pclk delay registers from HIF through the host data bus (hif_hd_in[4:0]) during write access (hif_rnw = 0; hif_dll_sel = 1). For read access (hif_rnw = 1; hif_dll_sel = 1) from the pclk delay registers, the data stored inside the registers can be read through the host data output bus (hif_hd_out_z[4:0]) with data ready signal (dll_hif_drdy) asserted.
15 res 9 8 dll_pclk_dly_reg 2 1 res 0
Bits 2:0 8:2 15:9
Mode
Field Name Reserved
Description These bits are reserved. When Address[8:2] is set at 1000101, the data stored in the pclk delay registers can be accessed for read/write. Reserved.
Default
R/W
dll_pclk_dly_reg Reserved
July 1999 Rev.2.0
97
DLL SCLK Offset Registers (DLL_SCLK_OFST_REG) Address: 0x05D18

This register stores the sclk_mifin offset delay value, which can be written from the Host through the host data bus (hif_hd_in[4:0]) during write access (hif_rnw=0; hif_dll_sel=1). This delay is a fixed phase offset between the internal sclk and sclk_mifin which clocks the data receiving from SDRAM. The data stored inside the sclk_mifin offset delay registers can also be read from the Host through the host data output (hif_hd_z[4:0]).
15 res 9 8 dll_sclk_ofst_reg 2 1 res 0
Bits 1:0 8:2
Mode
Field Name Reserved
Description These bits are reserved. When Address[8:2] is set at 1000110, the data stored in the sclk_mifin offset delay registers can be read or written through hif_hd_z[4:0]. Reserved.
Default
dll_sclk_ofst_reg
15:9
Reserved
98
July 1999 Rev.2.0
8.0 8.1
DISPLAY PROCESSOR ARCHITECTURE REGISTERS DPC REGISTERS

A word in this section refers to a memory word i.e. 64-bit. Most registers are shadowed by an onchip memory, and actual controls are updated during a vertical blanking. A side-effect is that shadowed registers do not contain the default value upon chip reset, although the actual control registers are set with proper default values. Some registers are not shadowed, and they take effect immediate upon programming. These registers are marked with Not Shadowed.
Table 8.9: Register Name
DPC Register Map

DPC Registers (Base Address : 0x10000)

DPC Configuration Register (DPC_CONFIG_REG) DPC Status (DPC_STATUS_REG) DPC Interrupt Enable (DPC_INT_EN_REG) DPC Interrupt Status Register (DPC_INT_STAT_REG) DPC Display Count (DPC_DISP_COUNT_REG) DPC Sync Parameter 1 (DPC_SYNC_PARAM1_REG) DPC Sync Parameter 2 (DPC_SYNC_PARAM2_REG) DPC Sync Parameter 3 (DPC_SYNC_PARAM3_REG) DPC Sync Parameter 4 (DPC_SYNC_PARAM4_REG) DPC Sync Delay 1 (DPC_SYNC_DELAY1_REG) DPC Sync Delay 2 (DPC_SYNC_DELAY2_REG) DPC Background Accumulated Luma Register (DPC_BG_CUMLUMA_REG) DPC Overlay Accumulate Luma Register (DPC_OVL_CUMLUMA_REG) DPC Background Configuration Register (DPC_BG_CONFIG_REG) DPC Background Color Register (DPC_BG_COLOR_REG) DPC Background Video Source Configuration Register (DPC_BVDOSRC_CFG1_REG) DPC Background Video Source Configuration Register (DPC_BVDOSRC_CFG2_REG) DPC Background Video Window Configuration 1 Register (DPC_BVDOWIN_CFG1_REG) DPC Background Video Window Configuration 2 Register (DPC_BVDOWIN_CFG2_REG) 0x10000 0x10004 0x10008 0x1000C 0x10010 0x10014 0x10018 0x1001C 0x10020 0x10024 0x10028 0x1002C 0x10030 0x10040 0x10044 0x10048 0x1004C 0x10050 0x10054 page 102 page 104 page 105 page 106 page 107 page 108 page 109 page 110 page 111 page 112 page 113 page 114 page 115 page 116 page 118 page 119 page 120 page 121 page 122
July 1999 Rev.2.0
99
DPC Background Video SC Configuration 1 Register (DPC_BVDO_SC_CFG1_REG) DPC Background Video SC Configuration 2 Register (DPC_BVDO_SC_CFG2_REG) DPC Background Video HS Control 1 Register (DPC_BVDO_HS_CTL1_REG) DPC Background Video HS Control 2 Register (DPC_BVDO_HS_CTL2_REG) DPC Background Video VS Control 1 Register (DPC_BVDO_VS_CTL1_REG) DPC Background Video VS Control 2 Register (DPC_BVDO_VS_CTL2_REG) DPC Background Video Initial V Phase Register (DPC_BVDO_IVPH_REG) DPC Overlay Configuration Register (DPC_OVL_CONFIG_REG) DPC Overlay Display List Start Address Register (DPC_OVL_DLIST_SA_REG) DPC Overlay Plane Start Address Register (DPC_OVL_SA_REG) DPC Overlay Size Register (DPC_OVL_SIZE_REG) DPC Overlay Position Register (DPC_OVL_POS_REG) DPC Global Alpha Register (DPC_GALPHA_IBASE_REG) DPC Overlay Maximum Color Key Register (DPC_OVL_MAX_KEY_REG) DPC Overlay Minimum Color Key Register (DPC_OVL_MIN_KEY_REG) DPC Overlay Filter Co-efficients Register (DPC_OVL_FLTR_COEF_REG) DPC Overlay Display List 1 Register (DPC_OVL_DLIST1_REG) DPC Overlay Display List 2 Register (DPC_OVL_DLIST2_REG) DPC Auxiliary Display Configuration Register (DPC_AUX_CONFIG_REG) DPC Auxiliary Display Position Register (DPC_AUX_POS_REG) DPC Auxiliary Display Horizontal Size Control Register (DPC_AUX_HS_CTL_REG) DPC Auxiliary Display Vertical Size Control Register (DPC_AUX_VS_CTL_REG) DPC Auxiliary Display Programmable 1 Timing Register (DPC_AUX_PROG1_REG) DPC Auxiliary Display Programmable 2 Timing Register (DPC_AUX_PROG2_REG)
0x10058 0x1005C 0x10060 0x10064 0x10068 0x1006C 0x10070 0x10080 0x10084 0x10088 0x1008C 0x10090 0x10094 0x10098 0x1009C 0x100A0 0x100A4 0x100A8 0x100C0 0x100C4 0x100C8 0x100CC 0x100D0 0x100D4
page 123 page 124 page 125 page 126 page 127 page 128 page 129 page 130 page 132 page 133 page 134 page 135 page 136 page 137 page 138 page 139 page 140 page 142 page 143 page 144 page 145 page 146 page 147 page 148
100
July 1999 Rev.2.0
DPC Auxiliary Display Programmable 3 Timing Register (DPC_AUX_PROG3_REG) DPC Cursor Start Address Register (DPC_CURS_SA_REG) DPC Cursor Position Register (DPC_CURS_POS_REG) DPC CUrsor Offset Register (DPC_CURS_OFFSET_REG) DPC Cursor Color Look UP Table (DPC_CURSCLUTn_REG; n = 0 to 15) DPC Memory Address Register (DPC_MEM_ADDR_REG) DPC Memory Data Register (DPC_MEM_DATA_REG) DPC GPIO Enable Register (DPC_GPIO_EN_REG) DPC GPIO Output Enable Register (DPC_GPIO_OUT_EN_REG) DPC GPIO Output Data Register (DPC_GPIO_OUTDATA_REG) DPC GPIO Input Data Register (DPC_GPIO_INDATA_REG) DPC Sync Pulse Generator Configuration 1 Register (DPC_SPG_CONFIG1_REG) DPC Sync Pulse Generator Configuration 2Register (DPC_SPG_CONFIG2_REG) DPC Sync Pulse Generator Configuration 3 Register (DPC_SPG_CONFIG3_REG) DPC_SPG_PCONFIG_REG
0x100D8 0x10100 0x10104 0x10108 0x101400x1017C 0x10180 0x10184 0x10190 0x10194 0x10198 0x1019C 0x101A0 0x101A4 0x101A8 0x101AC
page 149 page 150 page 151 page 152 page 153 page 154 page 155 page 158 page 159 page 160 page 161 page 162 page 163 page 164 page 165
July 1999 Rev.2.0
101
DPC Configuration Register (DPC_CONFIG_REG) Address: 0x10000

31 19 18 DPC_ AUX_ CLIP_ MODE 8 7 6 5 4 3 2 17 16
Reserved
DPC_ DPC_ PRM_ CURS_ CLIP_ MODE MODE 1 0
15
14
13
12
11
10
DPC_ DPC_ DPC_ DPC_ DPC_ DPC_ DPC_ DPC_ DPC_ DPC_ DPC_STRM_DAC DPC_DIGITAL_ VDAC_ VDAC_ VDAC_ PRM_ DPC_ DPC_ DIGITAL VDAC_ PRM_ CURS_ BVDO_ CURRENT SEL OUT SYNC_ BLNK_ TPAT_ VOUT_ AUX_EN OVL_EN _IN EN YCCOUT EN EN _FIELD EN SEL EN EN
Bits 0
Mode RW
Field Name DPC_CURRENT_ FIELD
Description When the source is interlace, and the display is progressive, this bit indicates the current field being fetched from frame buffer. Otherwise, this bit indicates the current field of display raster. 0=> top field 1=> bottom field Enable display of background video. When set, the video source from memory is displayed as the background video. When reset, the TL850 background graphics is displayed: color bar or background color. Enable display of overlays. When set, DPC displays according to a display list of different regions. Enable display of hardware cursor. When set, DPC displays the hardware cursor stored in the TL850 graphics memory. Set to enable the auxuliary video. Toggling this bit resets the auxiliary video circuit. Set to enable the primary video output. When reset, DPC does not produce video synchronization. Video blanking level is produced at the output. Note that video DAC must be turned off separately. Set to enable the primary video output in a YCbCr format. When reset, the output is in a RGB format. Reset to enable the DPC primary video DACs. Set to display a color bar. When reset, the primary output is displayed. Note that, if DPC_PRM_VOUT_EN is reset, then primary video is always black without syncs. Set to enable a 7.5 IRE pedestal for the blanking interval. Set to enable generation of sync in the green DAC outputs. The magnitude of the sync pulse is 40IRE.
Default 1
RW
DPC_BVDO_EN
2 3
RW RW
DPC_OVL_EN DPC_CURS_EN
0 0
4 5
RW RW
DPC_AUX_EN DPC_PRM_VOUT_EN
0 0
6 7 8
RW RW RW
DPC_PRM_YCCOUT DPC_VDAC_EN DPC_VDAC_TPAT_EN
0 1 1
9 10
RW RW
DPC_VDAC_BLNK_ SEL DPC_VDAC_SYNC_EN
0 0
102
July 1999 Rev.2.0
Bits 12:11
Mode RW
Field Name DPC_DIGITAL_OUT
Description This field controls the configuration of the digital video stream output port. Unused output are used as GPIO pins. 00: No digital video output provided. 01: 8-bit digital video port streams multiplexed YCbCr in the Bt. 601/656 format, synchronized with the primary display clock. Supported for NTSC/PAL primary output formats. The digital output is gpio_grn[7:0]. 10: 16-bit digital video port streams YCC422 luma and chroma. Luma is gpio_grn[7:0], and chroma is gpio_red[7:0]. 11: 24-bit digital video port streams YCC444 or RGB. Luma or Green is gpio_grn[7:0]. Cr or Red is gpio_red[7:0]. Cb or Blue is gpio_blu[7:0]. This field can be configured to stream the selected DACs input to the auxuliary video port. 00: Auxiliary ITU-656/601 video out 01: DAC1 (R) 10: DAC2 (G) 11: DAC3 (B) Set to bypass the regular DAC pixel inputs with the value of external 24-pin digital video pins. Also, the external hsync and vsync pins are used to drive the blank and sync input to the DAC. Set to enable Microsoft cursor mode. When set, the 0xff value in cursor alpha channel will cause the cursor pixel to be transparent, and the background pixel to be inverted as not(background pixel). Set to clip blended pixels to legal range of CCIR-601 luma and chroma. Reset to clip to 0x01 and 0xfe. Set to clip blended pixels to legal range of CCIR-601 luma and chroma. Reset to clip to 0x01 and 0xfe. Reserved
Default 00
14:13
RW
DPC_STRM_DACSEL
00
15
RW
DPC_DIGITAL_IN
16
RW
DPC_CURS_MODE
17 18 31:19
RW RW R
DPC_PRM_CLIP_ MODE DPC_AUX_CLIP_ MODE Reserved
0 0 0
July 1999 Rev.2.0
103
DPC Status (DPC_STATUS_REG) Address: 0x10004

31 res 15 DPC_HCOUNT 30 DPC_VCOUNT 8 7 6 5 4 20 19 res 3 2 18 DPC_HCOUNT 1 0 16
DPC_ DPC_ DPC_ DPC_ DPC_ DPC_ DPC_ DPC_ OVL_ BG_ AUX_ AUX_ AUX_ PRM_ PRM_ PRM_ UFLOW UFLOW VOUT_F VOUT_V VOUT_H VOUT_F VOUT_V VOUT_H
Bits 0 1 2 3 4 5 6
Mode R R R R R R R
Field Name DPC_PRM_VOUT_H DPC_PRM_VOUT_V DPC_PRM_VOUT_F DPC_AUX_VOUT_H DPC_AUX_VOUT_V DPC_AUX_VOUT_F DPC_BG_UFLOW
Description Set according to primary display sync code H Set according to primary display sync code V Set according to primary display sync code F. If display is in progressive mode, then F is always zero. Set according to CCIR-601 sync code H Set according to CCIR-601 sync code V Set according to CCIR-601 sync code F Set when the bg memory buffer underflows. The underflow may be due to either backgrond video or background graphics. This bit is cleared upon read. If underflow occurs, then the previous pixel is repeated on the screen. Set when the overlay underflows due to lack of DRAM bandwidth. This bit is cleared upon read. If underflow occurs, then the previous pixel is repeated on the screen. Primary display horizontal pixel count. This count is reset at the beginning of line when H transition from high to low. The counter continues to count during blanking. Reserved Primary vertical field line count. This count is reset at the first active line of a field. The counter continues to count during blanking. Generally, this is at the same time as the V transitions from high to low. However, for first field of NTSC, its one line after the V transition. Reserved
Default
DPC_OVL_UFLOW
18:8
DPC_HCOUNT
0x000
19 30:20 R
res DPC_VCOUNT
0x000
31
104
July 1999 Rev.2.0
DPC Interrupt Enable (DPC_INT_EN_REG) Address: 0x10008

31 Reserved 15 12 11 10 9 8 7 6 5 4 3 2 1 0 16
Reserved
DPC_ DPC_ DPC_ DPC_ DPC_ DPC_ IDX_ AUX_ AUX_ MEM_ DISPL_ EOF1_ OF_INT OF_INT UF_INT UF_INT INT INT
DPC_ DPC_ DPC_ DPC_ DPC_ DPC_ HVSYNC VSYNCC HSYNCC SYNCAC SYNCLO EOF0_ CNT_ NT_ NT_ Q_ SS_ INT INT INT INT INT INT
Bits 0 1 2 3 4 5 6 7
Mode RW RW RW RW RW RW RW RW
Field Name DPC_SYNCLOSS_INT DPC_SYNCACQ_INT DPC_HSYNCCNT_INT DPC_VSYNCCNT_INT DPC_HVSYNCCNT_ INT DPC_EOF0_INT DPC_EOF1_INT DPC_DISPL_INT
Description Synchronization loss in primary display. Video synchronization is acquired after loss-of-sync Horizontal sync count (DPC_LINE_COUNT) reaches zero. Vertical sync count (DPC_FRAME_COUNT) reaches zero. Both vertical and horizontal sync counts have reached zero. End of active field 0 (F=0, V from 0 to 1) has been reached End of active field 1 (F=1, V from 0 to 1) has been reached Display list interrupt. This interrupt is asserted when a display entry with the interrupt enable bit set is being displayed. At least one of the on-chip display buffers has underflowed. Auxiliary buffers had underflowed. Auxiliary buffers had overflowed. The index base addition has overflowed during display of an index overlay format. Reserved
Default
8 9 10 11 31:12
RW RW RW RW
DPC_MEM_UF_INT DPC_AUX_UF_INT DPC_AUX_OF_INT DPC_IDX_OF_INT
July 1999 Rev.2.0
105
DPC Interrupt Status Register (DPC_INT_STAT_REG) Address: 0x1000C

31 DPC_DIPL_INT_CNT 15 Reserved 10 9 8 7 6 5 24 23 Reserved 4 3 2 1 0 16
DPC_INT_STAT
Bits 9:0 23:10 31:24
Mode R
Field Name DPC_INT_STAT
Description Interrupt status. Reset on read. The interrupt conditions are already listed above. Not Shadowed Reserved
Default
DPC_DIPL_INT_CNT
Reset to zero on read. A number greater than one indicates the number of display interrupts.
106
July 1999 Rev.2.0
DPC Display Count (DPC_DISP_COUNT_REG) Address: 0x10010

31 Reserved 15 Reserved 11 10 9 8 7 6 5 24 23 DPC_FRAME_COUNT 4 3 2 1 0 16
DPC_LINE_COUNT
Bits 10:0
Mode RW
Field Name DPC_LINE_COUNT
Description A value can be programmed into this register. The register is decremented when H transitions from low to high until zero is reached. An interrupt condition may be enabled when zero is reached. Upon end of field when F transitions, the counter is reloaded with the original counter value for decrementing. Reserved A value can be programmed into this register. The register is decremented at the end of a frame, when V transitions from low to high, until zero is reached. An interrupt condition may be enabled when zero is reached. If the display is field based, then the field is counted. Reserved
Default 0x000
15:11 23:16 RW
Reserved DPC_FRAME_COUNT
0x000
31:24
Reserved
July 1999 Rev.2.0
107
DPC Sync Parameter 1 (DPC_SYNC_PARAM1_REG) Address: 0x10014

31 30 29 28 27 26 DPC_PIX_PER_LINE 16
DPC_ DPC_ DPC_ DPC_ DPC_ DISP_ OUTPUT_ SYNCSIG SYNCSIG_ SYNCCODE_ RESET FIELD _HVIND EN EN 15 12 11 10 9 8 7 6
DPC_VSYNC_DELAY
Reserved
DPC_ DPC_ SYNC_ SYNC_ PROGSS MODE
DPC_ DPC_ TRS_ PRM_ WIDTH CLKSEL
Bits 0
Mode RW
Field Name DPC_PRM_CLKSEL
Description Set to use the external video clock divided by 2 as the pixel clock (pclk). Generally, this bit is reset so that the display subsystem uses the pixel clock provided by the external primary display without any modification. Set to indicate 4 samples per timing reference signals (i.e. EAV and SAV) as per SMPTE 274M and SMPTE 296M. Reset for 2 samples as per ITU-R 601 and SMPTE 293M. Selection of synchronization reference for input of the synchronization generator. Note that both video ouputs have the same video frame time. 0=> Primary video output is the synchronization reference. The HSYNC/VSYNC pins of the primary video output is used as inputs to the synchronization generator. 1=> Synchronization generator is free running. When this value is set, the synchronization generator is reset to the beginning of a frame. Set to output progressive synchronization. Reserved
Default 0
RW
DPC_TRS_WIDTH
RW
DPC_SYNC_MODE
3 5:4 15:6 26:16 27 28 29
RW RW RW RW RW RW RW
DPC_SYNC_PROGSS
DPC_VSYNC_DELAY DPC_PIX_PER_LINE DPC_SYNCCODE_EN DPC_SYNCSIG_EN DPC_SYNCSIG_HVIND
The delay, in samples from the beginning for the active line to the assertion of Vsync in the second field. The number of pixel samples on the active line. Set to enable output of embedded sync codes, including any parity code. Set to enable output of sync signal. When primary display is the slave, then DPC_SYNCSIG_EN bit is ignored. Set to output H and V indicators instead of hsync and vsync. For this bit to be in effect, DPC_SYNCSIG_EN has to be set. When the primary display is the synchronization master, set interpret venc_h_i as H and venc_v_i as F. Reset to interpret vinc_h_i as hsync and venc_v_i as vsync. Set to output dpc_field instead of dpc_vsync_o. Vsync is output by reseting this bit. When primary display is the synchronization master, this bit is ignored. Set this bit to reset circuits in the display clock domain. This bit is used to switch setting of the display PLL. 1 1 0
30
RW
DPC_OUTPUT_FIELD
31
RW
DPC_DISP_RESET
108
July 1999 Rev.2.0

31 Reserved 15 DPC_HSYNC_WIDTH 12 11 Res 10 9 29 28 DPC_BACK_PORCH 8 DPC_FRONT_PORCH 20 19 Res 18 16
DPC_HSYNC_WIDTH 0
DPC_ DPC_ VSYNC_ HSYNC_ INVERSE INVERSE
Bits 8:0 9
Mode RW RW
Field Name DPC_FRONT_PORCH DPC_HSYNC_ INVERSE
Description The number of samples between the EAV symbol and the falling edge of the negative sync pulse. Set to invert polarity of dpc_hsync_o output pins. The polarity when reset is active low for hsync. When primary display is the synchronization master, then this bit determines the active polarity of venc_h_i input pin. Set to invert polarity of dpc_vsync_o output pins. The polarity when reset is active low for vsync, and active high for field. When primary display is the synchronization master, then this bit controls the polarity of vinc_v_i. When this bit is reset, venc_v_i low means field 0. Venc_v_i is never interpreted as the vsync or V when encoder is the master. Reserved. The width, in samples, of the horizontal sync pulse. Reserved The number of samples between rising edge of the negative sync pulse and the SAV symbol. Reserved
Default
10
RW
DPC_VSYNC_ INVERSE
11 18:12 19 28:20 31:29
R RW
Res DPC_HSYNC_WIDTH Reserved
RW
DPC_BACK_PORCH Reserved
July 1999 Rev.2.0
109
DPC Sync Parameter 3 (DPC_SYNC_PARAM3_REG) Address: 0x1001C

31 Reserved 29 28 DPC_FIELD0 _NTSC 12 DPC_FIELD0_ACTIVE 11 DPC_FIELD)_TOP 27 DPC_FIELD0_BOTTOM 24 23 Res 22 DPC_FIELD0_ACTIVE 16
15
3 Res
DPC_FIELD0_VSYNC
Bits 2:0
Mode RW
Field Name DPC_FIELD0_VSYNC
Description The number of scan lines occupied by the vertical sync pulse. Assertion of the vertical sync coincides with the horizontal datum. Assertion of the vertical sync coincides with the horizontal datum. Reserved The number of scan lines between the end of sync and the beginning of active video in the first field. The number of scan lines in the active video region of the first field. Reserved
Default
3 11:4 22:12 23 27:24 RW RW RW
Reserved DPC_FIELD0_TOP DPC_FIELD0_ACTIVE
DPC_FIELD0_BOTTOM
The number of scan lines between the end of the active video region of the first field and the beginning of the second field. The video is blanked during this region. Set this bit to drop the V indicator one line earlier. This bit is used to support NTSC where vertical blanking interval is one line longer than the V indicator. Reserved
28
RW
DPC_FIELD0_NTSC
31:29
110
July 1999 Rev.2.0

31 Reserved 15 DPC_FIELD1_ACTIVE 12 28 27 24 23 Res 22 DPC_FIELD1_ACTIVE 4 DPC_FIELD1_TOP 3 Res 2 0 16
DPC_FIELD1_BOTTOM 11
DPC_FIELD1_VSYNC
Bits 2:0
Mode RW
Field Name DPC_FIELD1_VSYNC
Description The number of scan lines occupied by the second field vertical sync pulse. The second field vertical sync is delayed by the amount in the DPC_VSYNC_DELAY register from the horizontal datum. (see DPC_SYNC_PARAM1 register) Reserved
Default
3 11:4 22:12 23 27:24 RW DPC_FIELD1_BOTTOM RW RW DPC_FIELD1_TOP DPC_FIELD1_ACTIVE
The number of scan lines between the end of sync and the beginning of active video in the second field. The number of scan lines in the active video region of the second field. Reserved The number of scan lines between the end of the active video region of the second field and the beginning of the first field. The video is blanked during this region. Reserved
31:28
July 1999 Rev.2.0
111
DPC Sync Delay 1 (DPC_SYNC_DELAY1_REG) Address: 0x10024

31 DPC_LINES_TO_SYNC 28 27 Reserved 25 24 DPC_ SDELAY _EN1 23 Reserved 22 21 DPC_SYNC_DELAY_V1 16
15 DPC_SYNC_DELAY_V1
Bits 21:0
Mode RW
Field Name DPC_SYNC_DELAY_ V1
Description The synchronization delay is counted in terms of video clock cycle. The output of this sync generator can be the delayed version of the primary display sync. The sync generator can also be free running. The output serves as timing references for the DPC core. Reserved
Default
23:22 24 27:25 31:28 RW DPC_LINES_TO_SYNC RW DPC_SDELAY_EN1
Set to enable the delay counter 1. Reserved The value of this field is the number of proper consecutive video lines before line synchronization lock is achieved. After the line synchronization lock, DPC attempts to find the F indicator for the first field. After this, the proper video synchronization are generated based on F. This field is also the number of improper consecutive video lines before loss of sync is detected. An interrupt can be optionally generated when loss of sync is detected.
112
July 1999 Rev.2.0
DPC Sync Delay 2 (DPC_SYNC_DELAY2_REG) Address: 0x10028

31 Reserved 25 24 DPC_ SDELAY _EN2 11 DPC_SYNC_DELAY_V2 23 Reserved 16
15 Reserved
12
Bits 11:0
Mode RW
Field Name DPC_SYNC_DELAY_ V2
Description The synchronization delay is counted in terms of video clock cycle. The output of this sync generator is the delayed version of the sync generated by the first synchronization generator. The output serves as timing references for the display interface unit (DIF.) Reserved
Default
23:12 24 31:25 RW DPC_SDELAY_EN2
Set to enable the delay counter 2. Reserved
July 1999 Rev.2.0
113
DPC Background Accumulated Luma Register (DPC_BG_CUMLUMA_REG) Address: 0x1002C

31 Reserved 15 12 11 DPC_BG_CUMLUMA 28 27 25 24 23 22 21 16
DPC_BG_CUMLUMA 4 3 2 0
Bits 27:0
Mode R
Field Name DPC_BG_CUMLUMA
Description Accumulated luma of background outside of the overlay region. The information within this register is used by the system to adjust scaled video intensity. The content is an accumulation of each background pixel not covered by the scaled video. The content is cleared automatically at the first line of next frame. Not Shadowed Reserved
Default 0x0000 00
31:28
114
July 1999 Rev.2.0
DPC Overlay Accumulate Luma Register (DPC_OVL_CUMLUMA_REG) Address: 0x10030

31 Reserved 15 DPC_OVL_CUMLUMA 28 27 DPC_OVL_CUMLUMA 0 16
Bits 27:0
Mode R
Field Name DPC_OVL_CUMLUMA
Description Accumulated luma of active region of overlay after compositing with the background. The information within this register is used by the system to adjust scaled video intensity. The content is an accumulation of each scaled video pixel not including the background. The content is cleared automatically at the first line of next frame. Not Shadowed Reserved
Default 0x0000 00
31:28
July 1999 Rev.2.0
115
DPC Background Configuration Register (DPC_BG_CONFIG_REG) Address: 0x10040

31 Reserved 15 DPC_ BG_BW MODE 14 12 11 DPC_BVDO_VFLR_ TAP 8 7 6 5 4 3 2 1 0 16
DPC_THROUGHPUT
DPC_ DPC_ DPC_ BVDO_ BVDO_ BVDO_ VLUVFLR_ NUI_EN MOFF EN
DPC_ DPC_ DPC_ BVDO_ DPC_BVDO_FLD_ BVDO_ BVDO_ HFLR_ CFG FMT422 MPEG1 EN
Bits 1:0
Mode RW
Field Name DPC_BVDO_FLD_CFG
Description Configuration of source memory and display formats. 00=> Both source and display are in the frame format. Consecutive lines in time are fetched alternatively from two fields. 01=> Video source is fetched using the field format for progressive frame display. The starting phase of the source must be adjusted according to the source field. 10=> Video source is fetched using the frame format for field display fomat. The starting phase of the display must be adjusted according to the display field. 11=> Both source and display are in the field foramt. Conscutive lines in time are fetched from the same field. The user specifies data formats in this field. Parameters of ypos are specified in terms of a frame picture. For example, a line with odd ypos in an interlace picture is always in the bottom field. Settings of scaling circuit must account for different formats of source and display. Set to adjust display for MPEG1 style frame buffer. Set to interpret video frame buffer as 4:2:2 format. When reset, 4:2:0 format is assumed. When set, the vertical scale factor, dpc_bvdo_vfs1, must not exceed 1.0. Thus, down-conversion and a progressive source displayed on an interlaced display (i.e., when dpc_bvdo_fld_cfg = 2) are not allowed. Set to enable the video horizontal filter. Set to enable the video vertical filter. Set to turn off the luma portion of the vertical filter. This bit is used to conserved memory bandwidth when luma is not filtered and chroma is filtered. An application is to display from 480P to 480I which has interlace luma and progressive chroma frame. Set to enable the nonuniform interpolation. The number of vertical taps used for vertical graphics filtering. The reduction of vertical taps allows for reduced memory bandwidth. The range is 1, 2 or 3. For horizontal source width greater than 1440 pixels, this field must be one. For horizontal source greater than 720 pixels, this field must be two.
Default
2 3
RW RW
DPC_BVDO_MPEG1 DPC_BVDO_FMT422
0 0
4 5 6
RW RW RW
DPC_BVDO_HFLR_EN DPC_BVDO_VFLR_EN DPC_BVDO_VLUMOFF
0 0 0
7 11:8
RW RW
DPC_BVDO_NUI_EN DPC_BVDO_VFLR_ TAP
0 0x2
116
July 1999 Rev.2.0
Bits 14:12
Mode RW
Field Name DPC_THROUGHPUT
Description The field controls the throughput of the video pipeline. The value indicates the number of cycles per generated pixel. The value 0x0 indicates the throughput of 8 cycles per pixel. Note: at throughput of one, the maximum horizontal scaling factor cannot be greater than 1.0. Set to display background as black and white Reserved.
Default 0x1
15 31:16
RW R
DPC_BG_BWMODE Reserved
July 1999 Rev.2.0
117
DPC Background Color Register (DPC_BG_COLOR_REG) Address: 0x10044

31 Reserved 15 DPC_BG_COLOR 24 23 DPC_BG_COLOR 0 16
Bits 23:0 31:24
Mode RW
Field Name DPC_BG_COLOR
Description Default background graphics color in 24-bit YCbCr Reserved.
Default 0x23d4 72
118
July 1999 Rev.2.0
DPC Background Video Source Configuration Register (DPC_BVDOSRC_CFG1_REG) Address: 0x10048

31 Res 30 DPC_BVDOSRC_YPOS 20 19 18 17 16
Reserved
DPC_BVDOSRC_ XPOS 0
15 DPC_BVDOSRC_XPOS
7 DPC_BVDO_BOTBASE
3 DPC_BFDO_TOPBASE
Bits 3:0 7:4 17:8 19:18 30:20
Mode RW RW RW R RW
Field Name DPC_BVDO_TOPBASE DPC_BVDO_BOTBASE DPC_BVDOSRC _XPOS Reserved DPC_BVDOSRC_ YPOS
Description Selects one of 16 base registers in MIF containing the top field buffer address. Selects one of 16 base registers in MIF containing the bottom field buffer address. The x-position of source fields in number of 16-pixel groups. In other word, its the number of word-pairs. Reserved. The y-position of source image in number of pixels. This number is the y position accounting for both fields independent of content. The content can be either progressive or interlace material. Reserved.
Default 0x0 0x1 0
31
July 1999 Rev.2.0
119
DPC Background Video Source Configuration Register (DPC_BVDOSRC_CFG2_REG) Address: 0x1004C

31 Reserved 15 Reserved 11 10 DPC_BVDOSRC_WD 27 26 DPC_BVDOSRC_HT 0 16
Bits 10:0
Mode RW
Field Name DPC_BVDOSRC_WD
Description The width of source fields in number of pixels, starting at the pixel defined by DPC_BVDOSRC_XPOS and DPC_BVDO_FIRST_PIX. The minimum number is 16 pixels, and it must be an even width. Reserved. The height of source frame in number of pixels, accounting for both fields. This number shall be an even number, start at the line defined by DPC_BVDOSRC_YPOS. Note that MIF also requires a height parameter which is a sum of both luma lines and chroma lines within the buffer. The minimum number is 16 pixels. Reserved.
Default 0
15:11 26:16
R RW
Reserved. DPC_BVDOSRC_HT
31:27
Reserved
120
July 1999 Rev.2.0
DPC Background Video Window Configuration 1 Register (DPC_BVDOWIN_CFG1_REG) Address: 0x10050

31 Res 15 DPC_BVDOWIN_XPOS 30 DPC_BVDOWIN_YPOS 8 7 Reserved 4 20 19 Res 3 DPC_BVDO_FIRST_PIX 18 16
DPC_BVDOWIN_XPOS 0
Bits 3:0
Mode RW
Field Name DPC_BVDO_FIRST_ PIX Reserved DPC_BVDOWIN_XPOS Reserved DPC_BVDOWIN_YPOS
Description This field indicates the offset of the first pixel within the first two words of a video pixel row. The first pixel must be on an even pixel boundary. Reserved. The x-position of video display window in number of pixels. The x-position must be an even number. Reserved. The y-position of video display window in number of pixels. Reserved.
Default 0x0
7:4 18:8 19 30:20 31
R RW R RW
July 1999 Rev.2.0
121
DPC Background Video Window Configuration 2 Register (DPC_BVDOWIN_CFG2_REG) Address: 0x10054

31 Reserved 15 Reserved 11 10 DPC_BVDOWIN_WD 27 26 DPC_BVDOWIN_HT 0 16
Bits 10:0 15:11 26:16 31:27
Mode RW R RW R
Field Name DPC_BVDOWIN_WD Reserved DPC_BVDOWIN_HT Reserved
Description The width of video display window in number of pixels. The width must be an even number of pixel. Reserved. The height of video display window in number of pixels. Reserved.
Default 0
122
July 1999 Rev.2.0
DPC Background Video SC Configuration 1 Register (DPC_BVDO_SC_CFG1_REG) Address: 0x10058

31 Res 15 Reserved 12 11 8 7 28 27 DPC_BVDO_R_XPOS 6 5 4 3 0 16
DPC_BVDO_L_XPOS
Bits 11:0 15:12 27:16 31:28
Mode RW
Field Name DPC_BVDO_L_XPOS Reserved
Description The left pixel position of central region within video window. Reserved The right pixel position in central region within video window. Reserved.
Default
RW
DPC_BVDO_R_XPOS
July 1999 Rev.2.0
123
DPC Background Video SC Configuration 2 Register (DPC_BVDO_SC_CFG2_REG) Address: 0x1005C

31 Res 15 Reserved 12 11 DPC_BVDO_T_YPOS 28 27 DPC_BVDO_B_YPOS 0 16
Bits 11:0 15:12 27:16 31:28
Mode RW
Field Name DPC_BVDO_T_YPOS Reserved
Description The starting output pixel position in region 1 within window. Reserved The starting output pixel position in region 2 within window. Reserved.
Default
RW
DPC_BVDO_B_YPOS
124
July 1999 Rev.2.0
DPC Background Video HS Control 1 Register (DPC_BVDO_HS_CTL1_REG) Address: 0x10060

31 DPC_BVDO_HFM1 15 DPC_BVDO_HFN1 8 7 DPC_BVDO_HFS1 4 20 19 Res 3 Reserved 18 16
DPC_BVDO_HFN1 0
Bits 3:0 7:4
Mode RW RW
Field Name Reserved DPC_BVDO_HFS1
Description Must be set to zero. Horizontal filter step size between input and output samples. The MSB is the integer bit. The maximum setting is 0xc. The maximum is 0x8 if throughput is set to 1. Horizontal DDA parameter: HFN is positive. Reserved Horizontal DDA parameter: HFM is 2s complement.
Default
18:8 19 31:20
RW
DPC_BVDO_HFN1 Res
RW
DPC_BVDO_HFM1
July 1999 Rev.2.0
125
DPC Background Video HS Control 2 Register (DPC_BVDO_HS_CTL2_REG) Address: 0x10064

31 DPC_BVDO_HFM2 15 DPC_BVDO_HFN2 8 7 DPC_BVDO_HFS2 4 20 19 Res 3 Reserved 18 16
DPC_BVDO_HFN2 0
Bits 3:0 7:4
Mode RW RW
Field Name Reserved DPC_BVDO_HFS2
Description Must be set to zero. Horizontal filter step size between input and output samples. The MSB is the integer bit. The maximum setting is 0xc. The maximum is 0x8 if throughput is set to 1. Horizontal DDA parameter: HFN is positive. Reserved Horizontal DDA parameter: HFM is 2s complement.
Default
18:8 19 31:20
RW
DPC_BVDO_HFN2 Res
RW
DPC_BVDO_HFM2
126
July 1999 Rev.2.0
DPC Background Video VS Control 1 Register (DPC_BVDO_VS_CTL1_REG) Address: 0x10068

31 DPC_BVDO_VFM1 15 DPC_BVDO_VFN1 8 7 DPC_BVDO_VFS1 20 19 Res 3 2 Reserved 18 16
DPC_BVDO_VFN1 0
Bits 2:0 7:3
Mode RW RW
Field Name Reserved DPC_BVDO_VFS1
Description Must be set to zero. Vertical filter step size between input and output samples. Two MSBs are integer bits The maximum setting is 0x10 which corresponds to 2.0. As an example, setting of 2.0 is needed for 480P to 480I case where a 480-line frame is used to generate a 240-lines field. Vertical DDA parameter: VFN is positive. Reserved Vertical DDA parameter: VFM is 2s complement.
Default
18:8 19 31:20
RW
DPC_BVDO_VFN1 Res
RW
DPC_BVDO_VFM1
July 1999 Rev.2.0
127
DPC Background Video VS Control 2 Register (DPC_BVDO_VS_CTL2_REG) Address: 0x1006C

31 DPC_BVDO_VFM2 15 DPC_BVDO_VFN2 8 7 DPC_BVDO_VFS2 20 19 Res 3 2 Reserved 18 16
DPC_BVDO_VFN2 0
Bits 2:0 7:3 18:8 19 31:20
Mode RW RW RW
Field Name Reserved DPC_BVDO_VFS2 DPC_BVDO_VFN2 Res
Description Must be set to zero. Vertical filter step size between input and output samples. Two MSBs are integer bits. The maximum setting is 0x10. Vertical DDA parameter: VFN is positive. Reserved Vertical DDA parameter: VFM is 2s complement.
Default
RW
DPC_BVDO_VFM2
128
July 1999 Rev.2.0
DPC Background Video Initial V Phase Register (DPC_BVDO_IVPH_REG) Address: 0x10070

31 Reserved 15 DPC_BVDO_IVPH2BOT 12 11 8 7 DPC_BVDO_IVPH1BOT 24 23 DPC_BVDO_IVPH3BOT 4 3 DPC_BVDO_IVPH1TOP 20 19 DPC_BVDO_IVPH3TOP 0 16
DPC_BVDO_IVPH2TOP
Bits 3:0 7:4 11:8
Mode RW RW RW
Field Name DPC_BVDO_IVPH1TO P DPC_BVDO_ IVPH1BOT DPC_BVDO_ IVPH2TOP DPC_BVDO_ IVPH2BOT DPC_BVDO_ IVPH3TOP DPC_BVDO_ IVPH3BOT
Description The initial phase during scanning or displaying of a top video field. In a progressive case, this bit field is used. The initial phase during scanning or displaying of a bottom field. This is not used for a progressive case. The initial step to the central region during scanning or displaying of a top field. A progressive case uses this bit field. The initial step to the central region during scanning or displaying of a bottom field. This bit field is not used for a progressive case. The initial step to the lower region during scanning or displaying of a top field. A progressive case uses this bit field. The initial step to the lower region during scanning or displaying of a bottom field. This bit field is not used for a progressive Reserved.
Default
15:12
RW
19:16
RW
23:20
RW
31:24
July 1999 Rev.2.0
129
DPC Overlay Configuration Register (DPC_OVL_CONFIG_REG) Address: 0x10080

31 18 17 16
Reserved
DPC_ DPC_ OVL_ OVL_ BWYCCUB MODE 7 6 5 4 3 2 1 0
15
12
11
10
DPC_VFLTR_THRESH
DPC_ DPC_ DPC_ OVL_ VFLTR VFLTR ALPHA _TH_ _EN _PM EN
Res
DPC_GALPHA_ MODE2
DPC_GALPHA_ MODE1
Res
DPC_ DPC_ DPC_ GALPHA INDEX_ COLOR_ _EN KEY_EN KEY_EN
Bits 0
Mode RW
Field Name DPC_COLOR_KEY_EN
Description Enable the color keying operations for overlay. The overlay pixels are compared, separately for each color component, against upper and lower bound registers. Set to enable the index key operation when an index pixel mode is selected and the DPC_COLOR_KEY_EN is set. The blue max key registers is used to for the index keying operation. Set to enable the application of the global alpha value. Reserved
Default 0
RW
DPC_INDEX_KEY_EN
2 3 5:4
RW
DPC_GALPHA_EN
RW
DPC_GALPHA_MODE1
Select application of global alpha to implement 00=> global alpha not applied to RGB 01=> multiply RGB by global alpha 10=> multiply RGB by local alpha 11=> reserved Note: when 0x10 is set, the user must set bit 11, DPC_OVL_ALPHA_PM. Select application of global alpha to implement 00=> global alpha not applied 01=> replace local alpha with global alpha 10=> multiply local alpha by global alpha 11=> reserved Reserved Set to enable the vertical filtering. This mode supports antiflickering by filtering luma or alpha. The supported pixel formats are 8i, 4i and 2i. Set to enable the threshold checking during vertical filtering. If the pixel luminance before vertical filtering is below the threshold and vertical scaling factor is set to 1.0, then the original pixel before vertical filtering is used for display. Set when the graphics pixels have been premultiplied by the alpha channel.
00
7:6
RW
DPC_GALPHA_MODE2
00
8 9
RW RW
Reserved DPC_VFLTR_EN
10
RW
DPC_VFLTR_TH_EN
11
RW
DPC_OVL_ALPHA_PM
130
July 1999 Rev.2.0
Bits 15:12
Mode RW
Field Name DPC_VFLTR_ THRESH DPC_OVL_YCCUB DPC_OVL_BWMODE Reserved
Description Threshold register used to disable vertical filtering. The top 4-bit of threshold is set to the content of this register, and the bottom 4-bit of threshold is set to 0x8. Set to allow unbiased CbYCr bypass input. Set to display sgfx in black and white. Reserved
Default 0x00
16 17 31:18
RW RW R
0 0 0
July 1999 Rev.2.0
131
DPC Overlay Display List Start Address Register (DPC_OVL_DLIST_SA_REG) Address: 0x10084
31 Reserved 15 DPC_OVL_DLIST_SA 26 25 DPC_OVL_DLIST_SA 4 3 Reserved 0 16
Bits 3:0 25:4
Mode
Field Name
Default 00
RW
DPC_OVL_DLIST_SA
Overlay display list start word address. The address must be on the 2 word boundary. When the address is zero, there is no display list. Start address shall be on a pixel boundary. Reserved
31:26
132
July 1999 Rev.2.0
DPC Overlay Plane Start Address Register (DPC_OVL_SA_REG) Address: 0x10088

V
31 Reserved 15
26
25 DPC_OVL_SA 4 3 Reserved
16
DPC_OVL_SA
Bits 3:0 25:4 31:26
Mode
Field Name
Default 00
RW
DPC_OVL_SA
Overlay plane starting word address. The address must be a two-word boundary. Not Shadowed Reserved
July 1999 Rev.2.0
133
DPC Overlay Size Register (DPC_OVL_SIZE_REG) Address: 0x1008C

31 DPC_OVL_HEIGHT 15 DPC_OVL_WIDTH 10 9 DPC_OVL_PITCH 21 20 DPC_OVL_WIDTH 0 16
Bits 9:0
Mode RW
Field Name DPC_OVL_PITCH
Description Pitch (width) of graphic frame memory in multiple of of 8 words. The pitch must be in the multiple of 8 words. However, the DPC_SGFX_SA does not necessarily starts at an 8 word boundary. Width of region of interest in number of pixels. The width must be an even number of pixels. Note that this number mutiplied by the DPC_OVL_HSCALE must not be greater than 2048. Height of region of interest in number of progressive lines.
Default
20:10
RW
DPC_OVL_WIDTH
31:21
RW
DPC_OVL_HEIGHT
134
July 1999 Rev.2.0
DPC Overlay Position Register (DPC_OVL_POS_REG) Address: 0x10090

31 Reserved 15 Reserved 12 11 DPC_OVL_XPOS 27 26 21 DPC_OVL_YPOS 0 20 16
Bits 11:0 15:12 26:16 31:27
Mode RW
Field Name DPC_OVL_XPOS Reserved
Description Pixel position of region of interest relative to SAV code. The x-position must be on an even pixel boundary. Reserved Pixel vertical position of region of interest. Reserved.
Default
RW
DPC_OVL_YPOS Reserved
July 1999 Rev.2.0
135
DPC Global Alpha Register (DPC_GALPHA_IBASE_REG) Address: 0x10094

31 DPC_INDEX_BASE 15 DPC_OVL_CONTRST 28 27 Reserved 8 7 Reserved 24 23 DPC_OVL_BRIGHT 0 16
Bits 7:0 15:8
Mode R RW
Field Name Reserved DPC_OVL_CONTRST
Description Reserved. This scaling factor controls the contrast of overlay window. The factor 1.0 is defined to be 0x80 in hex number. The luma is multiplied by this factor. This 2s complement value is added to the luma of pixels in overlay window. The field controls the overlay windows brightness. Reserved. Base address of index table. When overlay frame buffer is in index mode. The top 4 bits of index is added to this index base register to produce the final index into the color look up table. If an overflow occurs, an optional interrupt may be taken.
Default
0x80
23:16
RW
DPC_OVL_BRIGHT
0x00
27:24 31:28
R RW
Reserved DPC_INDEX_BASE
0x00
136
July 1999 Rev.2.0
DPC Overlay Maximum Color Key Register (DPC_OVL_MAX_KEY_REG) Address: 0x10098

31 Reserved 15 DPC_MAX_GKEY 8 7 DPC_MAX_BKEY 24 23 DPC_MAX_RKEY 0 16
Bits 7:0
Mode RW
Field Name DPC_MAX_BKEY
Description The maximum blue color key register. This register is also used for matching index key register when one of the overlay index pixel mode is selected. The maximum green color key register The maximum red color key register Reserved
Default
15:8 23:16 31:24
RW RW
DPC_MAX_GKEY DPC_MAX_RKEY Reserved
July 1999 Rev.2.0
137
DPC Overlay Minimum Color Key Register (DPC_OVL_MIN_KEY_REG) Address: 0x1009C

31 Reserved 15 DPC_MIN_GKEY 8 7 DPC_MIN_BKEY 24 23 DPC_MIN_RKEY 0 16
Bits 7:0 15:8 23:16 31:24
Mode RW RW RW
Field Name DPC_MIN_BKEY DPC_MIN_GKEY DPC_MIN_RKEY Reserved
Description The minimum blue color key register.. The minimum green color key register The minimum red color key register Reserved.
Default
138
July 1999 Rev.2.0
DPC Overlay Filter Co-efficients Register (DPC_OVL_FLTR_COEF_REG) Address: 0x100A0

31 Reserved 15 Reserved 13 12 DPC_LUMA_COEFF1 29 28 DPC_ALLPHA_COEFF1 8 7 24 23 Reserved 6 5 DPC_LUMA_COEFF0 22 21 DPC_ALPHA_COEFF0 0 16
Reserved
Bits 5:0 7:6 12:8 15:13 21:16 23:22 28:24 31:29
Mode RW
Field Name DPC_LUMA_COEFF0 Reserved
Description Luma filter coefficient for the center tap. Reserved Luma filter coefficient for the outer taps. Reserved Alpha filter coefficient for the center tap. Reserved Alpha filter coefficient for the outer taps. Reserved
Default 0x20 = 1.0
RW
DPC_LUMA_COEFF1 Reserved
0x00 = 0.0
RW
DPC_ALPHA_COEFF0 Reserved
0x20 = 1.0
RW
DPC_ALPHA_COEFF1 Reserved
0x00 = 0.0
July 1999 Rev.2.0
139
DPC Overlay Display List 1 Register (DPC_OVL_DLIST1_REG) Address: 0x100A4

31 25 24 DPC_ OVL_ UNDR_ VDO 11 DPC_OVL_FIRSTPIX 8 7 6 5 23 16
Reserved
DPC_GLOBAL_ALPHA
15
14
13
12
3 DPC_OVL_PIXMODE
Reserved
DPC_ DPC_ DLIST_ DLIST_ EOL INT
DPC_VSCALE
DPC_HSCALE
Bits 3:0
Mode RW
Field Name DPC_OVL_PIXMODE
Description Selection of the overlay frame buffer formats 0000=> 8-bit alpha and 24-bit rgb color 0001=> 8-bit alpha and 16-bit rgb color 0010=> 8-bit alpha and 8-bit rgb color 0011=> 8-bit alpha and 8-bit index 0100=> 24-bit rgb color 0101=> 16-bit rgb color 0110=> 8-bit rgb color 0111=> 8-bit index 1000=> reserved 1001=> reserved 1010=> 4:2:2 CCIR-601 CbYCrY format 1011=> 2-bit index 1100=> 4-bit index 1101=> 4-bit alpha and 12-bit rgb color 1110=> 1-bit alpha and 15-bit rgb color 1111=> DVB compressed (not supported) The horizontal scale factor 01=> scaled by 1 10=> scaled by 2 11=> scaled by 3 00=> scaled by 4 The vertical scale factor 01=> scaled by 1 10=> scaled by 2 11=> scaled by 3 00=> scaled by 4 This field indicates the byte offset of the first pixel within the first two words of a video pixel row. This field allows for byte resolution of the starting pixel within two 8-byte word. The user has to program the corret byte offset according to the pixel mode (DPC_OVL_PIXMODE.) When this bit is set, the current display entry is causing an interrupt. This is a read only register. Set indicates the end of display list. The host can force the current display entry as the last entry.
Default 0000
5:4
RW
DPC_HSCALE
01
7:6
RW
DPC_VSCALE
01
11:8
RW
DPC_OVL_FIRSTPIX
0x0
12 13
R RW
DPC_DLIST_INT DPC_DLIST_EOL
140
July 1999 Rev.2.0
Bits 15:14 23:16 24 31:25
Mode RW RW
Field Name Reserved DPC_GLOBAL_ALPHA DPC_OVL_UNDR_VDO Reserved
Description Reserved Global alpha register for overlay blending. The value 0x80 corresponds to alpha of 1. Set to display the overlay plane as under the video plane. Reserved
Default
0x80 0x0
July 1999 Rev.2.0
141
DPC Overlay Display List 2 Register (DPC_OVL_DLIST2_REG) Address: 0x100A8

31 25 24 23 22 21 20 19 18 17 16
Reserved
DPC_ DPC_ DPC_ DPC_ DLIST_ DLIST_ DLIST_ DLIST_ PALLET PALLET MAP4 MAP2 8 4
DPC_DLIST_ LUTPTR
15 DPC_DLIST_LUTPTR
Bits 17:0
Mode RW
Field Name DPC_DLIST_LUTPTR
Description The field is the address of color look-up table descriptor used for the current overlay region. The color look-up descriptor contains upto 3 consecutive tables. A table exists in the descriptor if the corresponding bit is set. In addition, the content must reside on 32-word boundary, and this field is a 32-word address (not a byte address.) When set, the color look-up table descriptor contains the map from 2-bit per pixel to 8-bit index. When set, the color look-up table descriptor contains the map from 4-bit per pixel to 8-bit index. When set, the color look-up table descriptor contains the CLUT for first 16 entries. When set, the color look-up table descriptor contains the CLUT for the entire 256 entries. Reserved.
Default
18 19 20 21 31:22
RW RW RW RW
DPC_DLIST_MAP2 DPC_DLIST_MAP4 DPC_DLIST_PALLET4 DPC_DLIST_PALLET8 Reserved
142
July 1999 Rev.2.0
DPC Auxiliary Display Configuration Register (DPC_AUX_CONFIG_REG) Address: 0x100C0

31 Reserved 15 8 7 28 27 DPC_AUX_FIFO_TH 4 3 DPC_ AUX_ BWMODE 2 DPC_ AUX_ SRC_ SEL 1 DPC_ AUX_ SRC_ INTL 0 DPC_ AUX_ ITU60HZ 16
DPC_AUX_VDDA_PH
Reserved
Bits 0
Mode RW
Field Name DPC_AUX_ITU60HZ
Description Set for auxiliary video 50 Hz systems (e.g. PAL). When cleared, the 60 Hz auxiliary video timing is used. (e.g. NTSC) Set to indicate primary video is in interlace mode. When cleared, the primary video is progrssive, and the video scalar must discard odd number lines when display top field. Alternatively, even numbers are discarded when displaying the bottom field. Set to select the background of primary output channel for scaling and output. Reset to select the primary composite output. Set auxiliary video output to black and white. Reserved This value is used to initialize the vertical DDA. It is useful to fixup scaling of interlace picture for interlace display. The suggested value should be the same as DPC_AUX_VFS except in exceptional cases as determined by TeraLogic. The number of pixels accumulated within the auxiliary video FIFO buffer before the auxiliary video output starts. Valid values for following primary display modes are: 1920x1080I : 565 1280x720P : 721 Reserved
Default 0
RW
DPC_AUX_SRC_INTL
RW
DPC_AUX_SRC_SEL
3 7:4 15:8
RW R RW
DPC_AUX_BWMODE Reserved DPC_AUX_VDDA_PH
27:16
RW
DPC_AUX_FIFO_TH
31:28
July 1999 Rev.2.0
143
DPC Auxiliary Display Position Register (DPC_AUX_POS_REG) Address: 0x100C4

31 Reserved 15 Reserved 12 11 DPC_AUX_XPOS 27 26 DPC_AUX_YPOS 0 16
Bits 11:0
Mode RW
Field Name DPC_AUX_XPOS
Description Starting x position within the primary video display for auxiliary video scalar. The maximum value of the field is equal to: disp_width - max( (256*704/DPC_AUX_HFS), 704) Reserved Starting y position within the primary video display for auxiliary video scalar. Reserved
Default
15:12 26:16 31:27 RW
Reserved DPC_AUX_YPOS
144
July 1999 Rev.2.0
DPC Auxiliary Display Horizontal Size Control Register (DPC_AUX_HS_CTL_REG) Address: 0x100C8
31 DPC_AUX_HFM 15 DPC_AUX_HFN 8 7 DPC_AUX_HFS 20 19 DPC_AUX_HFN 0 16
Bits 7:0
Mode RW
Field Name DPC_AUX_HFS
Description Horizontal filter fractional step size between input and output samples. All zero indicates the value of 1.0, and this value indicates a step of one output pixel. Horizontal DDA parameter: HFN is positive. Horizontal DDA parameter: HFM is 2s complement.
Default
19:8 31:20
RW RW
DPC_AUX_HFN DPC_AUX_HFM
July 1999 Rev.2.0
145
DPC Auxiliary Display Vertical Size Control Register (DPC_AUX_VS_CTL_REG) Address: 0x100CC
31 DPC_AUX_VFM 15 DPC_AUX_VFN 8 7 DPC_AUX_VFS 20 19 DPC_AUX_VFN 0 16
Bits 7:0
Mode RW
Field Name DPC_AUX_VFS
Description Vertical filter fractional step size between input and output samples. All zero indicates the value of 1.0, and this value indicates a step of one output pixel. Vertical DDA parameter: VFN is positive. Vertical DDA parameter: VFM is 2s complement.
Default
19:8 31:20
RW RW
DPC_AUX_VFN DPC_AUX_VFM
146
July 1999 Rev.2.0
DPC Auxiliary Display Programmable 1 Timing Register (DPC_AUX_PROG1_REG) Address: 0x100D0

31 23 22 DPC_ AUX_ PROG_ FLG 10 DPC_AUX_HCNT_H0 21 20 19 16
Reserved
DPC_AUX_HCNT_H1
15 DPC_AUX_HCNT_H1
11
Bits 10:0
Mode RW
Field Name DPC_AUX_HCNT_H0
Description The DPC_AUX_HCNT_H0 (2*n1) is used internally to determine when to set the CCIR601 H signal to 0 where n is the number of pixels between the start of a digital video line (EAV) and the falling edge of the CCIR601 H signal. The DPC_AUX_HCNT_H1 (2*m) is used internally to determine when to set the CCIR601 H signal to 1 where m is the number of pixels per digital video line. When this bit is set, the programmable video timing register is used in the AUX unit. Otherwise, the built-in default values are used. Reserved
Default
21:11
RW
DPC_AUX_HCNT_H1
22
RW
DPC_AUX_PROG_FLG
31:23
July 1999 Rev.2.0
147

31 30 29 DPC_AUX_VDNT_V1_F 10 DPC_AUX_VDNT_V0_F 9 DPC_AUX_VCNT_MAX 20 19 DPC_AUX_VDNT_V0_F 0 16
Reserved 15
Bits 9:0 19:10 29:20 31:30
Mode RW RW RW
Field Name DPC_AUX_VCNT_MAX DPC_AUX_VCNT_V0_ F DPC_AUX_VCNT_V1_ F
Description The number of lines per frame. The line number where the CCIR601 V signal is reset to 0 in the first field. The line number where the CCIR601 V signal is set to 1 in the first field. Reserved
Default
148
July 1999 Rev.2.0

31 30 29 DPC_AUX_VDNT_V1_S 10 DPC_AUX_VDNT_V0_S 9 DPC_AUX_VCNT_F1 20 19 DPC_AUX_VDNT_V0_S 0 16
Reserved 15
Bits 9:0 19:10 29:20 31:30
Mode RW RW RW
Field Name DPC_AUX_VCNT_F1 DPC_AUX_VCNT_V0_ S DPC_AUX_VCNT_V1_ S
Description The line number where the CCIR601 F signal is set to 1. The line number where the CCIR601 V signal is reset to 0 in the second field. The line number where the CCIR601 V signal is set to 1 in the second field. Reserved
Default
July 1999 Rev.2.0
149
DPC Cursor Start Address Register (DPC_CURS_SA_REG) Address: 0x10100

31 Reserved 15 DPC_CURS_SA 26 25 DPC_CURS_SA 4 3 Reserved 0 16
Bits 3:0 25:4 31:26
Mode
Field Name
Default
RW
DPC_CURS_SA
Cursor starting word address in dynamic memory. This address must be on the 2 word boundary. Reserved
0x00000000
150
July 1999 Rev.2.0
DPC Cursor Position Register (DPC_CURS_POS_REG) Address: 0x10104

31 Reserved 15 Reserved 11 10 DPC_CURS_XPOS 27 26 25 DPC_CURS_YPOS 0 16
Bits 10:0 15:11 26:16 31:27
Mode RW
Field Name DPC_CURS_XPOS Reserved
Description X pixel position of cursor between 0 to 1023 relative to SAV. Reserved Y line postion of cursor between 0 to 1023 Reserved
Default
RW
DPC_CURS_YPOS Reserved
July 1999 Rev.2.0
151
DPC CUrsor Offset Register (DPC_CURS_OFFSET_REG) Address: 0x10108

31 Reserved 26 25 24 23 DPC_CURS_YOFFSET 16
DPC_CURS_ VSCALE 10 9 8 7
15 Reserved
0 DPC_CURS_XOFFSET
DPC_CURS_ HSCALE
Bits 7:0 9:8
Mode RW RW
Field Name DPC_CURS_XOFFSET DPC_CURS_HSCALE
Description X pixel offset of cursor from 0 upto 255. Horizontal scaling factor: 01=> scaled by 1 10=> scaled by 2 11=> scaled by 3 00=> scaled by 4 Reserved Y line offset of cursor from 0 upto 255. Vertical scaling factor: 01=> scaled by 1 10=> scaled by 2 11=> scaled by 3 00=> scaled by 4 Reserved
Default
01
15:10 23:16 25:24 RW RW
Reserved DPC_CURS_YOFFSET DPC_CURS_VSCALE
01
31:26
152
July 1999 Rev.2.0
DPC Cursor Color Look UP Table (DPC_CURSCLUTn_REG; n = 0 to 15) Address: 0x101400x1017C

31 DPC_CURSCLUT_REG 15 DPC_CURSCLUT_REG 0 16
Bits 31:0
Mode RW
Field Name DPC_CURSCLUT_REG
Description Display processors cursor color look up table. Each entry consists of alpha, Y, Cb and Cr. The 4-bit per cursor pixel is used to index into this register.
Default
July 1999 Rev.2.0
153
DPC Memory Address Register (DPC_MEM_ADDR_REG) Address: 0x10180

31 Reserved 15 Reserved
+
16
10
9 DPC_MEM_ADDR
Bits 9:0 31:10
Mode RW
Field Name DPC_MEM_ADDR
Description The address pointer for next memory access. Reserved
Default
154
July 1999 Rev.2.0
DPC Memory Data Register (DPC_MEM_DATA_REG) Address: 0x10184

Bits (deci) 31:0
Mode RW*
Control Register Name DPC_MEM_DATA
Description A read access returns the content of location pointed to by DPC_MEM_ADDR. A write access causes the content of memory pointed by DPC_MEM_ADDR to be updated. Either read or write access will caused the DPC_MEM_ADDR to be incremented automatically. 0x000-0x0ff: 256 CLUT locations of Alpha, RGB. Note that host CLUT access are disallowed during a scan line where index mode is active. Not Shadowed 0x100: 4-entry index remapping table from i2 to i8. 0x104-0x107: 16-entry index remapping table from i4 to i8. (0x100, 0x104 - 0x107 are big Endian and Not Shadowed) The horizontal filter coeffient data is a 32-bit quantity containing 4 8-bit values. Each value corresponds to a filter coefficient with 7 fractional bit. The leading bit is interpreted either as a sign bit or as an integer bit. The mapping of coefficients starts from the LSB of the word as follows: 0x200: (luma outside tap) phase 0 to phase 3. (signed) 0x201: (luma outside tap) phase 4 to phase 7. (signed) 0x202: (luma inside tap) phase 0 to phase 3. (unsigned) 0x203: (luma inside tap) phase 4 to phase 7. (unsigned) 0x204: (chroma outside tap) phase 0 to phase 3. (signed) 0x205: (chroma outside tap) phase 4 to phase 7. (signed) 0x206: (chroma inside tap) phase 0 to phase 3. (unsigned) 0x207: (chroma inside tap) phase 4 to phase 7. (unsigned) (continued on the next page.
July 1999 Rev.2.0
155
Bits (deci) 31:0
Mode RW*
Description (continued from previous page) Coefficients are used as follows Phase : tap (increasing pixel value from left to right) 0 : Out7 In7 In0 Out0 1 : Out6 In6 In1 Out1 2 : Out5 In5 In2 Out2 3 : Out4 In4 In3 Out3 4 : Out3 In3 In4 Out4 5 : Out2 In2 In5 Out5 6 : Out1 In1 In6 Out6 7 : Out0 In0 In7 Out7 The vertical filter coeffient data is a 32-bit quantity containing 4 8-bit values. Each value corresponds to a filter coefficient with 7 fractional bit. The leading bit is interpreted either as a sign bit or as an integer bit. The memory map of the coefficient is mapped starting from the LSB of the word as follows: 0x210: (luma outside tap) phase 0 to phase 3. (signed) 0x211: (luma outside tap) phase 4 to phase 7. (signed) 0x212: (luma inside tap) phase 0 to phase 3. (unsigned) 0x213: (luma inside tap) phase 4 to phase 7. (unsigned) 0x214: (chroma outside tap) phase 0 to phase 3. (signed) 0x215: (chroma outside tap) phase 4 to phase 7. (signed) 0x216: (chroma inside tap) phase 0 to phase 3. (unsigned) 0x217: (chroma inside tap) phase 4 to phase 7. (unsigned) Coefficients are used as follows for the 3-tap case. Phase : tap (increasing pixel value from left to right) 0 : Out7 In0 Out0 1 : Out6 In1 Out1 2 : Out5 In2 Out2 (continue to the next page)
156
July 1999 Rev.2.0
Bits (deci) 31:0
Mode RW*
Description (continued from the previous page) 3 : Out4 In3 Out3 4 : Out3 In4 Out4 5 : Out2 In5 Out5 6 : Out1 In6 Out6 7 : Out0 In7 Out7 Coefficients are used as follows for the 2-tap case. Phase : tap (increasing pixel value from left to right) 0 : In0 Out0 1 : In1 Out1 2 : In2 Out2 3 : In3 Out3 4 : In4 Out4 5 : In5 Out5 6 : In6 Out6 7 : In7 Out7 The color space converter coefficient data is stored in 6 registers as follows: 0x300 [26:16]: dpc_csc_coeff11
mal signed 2 bit integer, 8 bit deci-
0x300 [10:0]: dpc_csc_coeff12 signed 2 bit integer, 8 bit decimal 0x301 [26:16]: dpc_csc_coeff13 signed 2 bit integer, 8 bit decimal
0x301 [15:8]: dpc_csc_unbias1 8 bit unsigned 0x301 [7:0]: dpc_csc_bias1 8 bit unsigned 0x302 [26:16]: dpc_csc_coeff21
mal signed 2 bit integer, 8 bit deci-
0x303 [15:8]: dpc_csc_unbias2 8 bit unsigned 0x303 [7:0]: dpc_csc_bias2 8 bit unsigned 0x304 [26:16]: dpc_csc_coeff31bit
decimal signed 2 bit integer, 8 bit
0x305 [15:8]: dpc_csc_unbias3 8 bit unsigned 0x305 [7:0]: dpc_csc_bias3 8 bit unsigned
11 12 13 Y/G CB/B = 21 22 23 CR/R 31 32 33
B1 Y - U1 CB - U2 + B2 B3 CR - U3
July 1999 Rev.2.0
157
DPC GPIO Enable Register (DPC_GPIO_EN_REG) Address: 0x10190

31 Reserved 15 GPIO_BLU 28 27 DDC1 26 25 24 23 GPIO_GRN 7 GPIO_RED 0 16
DDC0 VSYNC HSYNC 8
Bits 7:0 15:8 23:16 24 25 26 27 31:28
Mode RW RW RW RW RW RW RW
Field Name GPIO_RED GPIO_BLU GPIO_GRN HSYNC VSYNC DDC0 DDC1
Description Set to enable selected pins as GPIO pins. bit[7:0] : gpio_red[7:0] Not Shadowed GPIO Blue [7:0] GPIO green [7:0] HSYNC VSYNC DDC0 when disabled pin outputs low. DDC1 when disabled pin ouputs high. Reserved
Default 0x0000 000
158
July 1999 Rev.2.0
DPC GPIO Output Enable Register (DPC_GPIO_OUT_EN_REG) Address: 0x10194

DDC0 VSYNC HSYNC 8
Bits 7:0
Mode RW
Field Name GPIO_RED
Description Set pins selected by DPC_GPIO_EN register to output mode. The pins threestate control is enabled. bit[7:0] : gpio_red[7:0] ) Not Shadowed GPIO Blue [7:0] GPIO green [7:0] HSYNC VSYNC DDC0 when disabled pin outputs low. DDC1 when disabled pin ouputs high. Reserved
Default 0x0000 000
15:8 23:16 24 25 26 27 31:28
RW RW RW RW RW RW
GPIO_BLU GPIO_GRN HSYNC VSYNC DDC0 DDC1
July 1999 Rev.2.0
159
DPC GPIO Output Data Register (DPC_GPIO_OUTDATA_REG) Address: 0x10198

DDC0 VSYNC HSYNC 8
Bits 7:0 15:8 23:16 24 25 26 27 31:28
Mode RW RW RW RW RW RW RW
Field Name GPIO_RED GPIO_BLU GPIO_GRN HSYNC VSYNC DDC0 DDC1
Description Set pins selected by DPC_GPIO_EN register to bit value. bit[7:0] : gpio_red[7:0]. Not Shadowed GPIO Blue [7:0] GPIO green [7:0] HSYNC VSYNC DDC0 when disabled pin outputs low. DDC1 when disabled pin ouputs high. Reserved
Default 0x8000 0000
160
July 1999 Rev.2.0
DPC GPIO Input Data Register (DPC_GPIO_INDATA_REG) Address: 0x1019C

DDC0 VSYNC HSYNC 8
Bits 7:0
Mode RW
Field Name GPIO_RED
Description Read values of 28 pins. All 28 pins are being sampled at all times. Note that due to uncertainty in the synchronization, values between 28 pins are not guaranteed to be synchronized with each other. bit[7:0] : gpio_red[7:0] GPIO Blue [7:0] GPIO green [7:0] HSYNC VSYNC DDC0 when disabled pin outputs low. DDC1 when disabled pin ouputs high. Reserved
Default
15:8 23:16 24 25 26 27 31:28
RW RW RW RW RW RW
GPIO_BLU GPIO_GRN HSYNC VSYNC DDC0 DDC1
July 1999 Rev.2.0
161
DPC Sync Pulse Generator Configuration 1 Register (DPC_SPG_CONFIG1_REG) Address: 0x101A0

31 Reserved 15 DPC_SPG_HSTART0 28 27 DPC_SPG_HSTART1 4 3 Res 2 1 0 DPC_ SPG_EN 16
DPC_ DPC_ SPG_TRI SPG_ -LEVEL 4801
Bits 0
Mode RW
Field Name DPC_SPG_EN
Description Set to enable the sync pulse generator. The control pulses are fed to the HSYNC and VSYNC pin in place of regular HSYNC and VSYNC. Set to for the 480I case. Differences are shorter equalization pulse outside of the serration period. Also pclk handling is adjusted. Set to enable the generation of tri-level sync pulses as required by EIA770.3 Reserved. Set the starting position of the first half line. Set the starting position of the second half line. Reserved
Default 0
RW
DPC_SPG_480I
2 3 15:4 27:16 31:28
RW R RW RW
DPC_SPG_TRILEVEL Reserved DPC_SPG_HSTART0 DPC_SPG_HSTART1
162
July 1999 Rev.2.0
DPC Sync Pulse Generator Configuration 2Register (DPC_SPG_CONFIG2_REG) Address: 0x101A4

31 30 29 DPC_SPG_BROADCNT 24 23 DPC_SPG-HSYNTRIG 20 19 Reserved 17 16 DPC_ SPG_ HPSCALE 0 DPC_SPG_H
Reserved
15 DPC_SPG_HPSCALE
12
11
Bits 11:0 16:12 19:17 23:20 29:24 31:30
Mode RW RW R RW RW
Field Name DPC_SPG_H DPC_SPG_HPSCALE Reserved DPC_SPG_HSYNTRIG DPC_SPG_ BROADCNT
Description The number of pixel sample in H. An H is half a line in interlace display. An H is a full line in progressive display. The scale factor used in specifying following horizontal parameters of sync pulse generator. Reserved. The scaled count from beginning of an H period to start of HSYNC. The scaled count of number of pixels within an H, but outside of a broad pulse. Reserved
Default
July 1999 Rev.2.0
163
DPC Sync Pulse Generator Configuration 3 Register (DPC_SPG_CONFIG3_REG) Address: 0x101A8

31 Reserved 15 DPC_SPG_VSTART0 12 11 DPC_SPG_VMAXCNT 27 26 DPC_SPG-VSTART1 0 16
Bits 11:0 15:12
Mode RW RW
Field Name DPC_SPG_VMAXCNT DPC_SPG_VSTART0
Description The maximum number of H within a frame. The start line of vertical sync structure. For an interlace display, this register specify the starting position of the first field. The start line of vertical sync structure for the second field of an interlace display. Reserved
Default
26:16 31:27
RW
DPC_SPG_VSTART1
164
July 1999 Rev.2.0
DPC_SPG_PCONFIG_REG Address: 0x101AC

31 DPC_SPG_S1_END 15 DPC_SPG_VEQCNT 11 28 27 24 DPC_SPG_S1_START 10 8 7 Res 23 DPC_SPG_S0_END 6 4 3 Res 20 19 DPC_SPG_S0_START 2 0 16
DPC_SPG_HIP_WD
DPC_SPG_LOP_WD
DPC_SPG_EQP_WD
Bits 2:0 3 6:4 7 10:8 15:11 19:16 23:20 27:24 31:28
Mode RW
Field Name DPC_SPG_EQP_WD Reserved
Description The width of equalization pulse used for the 480I case. Reserved The width of low sync pulse used in a horizontal sync. Reserved The width of high sync pulse used in a vertical sync. The number of H periods in a vertical synchronization. The starting H period of the field 0 serration. The ending H period of the field 0 serration. The starting H period of the field 1 serration. The ending H period of the field 1 serration.
Default
RW
DPC_SPG_LOP_WD Res
RW RW RW RW RW RW
DPC_SPG_HIP_WD DPC_SPG_VEQCNT DPC_SPG_S0_START DPC_SPG_S0_END DPC_SPG_S1_START DPC_SPG_S1_END
July 1999 Rev.2.0
165
9.0
TSD REGISTERS
The following subsections describe the TSD Configuration registers. Table 9.10: TSD Register Map
Register Name TSD Registers (Base Address : 0x20000)

TSD DMA Read and TSD DMA Configuration Register (TSD_DMA_RD_CONFIG_REG) TSD DMA Write Address High/Low Register (TSD_DMA_WR_ADD_REG) TSD Byte Stop and Byte Limit Register (TSD_IO_BYTELIM_CNT_REG) STC Counter Low and Middle Register (TSD_STC_CNT_LM_REG) STC Counter High Register (TSD_STC_CNT_H_REG) TSD IO Configuration and VCXO Register (TSD_CON_VCXO_REG) TSD Interrupt Status Register (TSD_INT_STATUS_REG) TSD IO Status Register (TSD_IO_STATUS_REG) TSD MPEG and Byte Count Register (TSD_MPEG_BYTECNT_REG)
0x27000 0x27004 0x27800 0x27804 0x27808 0x27810 0x27814 0x27820 0x27824
page 167 page 168 page 169 page 170 page 171 page 172 page 173 page 174 page 175
166
July 1999 Rev.2.0
TSD DMA Read and TSD DMA Configuration Register (TSD_DMA_RD_CONFIG_REG) Address: 0x27000
31 TSD_DMA_RD_ADD Host 16
15
14
13
12 res
8 TSD_ DMA_ VALID
7 TSD_DMA_LENGTH
TSD_ TSD_ TSD_ DAM_ DAM_ DMA_ DONE1 DONE2 DONE3
Bits 7:0 8 12:9 13
Mode R R R R
Field Name TSD_DMA_LENGTH TSD_DMA_VALID Reserved TSD_DMA_DONE3
Description This the byte length of the DMA transaction. This is the valid indicator for the DMA channel. Reserved. These bits must be written as 0s. This is mapped to R15[0]. The TSD has sent the memory request to the MIF. The MCU now can update the DMA for the next transaction, which can take place 20 cycles after DONE2. Note that it might be 100 cycles before the data is retired to memory. This is mapped to R15[1]. Data for this DMA has transferred to the MIF buffer 10 cycles after DONE1. This is mapped to R15[2]. Data for this DMA is read out of the data RAM. Worst case after start of DMA is >100 cycles. This is the read address of the data RAM.
Default
14
TSD_DMA_DONE2
15
TSD_DMA_DONE1
31:16
TSD_DMA_RD_ADD
July 1999 Rev.2.0
167
TSD DMA Write Address High/Low Register (TSD_DMA_WR_ADD_REG) Address: 0x27004

31 res 15 TSD_DMA_WR_ADDL Host 26 25 TSD_DMA_WR_ADDH Host 0 16
Host Bits 15:0 25:16 31:26
Mode RW R R
Field Name TSD_DMA_WR_ADDL TSD_DMA_WR_ADDH Reserved
Description This is the lower write address memory. This is the upper write address memory. These bits are reserved and set to 0.
168
July 1999 Rev.2.0
TSD Byte Stop and Byte Limit Register (TSD_IO_BYTELIM_CNT_REG) Address: 0x27800
31 TSD_BYTESTOP_COUNTER Host 16
15 TSD_BYTE_LIMIT_COUNTER Host
Host Bits 15:0 31:16
Mode R R
Field Name TSD_BYTE_LIMIT_COU NTER TSD_BYTESTOP_COUN TER
Description This byte counter wraps around after reaching its limit. When byte counter reaches this, the PCI incoming MPEG stream stops.
Default 16h02 00
July 1999 Rev.2.0
169
STC Counter Low and Middle Register (TSD_STC_CNT_LM_REG) Address: 0x27804

31 STC_COUNTER_M Host 15 STC_COUNTER_L Host 0 16
Bits 15:0 31:16
Mode R R
Field Name STC_COUNTER_L STC_COUNTER_M
Description These are the low 16 bits of the 48 bit STC counter. The MCU must read this first. Middle 16 bit of the 48 bit STC counter. The MCU must read this after STC_COUNTER_L.
Default
170
July 1999 Rev.2.0
STC Counter High Register (TSD_STC_CNT_H_REG) Address: 0x27808

31 Reservedt 15 STC_COUNTER_H Host 0 16
Bits 15:0 31:16
Mode R -
Field Name STC_COUNTER_H RESERVED
Description These are the upper 16 bits of the STC counter. The MCU must read this last. Reserved
Default
July 1999 Rev.2.0
171
TSD IO Configuration and VCXO Register (TSD_CON_VCXO_REG) Address: 0x27810

31 30 29 28 27 26 25 TSD_DRAM_OFFSET 16
TSD_ TSD_ TSD_ TSD_ TSC_ TSD_ DRAM_ XPROT_ON EXTSYNC SOURCE CIE ENDIAN FULL
15 PWM VALUE Host
Bits 15:0 25:16 26
Mode RW R R
Field Name PWM_VALUE TSD_DRAM_OFFSET TSD_DRAM_FULL
Description These bits control the PWM output. Offset address in 16 bit word to the data RAM for incoming stream. 1 means MCU could not process the data fast enough, need to stop PCI bus. MPEG stream will not write into data RAM after two cycles once it is set. PCI data Endian. 0 big Endian, 1 small Endian. This is the collision interrupt enable bit. Source of MPEG stream, 1 from PCI, 0 from 8 bit xport. Use the cframe external synchronization. 1 means turning on the transport dmux, 0 is off.
Default
10h020
27 28 29 30 31
R R R R R
TSD_ENDIAN TSD_CIE TSD_SOURCE TSD_EXTSYNC TSD_XPORT_ON
172
July 1999 Rev.2.0
TSD Interrupt Status Register (TSD_INT_STATUS_REG) Address: 0x27814

31 Reserved 15 TSD_BYTE_COUNTER Host 0 16
Bits 15:0
Mode R/ Clear
Field Name TSD_INT_STATUS
Description These are the interrupt status bits. Any set bit sends an interrupt to host. The bit is cleared when the host is read. MCU writing to it is ORed with the old value. Reserved
Default
31:16
RESERVED
July 1999 Rev.2.0
173
TSD IO Status Register (TSD_IO_STATUS_REG) Address: 0x27820

31 Reserved 15 Reserved 3 2 TSD_ COLLISION 1 TSD_ STOP 0 TSD_ EXTSYNC_DONE 16
Bits 0 1
Mode R R
Field Name TSD_EXTSYNC_DONE TSD_STOP
Description Used cframe once. This must be cleared by the MCU. This bit is set when the byte counter reaches TSD_BYTESTOP. It must be cleared by the MCU to accept new PCI data. This bit is set when a collision or overflow in the input data RAM occurs; it must be cleared by the MCU for a new detection. Reserved
Default
TSD_COLLISION
31:3
174
July 1999 Rev.2.0
TSD MPEG and Byte Count Register (TSD_MPEG_BYTECNT_REG) Address: 0x27824

31 TSD_MPEG_DATA Hos 15 TSD_BYTE_COUNTER Host 0 16
Bits 15:0
Mode RW
Field Name TSD_BYTE_COUNTER
Description This is the input stream byte counter. This counter and the TSD_DRAM_OFFSET form the address to the data RAM. These are 16 bits of the input MPEG stream data.
Default
31:16
TSD_MPEG_DATA
July 1999 Rev.2.0
175
10.0
MIF REGISTERS
Table 10.11: MIF Register Map Register Map MIF Registers (Base Address : 0x28000)
MIF Configuration Register (MIF_CONFIG_REG) Macroscheduler Internal State Select (MIF_MAC_STATE_REG) MIF Field Buffer #n (MIF_FLD_DSCR_n_REG; n = 0 to 15) MIF Status for Client #n (MIF_STATUS_REG) 0x28000 0x2803C 0x280400x2807C 0x280800x280DC page 177 page 179 page 181 page 183 Base + Offset Address Page #
176
July 1999 Rev.2.0
MIF Configuration Register (MIF_CONFIG_REG) Address: 0x28000 This register specifies the basic memory configuration parameters. Default value is 0x34303140.
31 mif_refresh_period 15 res 14 12 11 res 9 8 mif_num_ bank 7 res 24 23 res 6 mif_rank_size 22 21 20 19 res 3 res 2 mif_num_ rank 18 mif_num_col 1 res 0 mif_mem_ width 16 mif_tras 4
mif_bank_select
Bits 0
Mode RW
Field Name mif_mem_width
Description Memory width. 0: 64 bits 1: 32 bits
Default 0
1 2 RW
Reserved mif_num_rank Number of ranks of SDRAM chips. 0: 1 rank 1: 2 ranks 0
3 6:4 RW
Reserved mif_rank_size If the memory has 2 ranks of SDRAM chips, this field specifies the size of each rank. 000: 2MB 001: 4MB 010: 8MB 011: 16MB 100: 32MB Number of internal banks supported by the SDRAM chips. 0: 2 internal banks per chip 1: 4 internal banks per chip 100
RW
mif_num_bank
11:9 14:12 RW
Reserved mif_bank_select Which memory address pin of the TL850 is connected to BS0 of the SDRAM. 000: MA[9] 001: MA[10] 010: MA[11] 011: MA[12] 100: MA[13] 011
15 18:16 RW
Reserved mif_num_col Number of column bits. 000: 8 column bits (MA[0] - MA[7]) 001: 9 column bits (MA[0] - MA[8]) 010: 10 column bits (MA[0] - MA[9]) 011: 11 column bits (MA[0] - MA[10]) 100: 12 column bits (MA[0] - MA[11]) 000
19
Reserved
July 1999 Rev.2.0
177
Bits 21:20
Mode RW
Field Name mif_tras
Description Minimum bank active time (Tras). The minimum number of cycles from a row activate (RAS) to a precharge (of the same bank). Note that Trc (bank cycle time, the minimum time from row activate to row activate) is assumed to be Tras + 3. 00: 4 cycles 01: 5 cycles 10: 6 cycles 11: 7 cycles
Default 11
23:22 31:24 RW
Reserved mif_refresh_period Refresh Period. This field specifies the refresh period, where a single CAS before RAS refresh is performed every N cycles (using the internal 108MHz clock). The average time between refresh commands is: 32 * mif_refresh_period cycles. The default value for this field is 52 (0x34) = [(0.064 sec) * (108 x 106) / (4096 + 15)] / 32.
178
July 1999 Rev.2.0
10.1
MACROSCHEDULER INTERNAL STATE SELECT

The macroscheduler pacing control (bits 0 to 20) controls how often the macroscheduler produces a new schedule. The internal state bits (bits 28 to 30) specifies which internal state values will be asserted on the SDRAM address lines whenever the address lines are not being used to send real addresses. The 3 bits of this register selects one of the seven state machines inside the macroscheduler. 3'b000: {state_cnt, 3'b0, main_state} 3'b010: {state_cnt, 2'b0, write_state} 3'b011: {state_cnt, read_state}
3'b100: {state_cnt, 4'b0, a_improve_state} 3'b101: {state_cnt, 2'b0, a_other_state} 3'b110: {state_cnt, 4'b0, b_improve_state} 3'b111: {state_cnt, 2'b0, b_other_state}
Macroscheduler Internal State Select (MIF_MAC_STATE_REG) Address: 0x2803C

31 res 15 mac_num_access_starti[ 30 28 27 res 8 7 mac_num_access_limit 21 20 mac_sclk_domain_faster 19 mac_decr_correction 0 16
MAC_State_Select
Bits 7:0 15:8 19:16 20 27:21 30:28 31
Mode RW RW RW RW
Field Name mac_num_access_limit mac_num_access_start up mac_decr_correction mack_sclk_domain_ faster res
Description Threshold for starting new schedule. Increasing the value will cause schedules to be started sooner. Value to add into access count when starting a schedule after a period of no memory accesses (idle memory) (see table) (see table) Reserved
Default 38 (0x26) 14 (0x0e) 8 1
RW
mac_state_select res Reserved
Table 1: Recommended Values

sclk frequency/ clk frequency 2.00 to 1.42 1.42 to 1.29 mac_sclk_do main_faster 1 1 mac_decr_ correction 1 2
July 1999 Rev.2.0
179
Table 1: Recommended Values (cont.)

sclk frequency/ clk frequency 1.29 to 1.22 1.22 to 1.19 1.19 to 1.16 1.16 to 1.13 1.13 to 1.10 1.10 to 1.07 1.07 to 1.04 1.04 to 0.96 0.96 to 0.93 0.93 to 0.90 0.90 to 0.87 0.87 to 0.84 0.84 to 0.81 0.81 to 0.77 0.77 to 0.71 0.71 to 0.58 0.58 to 0.50 mac_sclk_do main_faster 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 mac_decr_ correction 3 4 5 6 8 11 15 0 15 11 8 6 5 4 3 2 1
180
July 1999 Rev.2.0
10.2
MIF FIELD BUFFER #N

This register specifies the location, size, and modes of a MPEG field buffer. Note that field buffers 14 and 15 are not defined for MCE writes (MCWR). A reference to field buffer 14 or 15 instructs the MIF to ignore the MCWR memory access. For all other clients, field buffer 14 or 15 are valid accesses.
31 res 15
30 fld_base_addr 14 13 fld_width 8 7 fld_format 6 fld_height
16
fld_amr_mode
MIF Field Buffer #n (MIF_FLD_DSCR_n_REG; n = 0 to 15) Address: 0x280400x2807C

Address 0x28040 0x28044 0x28048 0x2804C 0x28050 0x28054 0x28058 0x2805C 0x28060 0x28064 0x28068 0x2806C 0x28070 0x28074 0x28078 0x2807C Register Mnemonic MIF_FLD_BUF_0 MIF_FLD_BUF_1 MIF_FLD_BUF_2 MIF_FLD_BUF_3 MIF_FLD_BUF_4 MIF_FLD_BUF_5 MIF_FLD_BUF_6 MIF_FLD_BUF_7 MIF_FLD_BUF_8 MIF_FLD_BUF_9 MIF_FLD_BUF_10 MIF_FLD_BUF_11 MIF_FLD_BUF_12 MIF_FLD_BUF_13 MIF_FLD_BUF_14 MIF_FLD_BUF_15 MIF Field Buffer # 0 MIF Field Buffer # 1 MIF Field Buffer # 2 MIF Field Buffer # 3 MIF Field Buffer # 4 MIF Field Buffer # 5 MIF Field Buffer # 6 MIF Field Buffer # 7 MIF Field Buffer # 8 MIF Field Buffer # 9 MIF Field Buffer # 10 MIF Field Buffer # 11 MIF Field Buffer # 12 MIF Field Buffer # 13 MIF Field Buffer # 14 MIF Field Buffer # 15 Register Name
July 1999 Rev.2.0
181
Bits 6:0
Mode RW
Field Name fld_height
Description Field buffer height in multiples of 32 lines, counting both luma and chroma lines. This field is used to wrap the physcial y (using a modulo operation), so that buffers can contain less than a full field. The actual physical y used is (yp mod 32*fld_height). Allowed values of fld_height are 1 through 16. All other values (including zero) indicate that no modulo operation should be done. The default value of this field is 0. Chroma format. 0: 4:2:0 1: 4:2:2 Field buffer width in multiples of 16 words. The default value of this field is 15 (0x0f) which corresponds to 1920 pels. The value of 0 is not allowed and is reserved. Memory reduction mode. 00: AMR off 01: 2-to-1 compression 10: 4-to-1 compression 11: reserved The base (initial) address of the field buffer in multiples of 2048 bytes. The byte address in physical memory at which the field buffer starts is (2048 * fld_base_addr). The default value for this field is 0.
Default 0
RW
fld_format
13:8
RW
fld_width
0x0f
15:14
RW
fld_amr_mode
00
30:16
RW
fld_base_addr
31
Reserved
182
July 1999 Rev.2.0
10.3
MIF STATUS FOR CLIENT #N

This register specifies the status of the memory operations for a given client. As status information, this register is read-only. Software can use this register to determine if a client has active memory operations. If the hexadecimal value of 0x31415926 is written to this register, then the MIF is reset for this client. A reset causes all pending operations to be ignored (writes to the MIF buffer or to SDRAM are disabled). A reset also resynchronizes the internal bus for this client..
31 res 15 status_buf_cnt 12 11 status_desc_cnt 8 7 6 5 4 3 res 2 1
16
status_ status_ status_ status_ ready3 ready2 ready1 ready0
status_ status_ mac_busy mreq
MIF Status for Client #n (MIF_STATUS_REG) Address: 0x280800x280DC

Address 0x28080 0x28084 0x28088 0x2808C 0x28090 0x28094 0x28098 0x2809C 0x280A0 0x280A4 0x280A8 0x280AC 0x280B0 0x280B4 0x280B8 0x280BC 0x280C0 0x280C4 0x280C8 0x280CC 0x280D0 Register Mnemonic MIF_STATUS_HIF_RD MIF_STATUS_APU_RD MIF_STATUS_TOC MIF_STATUS_BLT0_RD MIF_STATUS_VPIP_RD MIF_STATUS_BVDO1 MIF_STATUS_CLUT MIF_STATUS_MC_RD MIF_STATUS_OVL1 MIF_STATUS_OVL2 MIF_STATUS_BLT1_RD MIF_STATUS_BLT2_RD MIF_STATUS_BVDO2 MIF_STATUS_BVDO3 MIF_STATUS_CURS MIF_STATUS_DL MIF_STATUS_HIF_WR MIF_STATUS_APU_WR MIF_STATUS_TRANS MIF_STATUS_BLT_WR MIF_STATUS_VPIP_WR Satus of HIF read Satus of APU read Satus of MCE top of channel read Satus of BLT channel 0 read Satus of VPIP read Satus of DPC background video 1 read Satus of CLUT read Satus of MCE motion comp read Satus of DPC graphic overlay 1 read Satus of DPC graphic overlay 2 read Satus of BLT channel 1 read Satus of BLT channel 2 read Satus of DPC background video 2 read Satus of DPC background video 3read Satus of DPC cursor read Satus of DPC display list read Satus of HIF write Satus of APU write Satus of transport stream write Satus of BLT write Satus of VPIP write Register Name
July 1999 Rev.2.0
183
Address 0x280D4 0x280D8 0x280DC
Register Mnemonic MIF_STATUS_HPIP MIF_STATUS_VSC MIF_STATUS_MC_WR Satus of HPIP write
Register Name
Satus of video capture write Satus of MCE macroblock write
Bits 0 1 3:2 4 5 6 7 11:8 15:12 31:16
Mode R R
Field Name status_mreq status_busy Reserved
Description Set if this client has is asserting mreq Set if this client has memory operations waiting to be scheduled by the macroscheduler. Reserved Set if buffer 0 is ready Set if buffer 1 is ready Set if buffer 2 is ready Set if buffer 3 is ready Value of counter used to order descriptors (Gray coded -see table below) Value of counter used to order access to the MIF buffer (Gray coded -- see table below) Reserved
Default
R R R R R R
status_ready0 status_ready1 status_ready2 status_ready3 status_desc_cnt status_buf_cnt res
184
July 1999 Rev.2.0
The following table gives the order of counter values and the buffer index for each counter value. Table 10.12: Buffer Index Gray Code Value
Gray Code Value 0000 0001 0011 0111 0110 0100 1100 1110 1111 1011 1001 1000 Buffer Index Buffer Depth = 1 Buffer Depth = 2 Buffer Depth = 3 Buffer Depth = 4
0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 1 0 1 0 1 0 1 0 1
0 1 2 0 1 2 0 1 2 0 1 2
0 1 2 3 0 1 2 3 0 1 2 3
July 1999 Rev.2.0
185
186
July 1999 Rev.2.0

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TL850 Preliminary Register Manual Version 2.0 July, 1999

TERALOGIC CONFIDENTIAL - DO NOT COPY

TERALOGIC CONFIDENTIAL - DO NOT COPY

This material is confidential and is provided under an existing NDA

TL850 Register Manual

July 1999 Rev.2.0

TERALOGIC CONFIDENTIAL - DO NOT COPY

This material is confidential and is provided under an existing NDA

PCI CONFIGURATION REGISTERS

PCI Configuration Registers - HIF

R/W R R R R R R/W R R R/W

Base Address for HIF (Host Interface) Bits [31:20] programmable

TERALOGIC CONFIDENTIAL - DO NOT COPY

July 1999 Rev.2.0

This material is confidential and is provided under an existing NDA

PCI Configuration Registers - HIF (cont.)

31:16 31:0 7:0 31:08 31:0 7:0 15:8 23:16

0x00040 0x00041 0x00042 0x00043 0x00044 0x00047

7:0 15:8 31:16 31:0

July 1999 Rev.2.0

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This material is confidential and is provided under an existing NDA

PCI Configuration Registers - HIF (cont.)

0x0004E 0x0004F 0x00050 0x00053

23:16 31:24 31:0

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HOST BUS REGISTER MAP

Host Bus Register Map

July 1999 Rev.2.0

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Base + Offset Address

HIF Registers (Base Address : 0x00000)

VSC Registers (Base Address : 0x01000)

APU Registers (Base Address : 0x03000)

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July 1999 Rev.2.0

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BLT Registers (Base Address : 0x04000)

July 1999 Rev.2.0

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PLL Registers (Base Address : 0x05000)

DLL Registers (Base Address : 0x05000)

DPC Registers (Base Address : 0x10000)

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July 1999 Rev.2.0

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TERALOGIC CONFIDENTIAL - DO NOT COPY

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TSD Registers (Base Address : 0x20000)

MIF Registers (Base Address : 0x28000)

July 1999 Rev.2.0

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This material is confidential and is provided under an existing NDA