International Journal of Computational Intelligence and Information Security, March 2013, Vol. 4 No.

3, ISSN: 1837-7823

FPGA based Gate and RTL Level Fault Injection Technique and Tool for Fault Tolerance Designs
P Venkata Konda Reddy1, Akhilesh Kumar2, Amrit Anand 3
1 2 3

PG scholar in Department of E&C Engineering, NIT Jamshedpur, Jharkhand, India

Associate Professor in Department of E&C Engineering, NIT Jamshedpur, Jharkhand, India

UG scholar in Department of E&C Engineering, BRCM CET, Bahal, Bhiwani, Haryana, India

Abstract
This paper presents the FPGA based fault injection technique and tool which allows the designers to inject the faults at gate and RTL level, where structural model of a digital system is written in VHDL. The approach utilizes the FPGA devices for emulation of VHDL designs. By using this tool we can observe the system behavior before and after injecting the faults into the fault tolerance designs. The developed tool provides both the features of hardware based and simulation based fault injection features including good graphical user interface. As a case study double ALU based fault tolerance processor was taken and evaluated using Spartan FPGA. Keywords: Fault Injection, s-a-0, s-a-1, SEU, Graphical User Interface, gate Level, RTL Level.

1. Introduction
In last two decades there has been a growing interest in techniques for validating the fault tolerance properties of critical digital systems and evaluation of their reliability. Because of rapid increase in the technology the integration level of electronic systems are increasing, which is making difficulty to generate an acceptable degree reliability as a consequence of the higher chance of faults in the system that can affect the behavior of the system. So fault injection is a valid solution to the problem of dependability validation. There are so many fault injection techniques have been developed and practically experimented. They are grouped into the following types. 1. Simulation based fault injection 2. Physical based fault injection Hardware Based fault injection Software based fault injection In simulation based fault injection a model of the system under test, which can be developed at different abstraction levels, is simulated by altering the logical values of the model elements. Hardware fault injection uses additional hardware to introduce faults into the target systems hardware. Typical hardware based fault injection tools are Messalina [1], FIST [2], MARS [3]. Software fault injection changes the contents of memory or Registers to simulate the occurrence of Hardware or software faults. FERRARI [4], DOCTOR [5], Xception [6]. Hardware fault injection has disadvantages like low probability and actions of target system are not easy to observe and result is difficult to collect. Simulation based fault injection has advantage of high controllability and observability but very high time consuming. One way to provide good controllability and observability including with speed in the fault injection experiments is to use FPGA based fault injection techniques and tools. An effecting FPGA base fault injection tool must support properties as below 1) High controllability and observability.

2) High speed fault injection techniques. 3) Capability of injection of multi- Level fault models.
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2. Modeling approach of Fault Models

Fault modeling is realized by building fault models. The developed tool supports the following synthesizable fault models for injecting into any VHDL designs, which are designed at Gate Level and RTL Level. Permanent faults Transition faults Single event upset faults (or) Bit-flip.

Fault injection process can be done by applying some extra gates and wires to the original design description and modifying the target VHDL model of the system. One of these extra wires is the Fault injection system (FIS) which playing the key role in the fault injection experiments. If a FIS takes the value 1, fault would be activated and if it takes the value 0, the fault would become inactive.

2.1. Permanent faults

For supporting the permanent faults in VHDL design, the developed tool nominates wires for fault injection and applies the FIS signal with one extra gate. So by selecting the FIS signal high at fault injection time, the permanent fault into the specified wire will be injected.

Figure 1: Synthesizable s-a-0 fault model

Figure 2: Synthesizable s-a-1 fault model

Figure 1 and figure 2 show the synthesized model for supporting the permanent faults those are s-a-1 and s-a-0 faults. Our developed tool uses timer for determining the fault injection time and duration time and injection module at the time of fault injection. Once the injection time reached one timer starts counting until the specified time at the time of fault injection.

2.2. Transient faults

For injecting a transient fault, after reaching the fault injection time, the FIS signal will be made high and the timer, which have been loaded with the duration of the transient fault injection start to count. Therefore, the FIS will be high (at logic 1) for the specified duration of time. As similar to the permanent fault, the additional wire (TX) will be used and each wire, namely X will be replaced with TX.

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International Journal of Computational Intelligence and Information Security, March 2013, Vol. 4 No. 3, ISSN: 1837-7823

Figure 3: Synthesizable transient fault model

2.3. Bit-Flip faults

The fault model that is used by the tool at this level is bit-flip (or single event upset). SEUs are the random events and may flip the content of the memory element at unpredictable times. Our tool generates modified circuit for each memory element that is specified for fault injection. The modified circuit for supporting bit flip fault model is shown in below figure 4. For supporting the bit-flip model, tool produces the additional signals such as Bit and FIS with one multiplexer. The inverted input will go to the flip-flop for the next clock when the FIS and bit are 1. The fault injection manager part of tool is responsible for setting and resetting the FIS and bit signals.

Figure 4: Synthesizable Bit-flip fault model

3. Design of fault injection tool

This tool environment consists of three parts (1) Source code modifier and fault list generator. (2) Fault injection manager (3) Results capturing with FPGA emulation Source code modifier and fault list generator are the software parts of the tool. This is implemented with two tools. Eclipse editor C programs to insert faults on a specific port. These are located on host (PC) computer. Separate C scripts are developed for inserting each fault. A GUI facilitates invoking the scripts by mouse right click. Fault injection manger is responsible for performing 24

International Journal of Computational Intelligence and Information Security, March 2013, Vol. 4 No. 3, ISSN: 1837-7823 the real time fault injection. The fault injection manager is implemented in VHDL. The fault injection manager is having VHDL package (dynamically updated by C programs) Fault scheduler Fault insertion components

The VHDL package is implemented to capture all the constants, type definitions, component declarations and fault injection time for each fault. The package also consists of number of total faults. This VHDL file is automatically updated by C programs every time when a fault is injected in code. The fault scheduler runs multiple counters to schedule each fault with required fault activation time and fault propagation time as per the package. The fault scheduler produces output fault number which is currently being active. This module generates the parallel fault injection signals for every fault. These signals are routed to all fault sites. Fault insertion components are gates with FIS (fault injection signal) control to inject the faults when the FIS is active high. These components instances are automatically made whenever faults are injected. Result analysis will be carried out with FPGA emulation results and fault list generated by C program. The analysis shall summarize the fault responses for each injected fault.

4. Fault injection process

The fault injection process for our tool is as shown in the following figure5.

Figure 5: Fault Injection process

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International Journal of Computational Intelligence and Information Security, March 2013, Vol. 4 No. 3, ISSN: 1837-7823

4.1. The setup/fault injection phase

Main objective of this phase is to generate modified VHDL source code of the test design. In this phase the VHDL model is opened through the tool editor and then user should select the signal or port to inject the faults. After selection of type of faults to be injecting and fault injection properties such as fault duration, fault latency, bus size, injection time the tool takes the responsibility to generate modified synthesizable source code in addition with fault injection manager which is responsible for real time fault injection in FPGA board. In the next step the modified source code is synthesized by using synthesis tool which generates the gate level source code which is used to configure the FPGA.

4.2. The emulation phase

In this phase we emulate fault free model and fault model. Main objective of this phase is to capture the information of the performance parameters of the emulated designs. This capture results are sent to the host computer through serial port.

4.3. The evaluation phase

In this phase evaluation of the model is achieved by tracing difference between golden run and faulty trace files. This can be done by the result analyzer. Analyzer is a part of our tool.

5. Case study
Double ALU based fault tolerance processor [8] has been chosen as benchmark to be evaluated by this tool. This is a synthesizable VHDL model. The architecture of processor has been coded by VHDL in 520 lines of code. We chose it because of its high reliability for soft errors. This processor can be used as a typical calculator. A fixed point system is used to implement calculations.

Figure 6: Processor architecture The faults are injected in different parts of the processor as ALU1, ALU2, data registers, and decoder. The trace files contain the data from address bus, data buses and registers. Three different workloads were run on the target system: multiplication, division and square root operations are performed to test processor. 26

International Journal of Computational Intelligence and Information Security, March 2013, Vol. 4 No. 3, ISSN: 1837-7823

5.1. List of faults injected and tested

Table 1: list of fault models and fault targets Type of fault Permanent faults Transient Faults Bit-Flip Faults Fault model Stuck-at-0 Stuck-at-1 Transient Flip-to-0 Flip-to-1 No.of Faults Injected 62 50 10 40 43 Fault target Comp, ALU1,d_reg1 d_reg1, ALU2 Comp,ALU1,d_reg3 d_reg4, ALU2 d_reg2, ALU1

Table 2: Performance results Work Load Division Square Root Observation Points ALU1 d_reg1 ALU1 d_reg1 % of errors in program results 3.5% 2.9% 4.5% 3.2%

The workloads used to run on this processor are division and square root. Table 1 shows the number of faults and types of faults injected in the specified parts of the processor. Table 2 presents the workloads implemented with injected faults in processor. From the output of result analyzer we can say that our processor is more reliable for division than the square root.

6. Simulation and Emulation results

Modelsim Xilinx Edition is Used for simulation of the individual modules and final top level (after inserting the faults) module. Xilinx ISE is used for synthesis, P&R and bit file generation. Xilinx Chipscope is used for capturing the results at FPGA emulation phase.

6.1. Fault_tolerant_processor (without injecting faults)

Figure 7: simulation results of Fault_tolerant_processor (without injecting faults) 27

International Journal of Computational Intelligence and Information Security, March 2013, Vol. 4 No. 3, ISSN: 1837-7823

6.2. Fault_tolerant_processor (After injecting faults)

Figure 8: simulation results of Fault_tolerant_processor (After injecting faults)

7. Synthesis results 7.1. without injecting faults

Figure 9: chip scope pro results without injecting faults into Processor

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International Journal of Computational Intelligence and Information Security, March 2013, Vol. 4 No. 3, ISSN: 1837-7823

7.2. After injecting faults

Figure 10: chip scope pro results with injecting faults into Processor

8. Conclusion
This paper presented a totally new fault injection tool that injects faults based on the synthesizability of the circuit models described by VHDL. It has been shown that how the tool was designed and implemented and how it injects faults into models. Fault injection into VHDL models has been designed at provided abstraction levels and fault models in VHDL. System emulation is achieved by using SPARTAN 3E FPGA. Furthermore system evaluations are done by comparing signal values of faulty circuit with fault free one that gathered during emulation. Finally emulation of two bench marks those are multiplication, division and square root were done. The results show that the effects of faults were more on d_reg1, d_reg2 than the ALU1, ALU2.

9. References
[1] I Arlat, Y Crouzet, and IC Laprie, "Fault Injection for Dependability Validation of Fault-Tolerant Computer Systems," Proc. 19th Ann. Ins Symp. Fault-Tolerant Computing, IEEE CS Press, LosAlamitos,Calif, 1989, pp. 348-355(massaline). Gunnetlo, I Karlsson, and I Tonn, "Evaluation of Error Detection Schemes Using Fault Injection by Heavyion Radiation," Proc. 19th Ann. Int'! Symp.Fault-Tolerant Computing,IEEE CS Press, Los Alamitos, Calif, 1989, pp. 340-347.(FIST) I Karlsson, I Arlat, and G. Leber, "Application of Three Physical Fault Injection Techniques to the Experimental Assessment of the MARS Architecture," Proc. Fifth Ann. IEEE Intel Working Conf.Dependable Computing for Critical Applications, IEEE CS Press, Los Alamitos, Calif, 1995, pp. 150161. G.A. Kanawati, N.A. Kanawati, J.A. Abraham, FERRARI: A Flexible Software-Based Fault and ErrorInjection System, IEEE Trans. on Computers, Vol 44, N. 2, February 1995, pp. 248-260 S. Han, K.G. Shin, and B.A. Rosenberg, "Doctor: An Integrated Software Fault-Injection Environment for Distributed Real-Time Systems," Proc. Second Annual IEEE Intel Computer Performance and Dependability Symp.,IEEE CS Press, Los Alamitos, Calif, pp. 204-213, 1995.(DOCTOR)

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International Journal of Computational Intelligence and Information Security, March 2013, Vol. 4 No. 3, ISSN: 1837-7823 J. Carreira, H. Madeira, and J.G. Silva, "Xception: Software Fault Injection and Monitoring in Processor Functional Units," Proc. Fifth Ann. IEEE Inn Working Conf.Dependable Computing for Critical Applications, IEEE CS Press, Los Alamitos, Calif, pp. 135-149, 1998. [7] E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, J. Karlsson, Fault Injection into VHDL Models: the MEFISTO Tool, Proc. FTCS 24, 1994, pp. 66-75 [8] M. Nikoladis, Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies, IEEE VTS,199, pp. 86-94 [9] Z. segall, D. Vrsalovic, D.Siewiorek,D.Yaskin, J.Kownacki, J. Barton, D . Rancey, A. Robinson, and T.Lin, FIAT fault injection based automated testing environment, in Proc. 18th Int.symp. On Fault tolerant computing(FTCS-18), 1988. [10] L. Antoni, R. Leveugle and B. Feher, Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes, Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002, pp. 245-253. [11] P. Civera, L. Macchiarulo, M. Rebadengo, M. S. Reorda, M. and A. Violante, Exploiting FPGA foraccelerating fault injection experiments, Proc. of the International On-Line Testing Workshop, 2001 pp.9-13. [12] P. Civera, L. Macchiarulo, M. Rebadengo, M. S. Reorda, M. and A. Violante, FPGA-based FaultInjection for Microprocessor Systems, Proc. of the Asian Test Symposium, Nov. 2001, pp. 304-309. [6]

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