Spice to GDS using Mentor Toolset

Simulation of Inverter Netlist in Eldo: 1. Move to the folder $WORK/spice_to_layout/eldo 2. You should find a file with name inv.cir. This is a spice netlist of a basic inverter whose transistor models are taken from the ADK ami05 model file. You will be performing the transient analysis for this inverter. Please open the file have a look at it before simulation. 3. Enter the command: eldo inv.cir -cou 4. Please scroll through the transcript and make sure that there are no errors. 5. Enter the command: ezwave inv.wdb 6. Click on the + mark present next to the inv folder icon. 7. It will open another folder icon named TRAN. Click the + present next to this folder. 8. It will display two waveform icons double click them to see the waveform. 9. Check the inverted output waveform. 10. Press the I key to zoom in, O key to zoom out and A key to view all. 11. Exit the ezwave session. 12. Open the inv.cir file and change the transistor model to nmos and pmos, which is currently n and p. This is because the model definition in the process file is defined nmos and pmos 13. In the terminal move to the folder $WORK/spice_to_layout/layout

Spice to Layout Conversion using ICstation 14. Invoke IC Station by giving the command: ic & 15. Choose the 'Create-Spice' option from the palette. 16. In the 'IC Station Cell' column enter 'inv'. 17. In the 'Spice file' column browse to file

$WORK/spice_to_layout/eldo/inv.cir 18. In the Subckt name enter 'inv' 19. In the Process file name tab browse to file $ADK/technology/ic/process/ami05 20. In the Rules file tab browse to file $ADK/technology/ic/process/ami05.rules 21. Choose OK. 22. Two windows will open. Choose the Menu > MGC > Setup and select the Left Right Tiling option. 23. Select the Menu > Other > Window > Set Grid. Set the Snap X to 0.01and Snap y to 0.01 24. Choose the Menu > Other > Layers > Show Layer Palette and chose the layers PWELL, NWELL, ACTIVE, P_PLUS_SELECT, N_PLUS_SELECT, POLY, CONTACT_TO_POLY, CONTACT_TO_ACTIVE, METAL1, VIA, METAL2. 25. Select the source window. Select one of the MOS transistors and click the place option from the palette. Place by taking the schematics as reference. 26. Similarly place the other MOS transistor also. 27. Connect the POLY layer from the PMOS to NMOS. For this select the POLY layer from the layer palette. Choose the Palette > PAT*. Select the options tab and enter the width as 2. Draw the POLY to connect the gates of the two transistor 28. Choose the Metal1 layer from the layer palette. Choose the Palette > PAT*. Select the options tab and enter the width as 3. Draw it on top of PMOS and the bottom of NMOS so that it forms the VDD and VSS Rail. 29. Similarly draw the small pieces of Metal1 so that it forms the input and output port. 30. Select the VDD rail. Choose the Menu > Connectivity > Port > Add to port. Select the VDD net and choose OK. 31. Do the similar things other ports as well. 32. Extend the POLY layer in between the PMOS and NMOS to bring the connection to Metal1 layer. 33. To do this Select the POLY layer from the Layer Palette. Choose the Palette > PAT*. Select the options tab and enter the width as 5. Draw the POLY for a distance of 5microns. 34. Select Palette > RU* and mark it for a distance of 1.5 microns from inner edge of poly extension.

35. Choose the CONTACT_TO_POLY layer form the palettes. Select the Palette > PAT*. Choose the 'options' tab and enter the width as 2. Draw the CONTACT_TO_POLY from the edge of the marking for a distance of 2 microns. 36. Zoom into one of the Input port select Menu > Routing Iroute. Click on the port and press the Space key to till you insert the Metal1 via. Click the port again and press the W key and enter the width as 5. Drag the cursor towards the poly layer with the contact overlap. Over the poly contact with Metal1 and extend a bit. 37. Choose the Menu > Routing > Iroute and route all the overflows. 38. Right Click on the Layout window. Choose the ADD > Cell option and browse to the path: $ADK/technology/ic/process/ami05_via/pwell_contact. Choose OK. And place it on the VSS Metal1 connection such that it should touch the pwell layer of the NMOS. 39. Select the VSS Metal1. Select the Menu Edit > Flatten and then choose OK. Extend the Metal1 layer so that it properly overlaps the contact. 40. Right Click on the Layout window. Choose the ADD > Cell option and browse to the path: $ADK/technology/ic/process/ami05_via/nwell_contact. Choose OK. And place it on the VSS Metal1 connection such that it should touch the pwell layer of the NMOS. 41. Select the VDD Metal1. Select the Menu Edit > Flatten and then choose OK. Extend the Metal1 layer so that it properly overlaps the contact

Physical Verification and Parasitic Extraction 42. To make that your layout is DRC free. Choose the Menu > Checking > DRC (ICRules). Inspect the transcript at the bottom of the tool and make sure that Total Results is 0. If you have the Total results other than 0, then choose Menu > Checking > First Error. Make necessary modifications in the layout to correct the errors. For subsequent errors. Choose the Menu > Checking > Next Error. 43. Generate the GDSII by selecting Translate > Write GDSII. In the Output GDS file path enter: $WORK/spice_to_layout/layout/inv.gds 44. Click on the Write options. Select the Replace Existing GDSII Stream File. Select the Add text on ports. Choose OK and again OK. 45. Choose the Menu > MGC > Transcript > Show transcript. Make sure that there are 0 errors and warnings. 46. Open the inv.cir file and change the transistor model to n and p, which are currently nmos and pmos. This is because the model definition in the rule file is defined n and p. 47. Choose the Menu > Calibre > Calibre DRC. Browse to the Calibre Home folder. This is the

path where Calibre software has been installed. 48. Choose Cancel in the Load Runset Dialog box. 49. Click on the Rules tab. Browse to the path: $ADK/technology/ic/process/ami05.rules 50. In the Calibre Run directory browse to path: $WORK/spice_to_layout/layout 51. Select the Inputs tab. In the Layout tab browse to the file: $WORK/spice_to_layout/laypout/inv.gds 52. Choose the Format as GDSII 53. Uncheck the Export from Layout viewer tab. 54. Enter the Top Cell as inv. 55. Select the output tab and inspect it leave the options to its default values. 56. Click on the RUN DRC button. This should display two windows. The RVE window and the DRC Summary Report. It should be DRC clean 57. Close all the Calibre windows. 58. In IC Station select the Menu > Calibre >RUN LVS 59. Choose Cancel in the Load Runset Dialog box. 60. Click on the Rules tab. Browse to the path: $ADK/technology/ic/process/ami05.rules 61. In the Calibre Run directory browse to path: $WORK/spice_to_layout/layout 62. Select the Inputs tab. In the Layout tab browse to the file: $WORK/spice_to_layout/layout/inv.gds 63. Choose the Format as GDSII 64. Uncheck the Export from Layout viewer tab 65. Enter the Top Cell as inv. 66. Click on the Netlist tab and browse to the file: $WORK/spice_to_layout/eldo/inv.cir 67. Choose the Format as SPICE

68. Enter the Top Cell as inv. 69. Click the H-cells tab. Select the Use Hcells file. Browse to the path: $ADK/technology/adk.hcell. 70. Choose the Outputs tab and inspect it. Leave the settings to default. 71. Click on the RUN LVS tab. 72. This will open the Calibre RVE and the LVS report file. Make sure that there are no errors and it shows a smiley face. 73. Close all the Calibre windows. 74. In IC Station choose Menu > Calibre > RUN PEX. 75. Choose Cancel in the Load Runset Dialog box. 76. Click on the Rules tab. Browse to the path: $ADK/technology/ic/process/ami05.rules 77. In the Calibre Run directory browse to path: $WORK/spice_to_layout/layout 78. Select the Inputs tab. In the Layout tab browse to the file: $WORK/spice_to_layout/layout/inv.gds 79. Choose the Format as GDSII 80. Uncheck the Export from Layout viewer tab 81. Enter the Top Cell as inv. 82. Click on the Netlist tab and browse to the file: $WORK/spice_to_layout/eldo/inv.cir 83. Choose the Format as SPICE 84. Click the H-cells tab. Select the Use LVS Hcells file. Browse to the path: $ADK/technology/adk.hcell. 85. In the PEX xcells file option. Browse to the path: $ADK/technology/adk.hcell. 86. Choose the Outputs tab and inspect it. Leave the settings to default. 87. Click on the RUN PEX. This should open the PEX netlist.

88. In the PEX netlist file window choose the File > Open and open the inv.cir. Copy and paste the following part in the inv.pex.netlist:

x1 vss vdd vout vin inv c1 vout vss 0.1p .lib $ADK/technology/accusim/ami05.mod .connect vss 0 v1 vdd vss dc 5v v2 vin vss pulse (0v 5v 0 5ns 5ns 50ns 100ns) .tran 1n 1u .plot tran v(vin) .plot tran v(vout) .end 89. Modify the ports according to the naming convention in the pex netlist. 90. Invoke a terminal. Move to the folder $WORK/spice_to_layout/layout. 91. Simulate the inv.pex.netlist with the command. eldo inv.pex.netlist -cou 92. View the waveform in Ezwave by giving the command. ezwave inv.pex.netlist.wdb 93. Open the simulated waveform which you had done in the start of the lab and compare the two output waveforms. 94. This completes the full flow for an inverter in Spice-to-layout flow.