Implementation

DMA channel entity DMA channel's interface is composed of:

interface to the upper entity (DMA controller) o cmd This bus tells the DMA channel how to interpret the data on the `addr_in' bus (basically, tells what register to load with data on 'addr_in'). The following commands can be sent (they are shown together with the values sent through the `cmd' and `addr_in' buses):
command nop set transfer count set source address set destination address set RAM read delay clocks number set RAM write delay clocks number set IO read delay clocks number 0 1 2 3 4 5 6 cmd bus contents any transfer count source address destination address RAM read delay clocks number RAM write delay clocks number IO read delay clocks number IO write delay clocks number any any any any transfer type (0 for nop, 1 for copy, 2 for swap) addr_in bus contents

set IO write delay clocks 7 number set source type as RAM set source type as IO set destination type as RAM 8 9 10

set destination type as IO 11 set transfer type

o

12

addr_in Maybe `addr_in' is not the best name, as long as through this bus are also sent many other things than source/destination addresses (see table above).

run If the channel is ready (no transfer in progress), and suspend is not requested, raising this line for at least a clock triggers a new transfer. Otherwise, it is ignored. o ready Signalizes that no transfer is in progress. o suspend When raised, the channel is requested to suspend. It completes the current elementary operation (copy or swap a location), then enters suspend mode and activates the `suspend_ack' line. o suspend_ack Acknowledges that the channel is in suspend mode. interface to RAM o ram_wr o ram_addr o ram_di o ram_do interface to IO o io_wr o io_addr o io_di o io_do
o

The DMA channel schematics is shown below:

DMA channel timings:

DMA channel test entity The testing strategy was to build a dedicated upper layer that wraps around the DMA channel entity and contains all the ingredients for a realistic simulation. That is, it contains a DMA channel, two RAMs, some additional logic and a dedicated testing interface. Testing can be done through VHDL bench tests or through simulator macros. Included in this package is a set of Modelsim macros for this purpose (please find the .do macro files in the same directory as the VHDL sources).

Whatever the testing method, through bench tests or macros, the test consists of the following steps:

gain control over the RAMs and set up their contents grant the DMA channel access to RAMs issue commands to the DMA channel (setup channel and make transfers) gain control over the RAMs and check RAMs contents to see if the data was moved correctly

DMA controller entity DMA controller's interface is composed of:

interface to the host: o cmd This bus tells the DMA controller how to interpret the data on the `addr_in' bus (what register to load with data on 'addr_in'). The following commands can be sent, on a per-DMA channel basis. They are shown together with the values sent through the `cmd' and `addr_in' buses:
command nop 0 cmd bus contents any next channel in chain available clocks request flag (1 for actually requesting a transfer, 0 if trying to cancel a transfer request that was not acknowledged yet) addr_in bus contents

set next channel in 1 chain set available clocks (per transfer quanta) request transfer 2

o o

addr_in Used in conjunction with `cmd' bus (see table above) ready When the controller raises this line, it signalizes that all channels have completed their transfers. It can be used as an overall interrupt line.

suspend General suspend input. When the host raises it, the controller suspends all channels and then signalizes `suspend acknowledge' by raising the `suspend_ack' line. o suspend_ack See the above entry (`suspend'). o selch This bus is used to select the specific DMA channel to which commands are sent via the `ch_cmd' and `ch_addr_in' buses. o ch_cmd This is the DMA channel-level cmd bus (see the DMA channel entity description, the `cmd' bus). o ch_addr_in This is the DMA channel-level addr_in bus (see the DMA channel entity description, the `addr_in' bus). o ch_ready Signalizes whether the currently selected channel is ready or not. Can be used, for example, if the host choses not to use the interrupts to find when a transfer is complete, but rather to directly check channel's `ready' flag. interface to RAM o ram_wr o ram_addr o ram_di o ram_do interface to IO o io_wr o io_addr o io_di o io_do
o

DMA controller timings:

When setting up an individual channel, put on `selch' the proper data to select

the channel and use the `ch_cmd' and `ch_addr_in' buses to set up channel parameters, as shown in the DMA channel entity - timings. DMA controller test entity For testing the DMA controller, the same methodology was chosen as for DMA channel. A DMA controller test entity was built, that wraps around the DMA controller. It contains a DMA controller, 2 RAMs and additional logic for switching RAMs buses towards the DMA controller or towards the test entity's interface.