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OP_TRI_GEN.CIR
This signal generator gives you two waveforms for the price of one: a triangle-wave and a square-wave. What is the central component of this circuit? The integrator capacitor CI. Basically we are interested in performing two functions on CI: charge it, discharge it - repeat indefinitely. During the design process, we ask these essential questions
1. 2. 3. 4. How do we charge/discharge CI? How fast do we charge/discharge CI? How do we switch from charging to discharging? When do we switch from charging to discharging and visa-versa?
Most likely, there are scores of circuit options for every question. It all depends on the usual design context - budget, required accuracy, schedule, available components, personal experience and so on. Here's one simple incarnation of the triangle wave generator.
LINEAR RAMPS
How do we charge / discharge CI? A triangle wave implies that our circuit generates a linear voltage ramp. One way to achieve this goal is by charging / discharging CI with a constant current. The Op Amp Integrator provides a handy way to accomplish this. Here's a simplified version of the circuit.
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Connect RI to VN and what happens? With V- held at the virtual ground (0V), a constant current flows from V- to VN.
Ramp Up
Iin = VN / RI. CI integrates Iin creating a positive linear ramp at Vo. The ramp is linear because Vo changes proportionally to the time elapsed T. Vo = - VN / (CI RI) T Connect RI to VP and a constant current flows from VP to V-, Iin = - VP / RI. Now Vo ramps down linearly
Ramp Down
Vo = - VP / (CI RI) T To control the period of the generator, you need to answer this - how fast does Vo ramp up and down? Just look at the above equations and solve for Vo / T.
How Fast? Ramp Up:
Vo / T = - VN / ( CI RI ) Ramp Down: Vo / T = - VP / ( CI RI )
These equations show you the parameters available to control the ramp up / down speeds.
COMPARATOR
And for our final question: how www.ecircuitcenter.com/Circuits/op_tri_gen/op_tri_gen.htm do we switch from ramping up to ramping down? Our goal is to replace
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And for our final question: how do we switch from ramping up to ramping down? Our goal is to replace the switch and VP/VN levels in the simplified circuit above. Here's one way to do it - an Op Amp Comparator with two thresholds. This simple yet wondrous circuit changes it's output state from VN to VP (or vise-versa) depending on the upper Vth+ and lower Vth- thresholds. Vth+ = - VN R1 / R2 Vth- = - VP R1 / R2 How does it work?
When Vin > Vth+, the output switches to VP, the POSITIVE output state. When Vin < Vth-, the output switches to VN, the NEGATIVE output state.
Zener diodes D1 and D2 set the positive and negative output levels: VP = Vf D1 + VZ D2 VN = Vf D2 + VZ D1. These output levels do double duty! Not only do they set the comparator thresholds, but also set the voltage levels for the next stage - the integrator.
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And don't forget the option of changing the reverse voltage of the zener diode via the BV parameter. Just remember the charging currents and thresholds will change too.
HOW ACCURATE?
You may have noticed that the triangle peaks and period may not accurately meet our +/-10V swing at 100 us. Why? The main reason is that our current source and thresholds are derived from zener diodes - not exactly the most accurate reference on the planet! You may need to spend a few bucks on trim pots for both R1 and RI. Other options for improving accuracy include bringing in some precision references for VP and VN. Some designs use improved means for deriving and switching the current sources that charge CI.
ASYMMETRICAL VOLTAGES
You can create asymmetrical voltage swings by including a reference voltage VREF to the comparator's negative input. (Actually, its been there all along, just set to 0V.) VREF let's you place the thresholds more freely - they can now both be positive or negative. Basically, VREF can shift the thresholds up or down as shown in the equation. Vth+ = VREF (R1+R2)/R2 - VN R1 / R2 Vth- = VREF (R1+R2)/R2 - VP R1 / R2 HANDS-ON DESIGN Pick new thresholds by including VREF. For example, set R1 = R2 = 10k and VREF = 2.5 V. Run a new simulation and check your new triangle boundaries. Again, make sure your Vth+ and Vth- are not outside the +/-15V limits of the op amp model!
ASYMMETRICAL RAMPS
Good news! You're not confined to equal ramp up and down rates. For this trick, create a new voltage source VREF2 and connect it to the integrator's positive input. For example, add VREF and change XOP1 to look like this.
X O P 1923O P A M P 1 V R E F 2902 V
What does this do? Now you've got two different current-source levels to charge CI. Iin+ = ( VP - V+) / RI. Iin- = (VN - V+) / RI. For example, set VREF2 to a voltage like 2V. With VREF2 = 2V, VP = 5V, VN = -5 V and RI = 12.5 kohms, you get unequal constant currents of Iin+ = -0.24 mA and Vin- = 0.56 mA. Rerun the simulation. You're triangle wave should start looking like sawtooth.
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SIMULATION NOTES
The model for the op amp in this circuit includes a +/-15 V clamp accomplished by zener diodes. This models the limited voltage swing of a typical op amp. You can change this to reflect the supply rails and output limits of the op amp you are using. To help our circuit start, we set the initial voltage of the CI to 0.1 V by the appending I C = 0 . 1 V to the CI statement. You could set it to some other voltage if you wish. Also, don't forget to tell SPICE to use this initial voltage by adding UIC (Use Initial Conditions) to the TRAN command. Find out more about the Op Amp Comparator and the Op Amp Integrator? For a more detailed description of the op amp, see the Basic Op Amp Model. For a quick review of subcircuits, check out Why Use Subcircuits?
SPICE FILE
Download the file or copy this netlist into a text file with the *.cir extension. O P _ T R I _ G E N . C I R-O P A M PT R I A N G L EG E N E R A T O R * *I N T E G R A T O R R I 1 2 1 2 . 5 K C I 3 2 0 . 0 0 1 U FI C = 0 . 1 X O P 1 023 O P A M P 1 * * *C O M P A R A T O RW I T HH Y S T E R E S I S R 1 3 4 2 0 K R 2 4 1 1 0 K X O P 2 456 O P A M P 1 R L I M 6 1 1 0 0 0 D 1 1 7 D Z 1 D 2 0 7 D Z 1 * *V R E F V R E F 5 0 0 V * * *O P A M PM A C R OM O D E L ,S I N G L E P O L EW I T H1 5 VO U T P U TC L A M P *c o n n e c t i o n s : n o n i n v e r t i n gi n p u t * | i n v e r t i n gi n p u t * | | o u t p u t * | | | . S U B C K TO P A M P 1 1 2 6 *I N P U TI M P E D A N C E R I N 1 2 1 0 M E G *D CG A I N = 1 0 0 KA N DP O L E 1 = 1 0 0 H Z *U N I T YG A I N=D C G A I NXP O L E 1=1 0 M H Z E G A I N 30 12 1 0 0 K R P 1 3 4 1 0 0 K C P 1 4 0 0 . 0 1 5 9 U F * Z E N E R L I M I T E R www.ecircuitcenter.com/Circuits/op_tri_gen/op_tri_gen.htm
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*Z E N E RL I M I T E R D 1 4 7 D Z L I M D 2 0 7 D Z L I M *O U T P U TB U F F E RA N DR E S I S T A N C E E B U F F E R50 40 1 R O U T 5 6 1 0 * *Z E N E RT OL I M I TO P A M PO U T P U TS W I N G( + / -1 5 v ) . m o d e l D Z L I M D ( I s = 0 . 0 5 uR s = 0 . 1B v = 1 4 . 3I b v = 0 . 0 5 u ) . E N D S * *Z E N E RT OL I M I TC O M P A R A T O RO U T P U TS W I N G . m o d e l D Z 1 D ( I s = 0 . 0 5 uR s = 0 . 1B v = 4 . 3I b v = 0 . 0 5 u ) * *A N A L Y S I S . T R A N 0 . 5 U S3 0 0 U SU I C * *V I E WR E S U L T S . P R I N TT R A N V ( 3 )V ( 1 ) . P R O B E . E N D
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