METU-EEE

EE 314-Digital Electronics Laboratory

5. ELEMENTARY GATE NETWORKS

I. INTRODUCTION 1. Objectives In this experiment, some of commonly used gate networks, such as multiplexers, comparators, and code converters are investigated using discrete components and XILINX software. 2. Background a. Multiplexers Digital multiplexers are combinational (non-memory) devices controlled by a selector which routes one of many input signals to the output. They can be considered as electronic equivalents of multiposition switches. Figure 5-1 gives the block diagram of an m-input, n-bit multiplexer. INPUT SIGNALS I11 I12
. .

I1n

I 2 1 I2 2
. .

I2n

Im1 Im2 Imn

. .

SELECT SIGNALS

S1 S2
. .

SELECTOR NETWORK

Sk
. .

Z1

Z2 OUTPUTS

Zm

Figure 5-1. The block diagram of an m-input, n-bit multiplexer. M groups of signals, where each group consists of n signals, can be multiplexed by a sufficient number of select inputs. In an ideal case, k select inputs can control n=2k signals per group.

3-input 2-bit multiplexer

In this multiplexer, S is the select input, Ia(Ia1Ia2), Ib(Ib1Ib2), Ic(Ic1Ic2) are the input groups, and Za, Zb, Zc are the outputs. E is an enable (active low) signal. That is, when E=1, Za=Zb=Zc=0 independent of the input signals. When E=0, depending on the value of the select input S, Zi will be either Ii1 or Ii2 where i=a, b, c. Figure 4-2 gives the schematic view of 3-input 2-bit multiplexer.

Experiment 5

METU-EEE

EE 314-Digital Electronics Laboratory

Ia1 E

Ia2

Ib1

Ib2

Ic1

Ic2

S1

Za Zb Zc Figure 5-2. The schematic view of 3-input 2-bit multiplexer. b. Comparators Comparators are used to compare two n-bit numbers and give an output signal indicating that the first number is greater than, equal to, or less than the second number. Table 5-1 gives the truth table of a 2-bit comparator. Table 5-1. The truth table of a 2-bit comparator

A A1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B A0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

A<B B0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

A=B Z2
1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1

A>B Z3
0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0

B1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Z1
0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0

c. Code converters There are coding systems other than the binary coding such as, excess-3 code, Gray code, etc. The Gray code has the property that any consecutive codes differ only by a single bit. Table 5-2 and Table 5-3 give the truth tables for two bit and four bit Gray codes respectively. Note the mirror image property (except for the most significant bit) of the Gray code.
Experiment 5 2

METU-EEE

EE 314-Digital Electronics Laboratory

Table 5-2. Truth table of 2-bit Gray code.

DECIMAL
0 1 2 3

G1
0 0 1 1

G0
0 1 1 0

Table 5-3. Truth table of 4-bit Gray code

BINARY DECIMAL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

GRAY B0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

B3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

B1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

G3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

G2
0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

G1
0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

G0
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

II. PRELIMINARY WORK 1. Read sections 4.7 and 4.10 from Digital Design, by Mano. 2. Read the experiments 1, 3 & 4 to refresh your mind about the design entry, simulation and design downloading in XILINX program. Bring the manuals for these experiments. 3. It is known that the following circuit is an 8-bit multiplexer. What is F(Q1,Q2,S2)? Select signal: S2S1S0 Input: A7...A0

Experiment 5

METU-EEE

EE 314-Digital Electronics Laboratory

4. Design a 16 to 1 multiplexer with the minimum number of select signals, using only 4-input, 3-input, 2-input NAND gates and INVERTERS, keeping the usage of hierarchical design in mind. (to be implemented in XILINX) 5. Design a 16 to 1 multiplexer with the minimum number of select signals, using 74151 IC s and NAND gates. (to be implemented on protoboard) 6. By using the truth table of the comparator given in Table 1, design a minimized comparator circuit to compare two 4-bit numbers, i.e., it has two 4-bit inputs and 3 outputs. Note that at any time only one of the outputs can be at logic level 1. This design will be implemented in XILINX and you are not allowed to use any complex gates from the libraries. You can only use NAND, NOR, XOR, and Inverter gates in your design. 7. Design a binary to gray converter and a gray to binary converter, using the truth table given in Table 3. This design will be implemented on protoboard. You are allowed to use NAND, XOR, and INVERTERS only. III. EXPERIMENTAL WORK 1. Construct the circuit you designed in Part 5 of the preliminary work on protoboard and test it. 2. Read the IMPORTANT NOTE below before proceeding. Draw the circuit you designed in part 4 of the preliminary work in XILINX. Perform the simulation to show that the circuit operates as a 16 to 1 multiplexer. As a final step, download your design into the XILINX FPGA box and test it using the box to verify that it also works as in the simulations. 3. Draw the circuit you designed in part 6 of the preliminary work in XILINX. Perform the simulation to show that the circuit operates as a comparator. As a final step, download your design into the XILINX FPGA box and test it using the box to verify that it also works as in the simulations. 4. Construct the circuits you designed in part 7 of the preliminary work on protoboard. Test the circuits to show that they operate as Binary to Gray and Gray to Binary converters respectively.

IMPORTANT NOTE :
i. A 16 to 1 MUX needs 4 select inputs and 16 data inputs. Thus we need 20 switches. Fortunately we have 4x8=32 switches installed on the box. You should assign 4 of them to select signals and 16 of them to 16 data inputs. Since 16-bit MUX requires many gates and routings between them, it will be wise to design a 4-bit MUX firstly, and then design 16-bits MUX hierarchically. Wire naming is a very useful method for large designs. The idea is the following; every wire with the same name is just connected to each other. See the example below:

ii.

iii.

Experiment 5

METU-EEE

EE 314-Digital Electronics Laboratory

Figure 5-3 Wire naming All wires with the same name are connected to each other. In more detail, the output of the IBUF of input A is connected to the D0 input of M2_1 since those wires have the same name, A_BUF. Similarly, the wires with the names B_BUF are also connected to each other, and so on. Although wire naming is useful for large circuits, the designer should be careful about the fact that, any wire with the same name will be connected. In order to give a name to a wire, right click on the wire and rename it.

Experiment 5

METU-EEE

EE 314-Digital Electronics Laboratory

IC LIST FOR EXPERIMENT 5 74151 7410 7400 7404 7486 Two 8 to 1 multiplexers with active low enable (Figure 5-3) Three 3-input NAND gates Four 2-input NAND gates Five inverter gates Four 2-input XOR gates

ENABLE

7 E 4 3 2 1 D0 D1 D2 D3 D4 D5 D6 D7 9 A

16 VCC

8 GND

Data Inputs

15 14 13 12

7 4 L S 1 5 1

~Y

B 10

C 11

Select Inputs

~Y resembling the inverse of Y.

ENABLE E 1 0 0 0 0 0 0 0 0 SELECT A X 0 0 0 0 1 1 1 1 SELECT B X 0 0 1 1 0 0 1 1 SELECT C X 0 1 0 1 0 1 0 1 OUTPUT Y 0 D0 D1 D2 D3 D4 D5 D6 D7

Figure 5-4. The pin diagram and function table of IC type 74151 8 x 1 multiplexer
Experiment 5 6

METU-EEE

EE 314-Digital Electronics Laboratory

Figure 5-5. Digital Gates in IC Packages with Identification Numbers and Pin Assignments

Experiment 5