ARM Simulator Release Notes

Release 4.6.12.0

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ARM Simulator Release Notes

These release notes provide important information that will assist you in using the ARM simulator. This document contains product information and known issues that are specific to the ARM simulator. The release notes contain the following sections: General Information o o o o o Supported Configuration Related Documentation New in this Release Simulator Version Details Limitations

Known Issues Reporting Issues

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Release Notes

General Information
The ARM simulator is available within the IDE (Integrated Development Environment) of the Code Composer Studio for simulating ARM based devices. The ARM simulator release package contains an executable that must be installed to use the simulator to access release notes and datasheet.

Supported Configuration
Following table lists the ARM simulator configurations supported in this release. Sl. No.
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Simulator Configuration
ARM968 (Little Endian, Big Endian)

Description
Simulates ARM968 CPU processor (cycle count accurate) Supports unaligned memory access, pre-fetch aborts, and undefined instructions Simulates ARM11 CPU processor (instruction count accurate) Supports nonmaskable FIQ (Fast Interrupt Request), undefined instructions, and advanced profiling Simulates Cortex M-3 CPU processor (instruction count accurate) Supports protocol compliant memory interfaces, memory protection unit, and basic exception model Simulates Cortex R-4 CPU processor (instruction count accurate) Supports 4GB flat memory with mixed endianness and unaligned memory accesses, basic support for CP15 registers

ARM11 (Little Endian, Big Endian, and Big Endian (BE-8))

Cortex M-3 (Little Endian, Big Endian, and Big Endian (BE-8))

Cortex R-4 (Little Endian, Big Endian, and Big Endian (BE-8))

The supported operating system is Microsoft Windows NT/2000/XP. To obtain ARM11, Cortex M3 or R4 simulators, please contact sim_support@list.ti.com

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Release Notes

Related Documentation
In addition to these release notes, the ARM simulator release package includes the following documentation:

ARM Datasheet - SPRS397

New in this Release

Fix for SDSCM00019903. New ARM instructions that were previously not supported by Cortex R4 simulator have been introduced. o CPS, REV. BKPT instruction shall be treated as a NOP.

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Release Notes

Simulator Version Details

Following table provides version details of the ARM Simulator: Simulator Version
4.6.12.0 4.6.11.0 4.6.10.0 4.6.9.0 4.6.8.0 4.6.6.0 4.6.5.0

Feature
Fix for SDSCM00019903 CPS, REV instruction support for R4 Fix for SDSCM00019301 Fix for SDSCM00018920, SDSCM00018687, SDSCM00019226 Cortex M3 validated completely Fix for SDSCM00017250, SDSCM00017410, SDSCM00017054 Fix for SDSCM00016299 Full instruction set architecture Functional simulator Unaligned memory accesses Data abort Prefetch abort Undefined instructions Protocol compliant memory interfaces

Release Date
24-09-2007

21-08-2007 13-08-2007 29-06-2007 22-05-2007 27-04-2007 11-04-2007

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Limitations
Following are the limitations of ARM968 simulator: Imprecise aborts Does not support peripherals, advanced debug features, and analysis features of Code Composer Studio Architecturally unpredictable scenarios are not trapped by simulator Limitations of AHBLite are: o o Instruction prefetch buffer and AHB( Advanced Highperformance Bus) write buffer cannot be modeled Various types of BUS transfers including non-cacheable instruction fetches and data loads, non-buffered data stores, buffered data stores, non-cacheable, and nonbufferable data swap operations cannot be modeled Lock, burst transfer, and protection control are not supported SPLIT or RETRY responses from slave (DMA) are not supported Only single word transfer is modeled

o o o

Following are the limitations of Cortex R-4 simulator: No cycle information No memory maps; entire memory is treated as a flat memory with 0 latency Buses, Caches and buffers are not modeled. MPU is not modeled. Following instructions are not supported o o o ARMv7R instructions for multi-core environment (event handling). They are treated as NOPs Co-processor instructions for other than move instructions for CP15 registers are not supported Exclusive load/store instructions are treated as normal load/store instructions. Monitor is not modeled, hence instructions, other than load/store, using the monitors are treated as NOPs.

Does not support Code Composer Studio advanced debug and analysis features.

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Following are the limitations of ARM11 simulator: Only the ISA and exception model has been modeled. No memory maps; entire memory is treated as a flat memory with 0 latency Imprecise aborts. Does not support Code Composer Studio advanced debug and analysis features. Architecturally unpredictable scenarios are not trapped by simulator.

Following are the limitations of Cortex M-3 simulator: Loading a test case and running it without setting T = 1 or setting proper start pointer would lead to LOCKED situation. The absence of a valid PC in the vector table would lead to a LOCK OUT situation. As a work around, for applications with invalid program counter in the vector table, after reset, a step is to be issued and the application should be reloaded to avoid the lock out situation. CPSR ( Current Program Status Register) debug view available o o Displays bit fields corresponding to older ARM variants. T bit shown by CPSR field tree view is not in correct position of T bit. To avoid confusion, users are advised not to use this view.

Memory mapped registers no separate views are available. You must view them in the debug memory view only. Exporting memory attributes through the MEMATTRx signal is not supported. Unaligned access into the system control space memory mapped registers such as MPU (Memory Protection Unit), NVIC (Non Vector Interrupt Controller), and SBC (System Control Block) is ignored. Buffers are not modeled. But all bus faults are treated as imprecise bus faults. Maximum number of priority bits supported is fixed to 8. Following are not modeled: o o o Ability to continue interrupts for LDM/STM instructions. SysTick timer and any debug models. Peripheral ID registers, Emulation support (DWT (Data Watch point and Trace), FPB (Flash patch and Breakpoint), ROM TABLE, ITM (Instrumentation Trace

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Release Notes

Macro cell), ETM (Embedded Trace Macro cell), and AHB Trace Macro Cell interface). o o o o WFE (Wait for Event). WFI (Wait for Interrupt). TXEV, RXEV. RESETREQ (Reset Request) , SYSRESETREQ (System Reset Request) resets the request signals coming out of Cortex M-3.

Architecturally unpredictable scenarios are not trapped by simulator.

Known Issues
The following section provides known issues that are filed in this release:

Identifier
SDSCM00013235

Headlines
M3 and R4 CCS simulators display ARM mode and Little Endian on the bottom C64x+ configurations does not come up if cortex 3.3.525 is installed over CCS 3.3 RTM

Component
ARM CPU

Target
Cortex M3 and Cortex R4 simulators

SDSCM00017940

C6000 SimInternal Components

C64x+

Reporting Issues
To report issues in this release, send an email to sim_support@list.ti.com addressing the issue.

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