Lead Lag Handout

EE 3CL4, 6 1 / 50 Tim Davidson Compensators Lead compensation
Design via Root Locus Lead Compensator example
EE3CL4: Introduction to Linear Control Systems

Section 6: Design of Lead and Lag Controllers using Root Locus Tim Davidson
McMaster University
Cascade compensation and steady-state errors Lag Compensation

Design via Root Locus Lag compensator example
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Winter 2013

Outline
1 Compensators 2 Lead compensation


3 Cascade compensation and steady-state errors 4 Lag Compensation
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5 Insights

Compensators
Early in the course we provided some useful guidelines

regarding the relationships between the pole positions of a system and certain aspects of its performance Using root locus techniques, we have seen how the pole positions of a closed loop can be adjusted by varying a parameter
What happens if we are unable to obtain that
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performance that we want by doing this?

Ask ourselves whether this is really the performance
that we want
Ask whether we can change the system,
say by buying different components

seek to compensate for the undesirable aspects of the
process

Cascade compensation

Usually, the plant is a physical process If commands and measurements are made electrically,
compensator is often an electric circuit

General form of the compensator is
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Gc (s) =
Kc
n j =1 (s
M i =1 (s
+ zi ) + pj )
Therefore, the cascade compensator adds open loop
poles and open loop zeros These will change the shape of the root locus

Compensator design

Where should we put new poles and zeros to achieve desired performance? That is the art of compensator design We will consider rst order compensators of the form c (1 + s/z ) Kc (s + z ) K c = Kc z /p Gc ( s ) = = , where K (s + p) (1 + s/p)
with the pole p in the left half plane and the zero, z in the left half plane, too
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For reasons that will soon become clear when |z | < |p |: phase lead network when |z | > |p |: phase lag network

Lead compensation

K c (s + z ) (s + p ) with |z | < |p|. That is, zero closer to origin than pole Gc (s) =
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Let p = 1/ and z = 1/(lead ). Since z < p, lead > 1. c = Kc z /p = Kc /lead . Then Dene K Gc (s) = c (1 + lead s) K Kc (s + z ) = (s + p ) (1 + s )

With |z | < |p|, lead > 1, Gc (s) =

Frequency response:
Lead compensation
Kc (s+z ) (s+p)
Kc (1+lead s) (1+ s)
Gc (j ) =
Bode diagram
c (1 + j lead ) K (1 + j )

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c lead Between = z and = p , |Gc (j )| K What kind of operator has a frequency response with magnitude proportional to ? Differentiator
Note that the phase is positive. Hence phase lead

A passive phase lead network

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Homework: Show that characteristic
V2 (s) V1 (s)
has the phase lead

Active lead and lag networks
Heres an example of an active network architecture.

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Principles of Lead design via Root Locus

The compensator adds poles and zeros to the P (s ) in
the root locus procedure.

Hence we can change the shape of the root locus. If we can capture desirable performance in terms of

positions of closed loop poles

then compensator design problem reduces to: changing the shape of the root locus so that these desired closed-loop pole positions appear on the root locus nding the gain that places the closed-loop pole positions at their desired positions What tools do we have to do this? Phase criterion and magnitude criterion, respectively
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Root Locus Principles

The point s0 is on the root locus of P (s) if 1 + KP (s0 ) = 0. In rst order compensator design with G(s) = and Gc =
Kc (s+z ) (s+p) , Q (s+zi ) KG M Qn i =1 j =1 (s +pj ) QM (s+z ) Qi =1 (s+zi ) n (s+p) j =1 (s +pj )
we have P (s) =
and

K = Kc KG . We will restrict attention to the case of K > 0 Phase cond. s0 is on root locus if P (s0 ) = 180 + k 360 :
M n
(angle from zi to s0 )
i =1 j =1
(angle from pj to s0 )
+ (angle from z to s0 ) (angle from p to s0 ) = 180 + k 360 Mag. cond. If s0 satises phase condition, the gain that puts a closed-loop pole at s0 is K = 1/|P (s0 )|: K =
n j =1 (dist M i =1 (dist
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from pj to s0 ) from zi to s0 )
(dist from p to s0 ) (dist from z to s0 )

RL design: Basic procedure

1
Translate design specications into desired positions of dominant poles Sketch root locus of uncompensated system to see if desired positions can be achieved If not, choose the positions of the pole and zero of the compensator so that the desired positions lie on the root locus (phase criterion), if that is possible Evaluate the gain required to put the poles there (magnitude criterion) Evaluate the total system gain so that the steady-state error constants can be determined If the steady state error constants are not satisfactory, repeat

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This procedure enables relatively straightforward design of systems with specications in terms of rise time, settling time, and overshoot; i.e., the transient response. For systems with steady-state error specications, Bode (and Nyquist) methods may be more straightforward (later)

Lead Comp. example

Consider a case with G(s) = s(s1 +2) and H (s ) = 1. Design a lead compensator to achieve: damping coefcient = 0.5 and velocity error constant Kv = lims0 sGc (s)G(s) > 20 swift transient response (small settling time) What to do? Can we achieve this with proportional control? If not we will attempt lead control
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Attempt prop. control

Sketch root locus of
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Sketch rays of angle cos (0.5) = 60 to neg. real axis Are there intersections? Yes If so, what is the corresponding value of K = KP KG ? K = d1 d2 = 5 Does that K generate a large enough velocity error const.? No, Kv = 2.5 :( Do the closed-loop poles have responses that decay quickly? No, Ts 4s
1 s(s+2) 1

Prop. control, step response

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Lead compensated design

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Plot poles of G(s). Where should the closed-loop poles be? cos1 (0.5) = 60 Note that the settling time is not specied; it only needs to be small. This provides design exibility. However, we need a large Kv which will require large gain. Need desired positions far from open loop poles. Lets start with desired roots at 4 j 8 This pair has Ts = 1s and n = 42 + 82 8.9

Lead Comp. example

Now where to put the zero and pole? (Centroid denoted ca ) Rule of thumb: put zero under desired root, or just to the left Determine position of the pole using angle criterion angles from OL zeros angles from OL poles = 180 90 (116 + 104 + p ) = 180 = p 50 Hence pole at p 10.86
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Lead Comp. example

Gain of compensated system: d1 d2 dp Prod. dist. from open-loop poles = Prod. dist. from open-loop zeros dz 8.94(8.25)(10.54) 97.1 8 Hence compensated open loop: Gc (s)G(s) =
97.1(s+4) s(s+2)(s+10.86)
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Velocity constant: Kv = lims0 sGc (s)G(s) 17.9 :(

What to do now?
We tried hard, but did not achieve the design specs Lets go back and re-examine our choices Zero position of compensator was chosen via rule of

thumb
Can we do better?
Yes, but two parameter design becomes trickier.

What were other choices that we made? We chose desired poles to be of magnitude n 8.9 We could choose them to be further away
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(faster transient response)

By how much? Show that when desired poles have n = 10 as well as
the required = 0.5, then the choice of z 4.47, p 12.5 and KC 125 results in Kv 22.3

Root Locus, new lead comp.

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Centroid denoted ca

New lead comp.

Prop.-contr. Controller, GC (s) OL TF, GC (s)G(s) CL TF,
Y (s ) R (s )
Lead contr.
125(s+4.47) (s+12.5) 125(s+4.47) 1 (s+12.5) s(s+2) 125(s+4.47) s(s+2)(s+12.5)+125(s+4.47)
5
5 s(s+2) 5 s(s+2)+5

CL poles CL zeros CL TF, again
1 j 2 ,
5 s2 +2s+5
4.47 j 8.94, 5.59 4.47, ,

131(1+0.013s) s2 +8.94s+100
1.71 s+5.59
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Complex conjugate poles still dominate Closed-loop zero at -4.47 (which is also an open-loop
zero) reduces impact of closed-loop pole at -5.59; see also slide 48 of Section 3: Fundamentals of Feedback

New lead comp., ramp response

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New lead comp., ramp response, detail

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New lead comp., step response

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Note faster settling time than prop. controlled loop, However, the CL zero has increased the overshoot a little Perhaps we should go back and re-design for = 0.45 in order to better control the overshoot

Outcomes
Root locus approach to phase lead design was
reasonably successful in terms of putting dominant poles in desired positions; e.g., in terms of and n
We did this by positioning the pole and zero of the lead

compensator so as to change the shape of the root locus

However, root locus approach does not provide
independent control over steady-state error constants (details upcoming)

That said, since lead compensators reduce the DC gain
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(they resemble differentiators), they are not normally used to control steady-state error.
The goal of our lag compensator design will be to
increase the steady-state error constants, without moving the other poles too far

Cascade compensation

Throughout this lecture, and all the discussion on cascade compensation, we will consider the case in which H (s) = 1. We will consider rst order compensators of the form Gc (s) = K (s + z ) (s + p)
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with the pole, p, and the zero, z , both in the left half plane when |z | < |p|: phase lead network when |z | > |p|: phase lag network

Steady-state errors
If closed loop stable, steady state error for input R (s): ess = lim e(t ) = lim s
t s0

R (s ) 1 + GC (s)G(s)
KC (s+z ) (s+p)
Let G(s) =
Q KG i (s+zi ) Q j (s +pj )
and consider GC (s) =
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Consider the case in which G(s) is a type-0 system. Steady state error due to a step r (t ) = Au (t ): A , where ess = 1+K posn Kposn = GC (0)G(0) = KC z KG i zi p j pj
Note that for a lead compensator, z /p < 1, So lead compensation may degrade steady-state error performance

Steady-state error
Now, consider the case in which G(s) is a type-1 Q
system, G(s) =
KGQ i (s+zi ) s j (s+pj )
Steady-state error due to a ramp r (t ) = At : ess = A/Kv ,

where the velocity constant is Kv = lim sGc (s)G(s) =

s 0
KC z KG i zi p j pj
Once again, lead compensation may degrade
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steady-state error performance

Is there a way to increase the value of these error
constants while leaving the closed loop poles in essentially the same place as they were in an uncompensated system? Perhaps |z | > |p|?

Lag compensation

K c (s + z ) (s + p ) with |z | > |p|. That is, pole closer to origin than zero Gc (s) =
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Let z = 1/ and p = 1/(lag ). Since z > p, lag > 1. c = Kc z /p = Kc lag . Then Dene K G c (s ) = c (1 + s ) K Kc (s + z ) = (s + p) (1 + lag s)

Frequency response
Gc (j ) = Magnitude C Low frequency gain: K Corner frequency in denominator at p = p = 1/(lag )
Corner frequency in numerator at z = z = 1/ p < z
C (1 + j ) K (1 + j lag )

C /lag = KC High frequency gain: K Phase

( ) = atan( ) atan(lag ) At low frequency: ( ) = 0 At high frequency: ( ) = 0 In between: negative, with max. lag at =
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zp

Bode Diagram

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Note integrative characteristic

A passive phase lag network

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Active lead and lag networks
Heres an example of an active network architecture.

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Lag compensator design

Lag compensator: Gc (s) = Kc
s+z s +p .
with |z | > |p|.
Recall position error constant for compensated type-0 system and velocity error constant for compensated type-1 system: Kposn = KC z KG i zi , p j pj Kv = KC z KG i zi p j pj

where in the latter case the product in the denominator is over the non-zero poles. Design Principles We dont try to reshape the uncompensated root locus. We just try to increase the value of the desired error constant by a factor lag = z /p without moving the poles (well not much) Reshaping was the goal of lead compensator design
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Lag compensator design

Design principles: Dont reshape the root locus
Adding the open loop pole and zero from the

compensator should only result in a small change to the angle criterion for any point on the uncompensated root locus Angles from compensator pole and zero to any point on the locus must be similar Pole and zero must be close together Increase value of error constant: Want to have a large value for lag = z /p . How can that happen if z and p are close together? Only if z and p are both small, i.e., close to the origin
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Lag comp. design via Root Locus

1 2

4 5
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Obtain the root locus of uncompensated system From transient performance specs, locate suitable dominant pole positions on that locus Obtain the loop gain for these points, K = KP KG ; hence the (closed-loop) steady-state error constant Calculate the necessary increase. Hence lag = z /p Place pole and zero close to the origin (with respect to desired pole positions), with z = lag p. Typically, choose z and p so that their angles to desired poles differ by less than 1 . Set KC = KP
What if there is nothing suitable at step 2? Perhaps do lead compensation rst, then lag compensation on lead compensated plant. i.e., design a lead-lag compensator

Example

Lets consider, again, the case with G(s) = s(s1 +2) . Design a lag compensator to achieve damping coefcient = 0.5 and velocity error constant Kv > 20 Note: we will get a different closed loop from our lead design. First step, obtain uncompensated root locus, and locate desired dominant pole locations
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Example

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Gain required to put closed loop poles in desired position = prod. distances from open loop poles That is, K = 2.242 = 5. Therefore KP = K /KG = 5 Velocity error const: Kv ,unc = lims0 sKP G(s) = K /2 = 2.5 The increase required is 20/2.5 = 8 That implies must choose p = z /8, where z is chosen to be close to the origin with respect to dominant closed-loop poles

Example

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Lets choose z = 0.1. Hence, p = 1/80.

Example

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Root locus of lag compd system with GC (s) =
KC (s+0.1) (s+1/80)
s: closed-loop poles for prop.-control with KP = 5 s: open-loop poles of lag compd system : OL zero of lag compd system; also a CL zero s: Closed-loop poles for lag-control with KC = 5

Example
Prop.-contr. Controller, GC (s) OL TF, GC (s)G(s) CL TF,
Y (s ) R (s )
Lag contr.
5(s+0.1) (s+0.9) 5(s+0.1) 1 (s+1/80) s(s+2) 5(s+0.1) s(s+2)(s+1/80)+5(s+0.1)
5
5 s(s+2) 5 s(s+2)+5

CL poles CL zeros CL TF, again
1 j 2 ,
5 s2 +2s+5
0.955 j 1.979, 0.104 0.1, ,

4.999(1+7104 s) s2 +1.909s+4.827
0.004 s+0.104
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Complex conjugate poles still dominate Closed-loop zero at -0.1 (which is also an open-loop
zero) reduces impact of closed-loop pole at -0.104; see also slide 48 of Section 3: Fundamentals of Feedback

Ramp response

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Ramp response, detail

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Step response

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Note longer settling time of lag controlled loop, and slight increase in overshoot, due to CL zero

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If we would like to improve the transient performance of
a closed loop
We can try to place the dominant closed-loop poles in
desired positions
One approach to doing that is lead compensator design However, that typically requires the use of an amplier

in the compensator, and hence requires a power supply If we would like to improve the steady-state error
performance of a closed loop

We can consider designing a lag compensator to
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provide the required gain

However, that typically slows down the transient
response These insights also have frequency domain
interpretations, which we will explore later

Lead Lag Handout

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EE 3CL4, 6 1 / 50 Tim Davidson Compensators Lead compensation

Design via Root Locus Lead Compensator example

EE3CL4: Introduction to Linear Control Systems

Cascade compensation and steady-state errors Lag Compensation

EE 3CL4, 6 2 / 50 Tim Davidson Compensators Lead compensation

Cascade compensation and steady-state errors Lag Compensation

Design via Root Locus Lead Compensator example

Design via Root Locus Lag compensator example

EE 3CL4, 6 4 / 50 Tim Davidson Compensators Lead compensation

Cascade compensation and steady-state errors Lag Compensation

What happens if we are unable to obtain that

performance that we want by doing this?

say by buying different components

EE 3CL4, 6 5 / 50 Tim Davidson Compensators Lead compensation

Cascade compensation and steady-state errors Lag Compensation

compensator is often an electric circuit

Therefore, the cascade compensator adds open loop

EE 3CL4, 6 6 / 50 Tim Davidson Compensators Lead compensation

Cascade compensation and steady-state errors Lag Compensation

EE 3CL4, 6 8 / 50 Tim Davidson Compensators Lead compensation

Cascade compensation and steady-state errors Lag Compensation

EE 3CL4, 6 9 / 50 Tim Davidson Compensators Lead compensation

With |z | < |p|, lead > 1, Gc (s) =

Cascade compensation and steady-state errors Lag Compensation

EE 3CL4, 6 10 / 50 Tim Davidson Compensators Lead compensation

A passive phase lead network

Cascade compensation and steady-state errors Lag Compensation

Homework: Show that characteristic

has the phase lead

EE 3CL4, 6 11 / 50 Tim Davidson Compensators Lead compensation

Active lead and lag networks

Heres an example of an active network architecture.

Cascade compensation and steady-state errors Lag Compensation

EE 3CL4, 6 12 / 50 Tim Davidson Compensators Lead compensation

Principles of Lead design via Root Locus

the root locus procedure.

Cascade compensation and steady-state errors Lag Compensation

positions of closed loop poles

EE 3CL4, 6 13 / 50 Tim Davidson Compensators Lead compensation

Root Locus Principles

Cascade compensation and steady-state errors Lag Compensation

(dist from p to s0 ) (dist from z to s0 )

EE 3CL4, 6 14 / 50 Tim Davidson Compensators Lead compensation

RL design: Basic procedure

Cascade compensation and steady-state errors Lag Compensation

EE 3CL4, 6 15 / 50 Tim Davidson Compensators Lead compensation

Lead Comp. example

Cascade compensation and steady-state errors Lag Compensation

EE 3CL4, 6 16 / 50 Tim Davidson Compensators Lead compensation

Attempt prop. control

Cascade compensation and steady-state errors Lag Compensation

Sketch root locus of

EE 3CL4, 6 17 / 50 Tim Davidson Compensators Lead compensation

Prop. control, step response

Cascade compensation and steady-state errors Lag Compensation

EE 3CL4, 6 18 / 50 Tim Davidson Compensators Lead compensation

Lead compensated design

Cascade compensation and steady-state errors Lag Compensation

EE 3CL4, 6 19 / 50 Tim Davidson Compensators Lead compensation

Lead Comp. example

Cascade compensation and steady-state errors Lag Compensation

EE 3CL4, 6 20 / 50 Tim Davidson Compensators Lead compensation

Lead Comp. example