Chapter 3

3.1. (a)
x1 x2 x3 f

0 0 0 0 1 1 1 1
(b)

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 1 0 1 0 0 1

#transistors = NOT gates 2 + AND gates 8 + OR gates = 3 2 + 4 8 + 1 10 = 48

3.2. (a) In problem 3.1 the canonical SOP for f is f = x 1 x 2 x3 + x 1 x2 x 3 + x 1 x 2 x3 + x 1 x2 x3 This expression is equivalent to f in Figure P3.2, as derived below.
x1 x2 x2 x3 + x2 x3

x3

x3

x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3

x2 x3 + x2 x3

(b) Assuming the multiplexers are implemented using transmission gates #transistors = NOT gates 2 + MUXes 6 = 1 2 + 3 6 = 20

3-1

3.3. (a) A SOP expression for f in Figure P3.3 is: f = (x1 x2 ) x3 = (x1 x2 )x3 + (x1 x2 )x3 = x 1 x 2 x3 + x 1 x2 x 3 + x 1 x 2 x3 + x 1 x2 x3 which is equivalent to the expression derived in problem 3.2. (b) Assuming the XOR gates are implemented as shown in Figure 3.61b #transistors = XOR gates 8 = 2 8 = 16

3.4. Using the circuit

The number of transistors needed is 16. 3.5. Using the circuit

The number of transistors needed is 20. 3.6. (a)

x1 x2 x3 f

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 1 1 1 0 0 0

3-2

(b) The canonical SOP expression is f = x 1 x 2 x3 + x 1 x2 x3 + x 1 x2 x 3 + x 1 x2 x3 + x 1 x2 x 3 The number of transistors required using only AND, OR, and NOT gates is #transistors = NOT gates 2 + AND gates 8 + OR gates 12 = 3 2 + 5 8 + 1 12 = 58

3.7. (a)

x1 x2 x3 x4

x1 x2 x3 x4

0 0 0 0 0 0 0 0
(b)

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 0 0 0 1 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 0 0 0 0 0 0 0

= x 1 x2 x 3 x 4 + x 1 x2 x3 x 4 + x 1 x 2 x3 x4 = x 1 x3 x 4 + x 2 x 3 x4

The number of transistors required using only AND, OR, and NOT gates is #transistors = NOT gates 2 + AND gates 8 + OR gates 4 = 4 2 + 2 8 + 1 4 = 28

3.8.
VDD

Vx Vx Vx

3 2

Vf

3-3

3.9.
Vx Vx
3

Vf

Vx Vx

3.10. Minimum SOP expression for f is f = x 2 x 3 + x 1 x 3 + x 2 x 4 + x 1 x4 = (x1 + x2 )(x3 + x4 )

which leads to the circuit

VDD

Vf Vx Vx Vx Vx

3.11. Minimum SOP expression for f is f = x 4 + x1 x 2 x 3

which leads to the circuit

3-4

VDD

Vf Vx Vx Vx Vx
4

3.12.
VDD VDD

Vf Vx Vy

Vz

3-5

3.13.
VDD VDD

Vy Vx Vz

Vy

Vz

Vf Vz Vy Vy

Vx

Vz

3.14. (a) Since VDS VGS VT the NMOS transistor is operating in the saturation region: 1 W k (VGS VT )2 2 nL A = 10 2 5 (5 V 1 V)2 = 800 A V VT , thus the NMOS transistor is operating in the triode region: ID =

(b) In this case VDS < VGS ID

= kn

1 2 W (VGS VT )VDS VDS L 2 1 A = 20 2 5 (5 V 1 V) 0.2 V (0.2 V)2 = 78 A V 2 1 W k (VGS VT )2 2 pL A = 5 2 5 (5 V + 1 V)2 = 400 A V VT , thus the PMOS transistor is operating in the triode region: ID =

3.15. (a) Since VDS VGS VT the PMOS transistor is operating in the saturation region:

(b) In this case VDS > VGS ID = kp

W 1 2 (VGS VT )VDS VDS L 2 1 A = 10 2 5 (5 V + 1 V) (0.2) V (0.2 V)2 = 39 A V 2 3-6

3.16. RDS = 1/ kn W (VGS VT ) L mA = 1/ 0.020 2 10 (5 V 1 V) = 1.25 k V

3.17. RDS = 1/ kn W (VGS VT ) L mA = 1/ 0.040 2 10 (3.3 V 0.66 V) = 947 V

3.18. Since VDS < (VGS VT ), the PMOS transistor is operating in the saturation region: ISD 1 W k (VGS VT )2 2 pL A = 50 2 (5 V + 1 V)2 = 800 A V =

Hence the value of RDS is RDS = VDS /IDS = 4.8 V/800 A = 6 k 3.19. Since VDS < (VGS VT ), the PMOS transistor is operating in the saturation region: ISD = 1 W k (VGS VT )2 2 pL A = 80 2 (3.3 V + 0.66 V)2 = 558 A V

Hence the value of RDS is RDS = VDS /IDS = 3.2 V/558 A = 5.7 k 3.20. The low output voltage of the pseudo-NMOS inverter can be obtained by setting V x = VDD and evaluating the voltage Vf . First we assume that the NMOS transistor is operating in the triode region while the PMOS is operating in the saturation region. For simplicity we will assume that the magnitude of the threshold voltages for both the NMOS and PMOS transistors are equal, so that VT = VT N = VT P The current owing through the PMOS transistor is ID = = = 1 Wp k (VDD VT P )2 2 p Lp 1 kp (VDD VT P )2 2 1 kp (VDD VT )2 2 3-7

Similarly, the current going through the NMOS transistor is ID 1 Wn (Vx VT N )Vf Vf2 Ln 2 1 = kn (Vx VT N )Vf Vf2 2 1 = kn (VDD VT )Vf Vf2 2 = kn

Since there is only one path for current to ow, we can equate the currents owing through the NMOS and PMOS transistors and solve for the voltage Vf . 1 kp (VDD VT )2 = 2kn (VDD VT )Vf Vf2 2 kp (VDD VT )2 2kn (VDD VT )Vf + kn Vf2 = 0 This quadratic equation can be solved using the standard formula, with the parameters a = kn , b = 2kn (VDD VT ), c = kp (VDD VT )2 which gives Vf = b 2a b2 c 2 4a a (VDD VT )2 1 kp kn kp (VDD VT )2 kn

= (VDD VT )

= (VDD VT ) 1

Only one of these two solutions is valid, because we started with the assumption that the NMOS transistor is in the triode region while the PMOS is in the saturation region. Thus Vf = (VDD VT ) 1 3.21. (a) Istat 1 Wp k (VDD VT )2 2 p Lp A = 12 2 1 (5 V 1 V)2 = 192 A V = 1 kp kn

(b) RDS = 1/ kn Wn (VGS VT ) Ln mA = 1/ 0.060 2 4 (5 V 1 V) = 1.04 k V

(c) Using the expression derived in problem 3.20 Wp = 24 Lp Wn kn = k n = 240 Ln kp = k p 3-8 A V2 A V2

VOL = Vf

= (5 V 1 V) 1 = 0.21 V

24 240

(d) PD = Istat VDD = 192 A 5 V = 960 W 1mW

(e) RSD P = VSD /ISD = (VDD Vf )/Istat = (5 V 0.21 V)/0.192 mA = 24.9 k (f ) The low-to-high propagation delay is 1.7C
Wp VDD k p Lp

tpLH

= =

1.7 70 fF = 0.99 ns A 24 V2 1 5 V

The high-to-low propagation delay is 1.7C

n kn W Ln VDD

tpHL

= =

60

1.7 70 fF = 0.1 ns A V2 4 5 V

3.22. (a) Istat = 1 Wp k (VDD VT )2 2 p Lp A = 48 2 1 (5 V 1 V)2 = 768 A V

(b) RDS = 1/ kn Wn (VGS VT ) Ln mA = 1/ 0.060 2 4 (5 V 1 V) = 1.04 k V

(c) Using the expression derived in problem 3.20 kp = k p A A Wn Wp = 96 2 kn = kn = 240 2 Lp V Ln V

3-9

VOL = Vf

= (5 V 1 V) 1 = 0.90 V

96 240

(d) PD = Istat VDD = 768 A 5 V = 3840 W 3.8mW

(e) RSD P = VSD /ISD = (VDD Vf )/Istat = (5 V 0.90 V)/0.768 mA = 5.34 k (f ) The low-to-high propagation delay is tpLH = = The high-to-low propagation delay is tpHL = = 3.23. (a) Istat = 1 Wp k (VDD VT )2 2 p Lp A = 12 2 1 (5 V 1 V)2 = 192 A V 1.7C n kn W Ln VDD 1.7 70 fF = 0.1 ns A 60 V2 4 5 V 1.7C
Wp VDD k p Lp

1.7 70 fF = 0.25 ns A 96 V2 1 5 V

(b) The two NMOS transistors in series can be considered equivalent to a single transistor with twice the length. Thus RDS = 1/ kn Wn (VGS VT ) Ln mA = 1/ 0.060 2 2 (5 V 1 V) = 2.08 k V

(c) Using the expression derived in problem 3.20 Wp = 24 Lp Wn kn = k n = 120 Ln kp = k p 3-10 A V2 A V2

VOL = Vf

= (5 V 1 V) 1 = 0.42 V

24 120

(d) PD = Istat VDD = 192 A 5 V = 960 W 1mW (e) RSD P = VSD /ISD = (VDD Vf )/Istat = (5 V 0.42 V)/0.192 mA = 23.9 k (f ) The low-to-high propagation delay is 1.7C
Wp k p Lp VDD

tpLH

= =

24

1.7 70 fF = 0.99 ns A V2 1 5 V

The high-to-low propagation delay is 1.7C

n kn W Ln VDD

tpHL

= =

1.7 70 fF = 0.2 ns A 60 V2 2 5 V

3.24. (a) Istat = 1 Wp k (VDD VT )2 2 p Lp A = 12 2 1 (5 V 1 V)2 = 192 A V

(b) The two NMOS transistors in parallel can be considered equivalent to a single transistor with twice the width. Thus RDS = 1/ kn Wn (VGS VT ) Ln mA = 1/ 0.060 2 8 (5 V 1 V) = 520 V

(c) Using the expression derived in problem 3.20 Wp = 24 Lp Wn kn = k n = 480 Ln kp = k p 3-11 A V2 A V2

VOL = Vf

= (5 V 1 V) 1 = 0.10 V

24 480

(d) PD = Istat VDD = 192 A 5 V = 960 W 1mW

(e) RSD P = VSD /ISD = (VDD Vf )/Istat = (5 V 0.10 V)/0.192 mA = 25.5 k (f ) The low-to-high propagation delay is tpLH = = The high-to-low propagation delay is 1.7C n kn W Ln VDD 1.7 70 fF = 0.05 ns A 60 V2 8 5 V 1.7C
Wp k p Lp VDD

1.7 70 fF = 0.99 ns A 24 V2 1 5 V

tpHL

= =

3.25. (a) NM H = VOH VIH = 0.5 V NM L = VIL VOL = 0.7 V (b) VOL = 8 0.1 V = 0.8 V NM L = 1 V 0.8 V = 0.2 V 3.26. Under steady-state conditions, for an n-input CMOS NAND gate the voltage levels V OL and VOH are 0 V and VDD , respectively. No current ows in a CMOS gate in the steady-state. Thus there can be no voltage drop across any of the transistors. 3.27. (a) PN OT (b) Ptotal = 0.2 250, 000 281 W = 14 W 3-12
gate

= f CV 2 = 75 MHz 150 fF (5 V)2 = 281 W

3.28. (a) PN OT
gate

= f CV 2 = 125 MHz 120 fF (3.3 V)2 = 163 W

(b) Ptotal = 0.2 250, 000 163 W = 8.2 W 3.29. (a) The high-to-low propagation delay is tpHL = 1.7C
n kn W Ln VDD

1.7 150 fF = 0.255 ns A 20 V2 10 5 V

(b) The low-to-high propagation delay is tpLH = 1.7C

Wp k p Lp VDD

A V2

1.7 150 fF = 0.638 ns 10 5 V

(c) For equivalent high-to-low and low-to-high delays tpHL 1.7C n kn W L n VD D Wp Lp = tpLH 1.7C = Wp k p L p VD D = = 3.30. (a) The high-to-low propagation delay is tpHL = 1.7C 1.7 150 fF = 0.193 ns = A n kn W V 40 V2 10 3.3 V Ln DD
kn kp W n

Ln 12.5 m 0.5 m

(b) The low-to-high propagation delay is tpLH = 1.7C

Wp VDD k p Lp

1.7 150 fF = 0.483 ns 10 3.3 V 16

A V2

(c) For equivalent high-to-low and low-to-high delays tpHL 1.7C n kn W L n VD D Wp Lp = tpLH 1.7C = Wp k p L p VD D = =
kn kp W n

Ln 8.75 m 0.35 m

3-13

3.31. The two PMOS transistors in a CMOS NAND gate are connected in parallel. The worst case current to drive the output high happens when only one of these transistors is turned ON. Thus each transistor has to have Wp = 4. the same dimensions as the PMOS transistor in the inverter, namely Lp
n The two NMOS transistors are connected in series. If each one had the ratio W Ln , then the two transistors Wn could be thought of as one equivalent transistor with a 2 Ln ratio. Thus each NMOS transistor must have Wn twice the width of that in the inverter, namely Ln = 4.

3.32. The two NMOS transistors in a CMOS NOR gate are connected in parallel. The worst case current to drive the output low happens when only one of these transistors is turned ON. Thus each transistor has to have n the same dimensions as the NMOS transistor in the inverter, namely W Ln = 2. The two PMOS transistors are connected in series. If each of these transistors had the ratio two transistors could be thought of as one transistor with a made twice as wide as that in the inverter, namely
Wn Ln Wp 2Lp Wp Lp ,

then the

ratio. Thus each PMOS transistor must be

= 8.

3.33. The worst case path in the PMOS network contains two transistors in series. Thus each PMOS transistor must be twice as wide the transistors in the inverter. The worst case path in the NMOS network also contains two transistors in series. Similarly, each NMOS transistor must be twice as wide as those in the inverter. 3.34. The worst case PMOS path contains three transistors in series so each transistor must be three times as wide as the PMOS transistors in the inverter. The worst case NMOS path contains two transistors in series. Thus the NMOS transistors must be two times as wide. 3.35. (a) The current owing through the inverter is equal to the current owing through the PMOS transistor. We shall assume that the PMOS transistor is operating in the saturation region. Istat = 1 Wp k (VGS VT p )2 2 p Lp A = 120 2 ((3.5 V 5 V) + 1 V)2 = 30 A V

(b) The current owing through the NMOS transistor is equal to the static current I stat . Assume that the NMOS transistor is operating in the triode region. Istat 30 A 1 2 Wn (VGS VT n )VDS VDS Ln 2 1 A = 240 2 2.5 V Vf Vf2 V 2 = kn

1 = 20Vf 4Vf2 Solving this quadratic equation yields Vf = 0.05 V. Note that the output voltage Vf satises the assumption that the PMOS transistor is operating in the saturation region while the NMOS transistor is operating in the triode region. (c) The static power dissipated in the inverter is PS = Istat VDD = 30 A 5 V = 150 W (d) The static power dissipated by 250,000 inverters. 250, 000 Ps = 37.5 W

3-14

3.36.
x1 x2 x3 NOR plane VDD VDD

P1 P2 P3 P4

NOR plane

f1

f2

3.37.
x1 x2 x3 NOR plane VDD VDD

P1 P2 P3 P4

NOR plane

f1

f2

3-15

3.38.
x1 x2 x3 NOR plane VDD VDD

S1 S2 S3 S4

NOR plane

f1

f2

3.39.
x1 x2 x3 NOR plane VDD VDD

S1 S2 S3 S4

NOR plane

f1

f2

3-16

3.40.
VDD

x1

x2

x3

NOR plane VDD

VDD

VDD

VDD

NOR plane

f1

3.41.
VDD

x1

x2

x3

NOR plane VDD

VDD

VDD

VDD

NOR plane

f1

3-17

3.42. f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 3.43. f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 f2 = m0 = m3 = m5 = m6 = m0 + m3 = m0 + m5 = m0 + m6 = m3 + m4 = m3 + m6 = m5 + m6 = m0 + m3 + m5 = m0 + m3 + m6 = m0 + m5 + m6 = m3 + m5 + m6 = m0 + m3 + m5 + m6 = m1 = m2 = m4 = m7 = m1 + m2 = m1 + m4 = m1 + m7 = m2 + m4 = m2 + m7 = m4 + m7 = m1 + m2 + m4 = m1 + m2 + m7 = m1 + m4 + m7 = m2 + m4 + m7 = m1 + m2 + m4 + m7

3-18

3.44.
x1 x2

0 0 1 0 0 0 0 1 0 0 1 0

x1 x2

x1 x3

0 1 1 1
x1 x3

x1 x2 + x1 x3

0 1 1 1

x1 x2 + x1 x3 + x2 x3

x2 x3

x2 x3

3.45. The canonical SOP for f is f = x 1 x2 x3 + x 1 x2 x3 + x 1 x 2 x 3 + x 1 x2 x3 + x 1 x2 x3 This expression can be manipulated into f = x 1 x2 + x 1 x3 + x 1 x2 = x 2 + x 1 x3 The circuit is
x1 x3

0 0 1 0

x1 x3

x2

0 1 1 1

x2 + x1 x3

3.46. The canonical SOP for f is f = x 1 x2 x4 + x 2 x3 x 4 + x 1 x2 x3 This expression can be manipulated into f = x2 (x1 x4 + x3 x4 ) + x2 (x1 x3 ) Using functional decomposition we have f = x 2 f1 + x2 f2 where f1 f2 = x 1 x4 + x 3 x 4 = x1 x 3 3-19

The circuit is
x1 x3 x4 x1 x4 + x3 x4

x1 x2 x4 + x2 x3 x4 + x1 x2 x3

0 x1 x3 x2 x1 x3

3.47. The canonical SOP for f is f = x 1 x2 x4 + x 2 x3 x 4 + x 1 x2 x3 This expression can be manipulated into f = x2 (x1 x4 + x3 x4 ) + x2 (x1 x3 ) Using functional decomposition we have f = x 2 f1 + x2 f2 where f1 f2 = x 1 x4 + x 3 x 4 = x1 x 3

The function f1 requires one 2-LUT, while f2 requires three 2-LUTs. We then need three additional 3-LUTs to realize f , as illustrated in the circuit
x1 x4 x1 x4 x1 x4 + x3 x4 x1 x2 x4 + x3 x2 x4 x3 x4 x2 x1 x3 x1 x3 x1 x2 x3 x3 x4 x1 x2 x4 + x2 x3 x4 + x1 x2 x3

3.48. g = x 2 x3 h = x1 j k = x2 = x3

3-20

3.49. (a)

x2 0

x1

x1 0 + x1 x2

x3 x1 x2 + x3 1 = x1 x2 + x3

x3

(b)

x3

x3 0 + x3 ( x1 + x2 ) = x1 x3 + x2 x3

x1 x2 + x1 1 = x1 + x2

x2 1

x1

3.50. (a)

x1 x2 1 1 x3 1 1

x1 x2

x1 x2 x3 = x1 x2 + x3

x3

3-21

(b)
x1 x2 x4 x1 x2 x3 x4 1 1 x4 x2 x3 x4 x1 x2 x4 x1 x2 x3 x4 = x1 x2 x4 + x1 + x2 x3 x4 x1 x2 x4

3.51.

module prob2 51 (x1, x2, x3, x4, f); input x1, x2, x3, x4; output f; assign f = (x2 & x3 & x4) | (x1 & x2 & x4) | (x1 & x2 & x3) | (x1 & x2 & x3); endmodule

3.52.

module prob2 52 (x1, x2, x3, x4, f); input x1, x2, x3, x4; output f; assign f = (x1 | x2 | x4) & (x2 | x3 | x4) & (x1 | x3 | x4) & (x1 | x3 | x4); endmodule

3.53.

module prob2 53 (x1, x2, x3, x4, x5, x6, x7, f); input x1, x2, x3, x4, x5, x6, x7; output f; assign f = (x1 & x3 & x6) | (x1 & x4 & x5 & x6) | (x2 & x3 & x7) | (x2 & x4 & x5 & x7); endmodule

3.54. The circuit in Figure P3.10 is a two-input XOR gate. Since NMOS transistors are used only to pass logic 0 and PMOS transistors are used only to pass logic 1, the circuit does nor suffer from any major drawbacks. 3.55. The circuit in Figure P3.11 is a two-input XOR gate. This circuit has two drawbacks: when both inputs are 0 the PMOS transistor must drive f to 0, resulting in f = VT volts. Also, when x1 = 1 and x2 = 0, the NMOS transistor must drive the output high, resulting in f = VDD VT .

3-22