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MOSFETs

A. Godoy

*

, J.A. L opez-Villanueva, J.A. Jimenez-Tejada, A. Palma, F. Gamiz

Departamento de Electr onica, Facultad de Ciencias, Universidad de Granada, 18071 Granada, Spain

Received 14 September 2000; received in revised form 24 January 2001; accepted 25 January 2001

Abstract

A new approach to calculate the subthreshold swing of short channel bulk and silicon-on-insulator metal oxide

semiconductor eld eect transistors is presented. The procedure utilizes a channel-potential expression appropriate for

submicron dimensions. The nal result is similar to that used for long channels except for a factor k which represents

the short channel eects. Comparison with dierent published results reveals excellent quantitative agreement. 2001

Elsevier Science Ltd. All rights reserved.

1. Introduction

The gain in integrability and speed is the main reason

for the continuous miniaturization of metal oxide

semiconductor eld eect transistors (MOSFETs). Bulk

CMOS remains as the main technology for submicron

gate ULSI systems. However, thin-lm silicon-on-insu-

lator (SOI) MOSFETs are of great interest due to im-

proved isolation and reduced parasitic capacitances

compared to bulk silicon technology.

As device dimensions are reduced, the so-called short

channel eects (SCE) become increasingly important

due to the penetration of the lateral eld into the

channel region. From these eects, degradation of

threshold voltage and the increase in subthreshold

swing, S, are the most signicant [13].

Much work has been focused on the study of

threshold voltage and dierent approaches have been

used to make an analytical model of the behavior of this

parameter [46]. However, despite its importance, few

articles have dealt with the modeling of S, a key factor

for transistor performance. Deterioration of the sub-

threshold behavior increases the o-current level and

standby power dissipation and reduces noise immunity

[2]. Such characteristics become particularly important

for low voltage portable electronics [7]. Two-dimen-

sional device simulators are usually used, though a

simple analytical model would be very valuable to un-

derstand the device physics.

Here, a short channel subthreshold swing model is

derived for three dierent structures: bulk, thin lm fully

depleted and double-gate (DG) SOI MOSFETs. The

nal expression is the same for the three devices. The

only dierence is a factor l, a natural length scale in-

troduced as a scaling parameter.

With this model, the accelerated S increase observed

in the very short channel range can be accurately pre-

dicted. Because of its simple functional form and com-

putational eciency, this model is suitable for the

guidelines of technology design and can be used in cir-

cuit simulation.

2. Analytical model

In this section, we provide the analytic framework

necessary to develop a subthreshold swing model for a

conventional MOSFET. After that, fully depleted and

DG SOI structures are analyzed. For all these devices a

negligible interface state density has been assumed.

Solid-State Electronics 45 (2001) 391397

*

Corresponding author. Tel.: +34-58-243230; fax: +34-58-

243227.

E-mail address: agodoy@ugr.es (A. Godoy).

0038-1101/01/$ - see front matter 2001 Elsevier Science Ltd. All rights reserved.

PII: S0038- 1101( 01) 00060- 0

2.1. Bulk MOSFETs

The subthreshold swing, S, is dened as the change in

gate bias required to change the subthreshold drain

current by one decade, and is given by:

S =

oV

g

o log I

D

; (1)

where V

g

is the gate voltage and I

D

the drain current.

The key point in this expression lies in the fact that V

g

and I

D

are related through the minimum of the surface

potential, w

S min

, since drain current at subthreshold

operation is dominated by a diusion process whereby

the current may be computed in terms of the probability

of a source electron surmounting an energy barrier. The

height of this barrier is qw

S min

, which is a function of the

applied gate voltage and where q is the electron charge.

Thus, I

D

is proportional to exp(w

S min

=V

T

) where V

T

is

the thermal voltage. Therefore, it is more convenient to

represent S as:

S =

oV

g

ow

S min

ow

S min

o ln I

D

ln(10): (2)

At this point, the calculation of the second derivative

in Eq. (2) is straightforward.

For a long channel MOSFET in the subthreshold

regime, if the mobile channel charge is neglected, it is

possible to state:

V

g

V

FB

= w

SL

Q

dep

C

ox

; (3)

where V

FB

is the at band, w

SL

is the long channel sur-

face potential, Q

dep

is the depletion charge and C

ox

is the

oxide capacitance. As for a long channel device the

surface potential is constant along the channel, it follows

that:

oV

g

ow

S min

= 1

C

dep

C

ox

; (4)

where C

dep

is the depletion capacitance. Hence, we can

conclude that for a long channel transistor:

S = 1

C

dep

C

ox

V

T

ln(10): (5)

Nevertheless, we are mainly interested in including

the SCEs. Since subthreshold conduction is governed by

the potential distribution, it is necessary to consider an

analytical expression that is appropriate for such di-

mensions. A widely employed model for the electrical

potential along the channel is given by [5]:

w(y) = w

SL

V

bi

( V

ds

w

SL

)

sinh

y

l

sinh

L

l

V

bi

( w

SL

)

sinh

Ly

l

sinh

L

l

; (6)

where y is the parallel coordinate to the SiSiO

2

inter-

face, V

bi

is the built-in potential between the source

substrate and drainsubstrate junctions, V

ds

is the

drainsource voltage, L is the channel length and l is

the characteristic length dened as:

l =

Si

t

ox

X

dep

ox

r

; (7)

where

Si

and

ox

are the permittivity of Si and SiO

2

respectively, t

ox

is the oxide thickness and X

dep

is the

depletion layer thickness. In order to simplify calcula-

tions, X

dep

is assumed to be a constant for which the

surface potential is set at its average value at sub-

threshold operation: 1:5/

B

(= 1:5V

T

ln(N

sub

=n

i

)) with

N

sub

representing the substrate doping concentration and

n

i

the intrinsic carrier concentration. In order to take

into account the eect of the substrate voltage, 1:5/

B

should be substituted by (1:5/

B

V

sub

) in the X

dep

cal-

culation which also modies the Q

dep

, C

dep

and l values.

The dependence of the surface potential, (6), on V

g

is

implicit in w

SL

, which is given by Eq. (3). Expression (6)

predicts a large variation in potential along the channel

for submicron devices. The injection of source electrons

into the channel and therefore the device current is de-

termined by the minimum value of the potential. This

minimum is located at y

0

and can be expressed as [9]:

y

0

=

l

2

log

V

bi

w

SL

( ) exp

L

l

V

bi

w

SL

V

ds

( )

V

bi

w

SL

V

ds

( ) V

bi

w

SL

( ) exp

L

l

4 5

:

(8)

Now, in the calculation of S we make use of the

identity:

ow

S min

oV

g

=

ow(y)

oV

g

!

y=y

0

(9)

which can be obtained deriving Eqs. (6) and (3):

ow(y)

oV

g

!

y=y

0

=

1

1

k

C

dep

C

ox

; (10)

where,

k = 1

sinh

y

0

l

sinh

Ly

0

l

sinh

L

l

: (11)

392 A. Godoy et al. / Solid-State Electronics 45 (2001) 391397

Finally, substituting Eq. (8) in Eq. (11) we obtain:

k = 1

2 V

bi

w

SL

( ) V

ds

( )tgh

L

2l

4 V

bi

w

SL

( ) V

bi

w

SL

V

ds

( ) sinh

2

L

2l

V

2

ds

q :

(12)

Thus, we have obtained a new expression for the

subthreshold swing which resembles the long channel

one and where k is the only dierence:

S =

1

k

C

dep

C

ox

V

T

ln(10): (13)

Therefore, the inuence of the SCE on the sub-

threshold swing is concentrated on the k factor and due

to its simplicity, it is possible to carry out a fast esti-

mation of its importance.

Further simplication is possible if the drain voltage

is small (V

ds

V

bi

w

SL

), when expression (12) reduces

to:

k 1

1

cosh

L

2l

: (14)

Moreover, if L 2l:

k 1 2 exp

L

2l

: (15)

2.2. Fully-depleted SOI MOSFETs

In this structure, the substrate has been replaced by a

thick buried oxide to dramatically reduce the junction

capacitance and a silicon lm of thickness t

Si

is grown

over the oxide. To obtain improved short-channel per-

formance in SOI over conventional MOS transistors, t

Si

must be smaller than the bulk depletion depth X

dep

,

originating a fully-depleted silicon lm.

As we are dealing with a dierent structure it is

necessary to use dierent boundary conditions which

will inuence the potential distributions. However, an

expression similar to Eq. (6) can be used to reproduce

the lateral potential distribution from source to drain.

Yan et al. [8] assumed that the electric eld at the

SiSiO

2

buried interface is approximately zero. This

is equivalent to considering an innite buried oxide

thickness (t

box

). A more general calculation was devel-

oped by Banna et al. [10] since an arbitrary t

box

is in-

cluded in their calculations. Thus, dierent expressions

for the natural length scale are found in both papers.

However, since t

box

is usually much thicker than the

front gate oxide t

ox

both expressions lead to the same

results, as proved in our numerical calculations.There-

fore, we nally write:

l =

Si

t

ox

t

Si

ox

r

: (16)

This expression is equivalent to that employed for

bulk MOSFETs (7) where X

dep

is replaced by t

Si

. For

thin lm transistors, since the silicon lm is fully de-

pleted we have to modify Eq. (3) to state that:

V

g

V

FB

= w

SL

qN

sub

t

Si

C

ox

: (17)

There is no variation of the depletion charge with the

front gate voltage and, as a consequence, using Eqs. (6)

and (17):

oV

g

ow

S min

=

1

k

: (18)

Therefore, we are able to write:

S =

1

k

V

T

ln(10) (19)

where k is similar to expression (12) using the appro-

priate parameters for the device under consideration.

Then, for a long channel transistor, the inverse sub-

threshold slope should reach its theoretical lower limit of

60 mV/dec. However, higher values of S have been

found. To explain subthreshold swing values higher than

60 mV/dec for long channels it must be considered

[11,12] that S is modied by parameters such as the

buried oxide thickness, which is not included in our

model since the former derivation did not account for

the capacitive coupling between the front and back in-

terfaces. In order to consider this eect, it is possible to

use a more elaborate model [11,12]:

oV

g

ow

SL

= 1

C

box

C

Si

C

ox

C

Si

C

box

( )

(20)

where C

Si

(=

Si

=t

Si

) is the silicon lm capacitance and

C

box

(=

ox

=t

box

) is the back gate oxide capacitance. This

expression should be multiplied by Eq. (19) to take into

account the correction factor. Nevertheless, our nu-

merical calculations have demonstrated that the eect of

Eq. (20) is negligible when SCE becomes important,

namely, when factor k 1.

2.3. Double-gate SOI MOSFETs

In this structure, the buried oxide is replaced by a

gate oxide and we will further consider the symmetrical

device for which equal voltages are applied at both front

and back gates. For this device:

V

g

V

FB

= w

SL

qN

sub

C

ox

t

Si

2

(21)

and using Eqs. (6) and (21):

A. Godoy et al. / Solid-State Electronics 45 (2001) 391397 393

oV

g

ow

S min

=

1

k

: (22)

Again, expression (6) can be used for the surface

potential where the characteristic length is now dened

as:

l =

Si

t

ox

ox

t

Si

2

r

; (23)

where the silicon lm thickness is halved. Therefore, for

the same device parameters this structure would have a

better subthreshold behavior than the fully depleted one

[8]. Again, we are able to write:

S =

1

k

V

T

ln(10) (24)

with k similar to Eq. (12) using the expressions appro-

priate for double-gate SOI MOSFETs.

3. Validation of the model

In this section, the former theory is compared with

experimental and numerical results presented by dier-

ent authors. Firstly, we compare the results obtained

with expression (13) for a conventional bulk MOSFET

with the data presented by Biesemans et al. [13]. Fig. 1

shows the subthreshold swing versus the substrate

doping concentration, N

sub

. Solid squares represent the

data obtained through Biesemans's model while the

solid line depicts expression (13). For high substrate

doping, S increases because of the increase in the de-

pletion capacitance C

dep

. In the low N

sub

region, the SCE

originate an increase in S since in this situation the lat-

eral eld is unscreened by the dopants. Both models

show the same behavior as a function of N

sub

, although

Eq. (13) is considerably easier to calculate and therefore

computationally more ecient and useful for computer

simulations.

We also used a two dimensional device simulator,

MEDICI [14], in order to study the variation of S with

the channel length. In Fig. 2, solid squares represent the

data obtained from MEDICI, while the solid line is

obtained from our analytical model. As can be seen, S

increases as the channel length is reduced and a very

good agreement is achieved for the whole range of

lengths employed. As can be deduced from the general

denition of S in Eq. (2), this parameter evaluates the

sensitivity of the surface potential to gate voltage vari-

ations. Thus, the reduction of channel length and hence

the appearance of SCE reduces this sensitivity, provo-

king an increase in S. In this gure, the dashed line rep-

resents the results obtained when approximation (15) is

employed. As can be observed, Eq. (15) is not appro-

priate for very short channel lengths where L becomes

comparable with 2l and the complete expression (12) is

necessary to reproduce the 2D simulation successfully.

It is important to note that when channel lengths

approximate 2l, and high drainsource voltages are

applied, it is possible to get negative S values from Eq.

(13). Then, for the correct use of the model, it is neces-

sary to ensure that L > 2l. This phenomenon could be

Fig. 1. Comparison between results from Ref. [13] and our

model, for a bulk MOS transistor with t

ox

= 7:5 nm, L =

0:25 lm and V

ds

= 0:1 V.

Fig. 2. Comparison between 2D numerical simulation and our

model for a bulk conventional MOS transistor with t

ox

=

10 nm, N

sub

= 10

17

cm

3

and V

ds

= 0:1 V. Solid line corre-

sponds to subthreshold swing calculated for k equal to ex-

pression (12) and dashed line is for k equal to expression (15).

394 A. Godoy et al. / Solid-State Electronics 45 (2001) 391397

considered an extreme case of SCE where the behavior

of the device is not appropriate.

To conrm the validity of our analytical model for

SOI devices, we rst used the results presented by

Horiuchi et al. [15]. Their data are shown in Fig. 3 as

solid squares, while the solid line represents our model.

As can be seen from this gure, expression (19) repro-

duces satisfactorily channel lengths as short as 50 nm.

The S roll-up when higher drainsource voltages are

applied is understood as the penetration of the lateral

drain eld into the channel region. The dierences in S

values for long-channel devices could be caused by the

presence of traps at the SiSiO

2

interfaces neglected in

our model.

Moreover, as shown in Fig. 4, we have successfully

reproduced the experimental results presented by Biese-

mans [13] for an SOI device with N

sub

= 3 10

17

cm

3

,

t

ox

= 7 nm, t

Si

= 30 nm, t

box

= 80 nm and V

ds

= 0:1 V.

Fig. 5 presents the dependence of the subthreshold

swing on the silicon lm thickness in a double gate SOI

MOSFET with L = 50 nm, N

sub

= 5 10

17

cm

3

and

V

ds

= 50 mV. Solid squares represent the data obtained

Fig. 4. Comparison between results from Ref. [13] (j) and our

model () for a fully-depleted SOI MOSFET with t

ox

= 7 nm,

t

Si

= 30 nm, t

box

= 80 nm, N

sub

= 3 10

17

cm

3

and V

ds

=

0:1 V.

Fig. 5. Subthreshold swing as a function of the silicon lm

thickness in a double-gate SOI MOSFETs with t

ox

= 3 nm,

L = 50 nm, V

ds

= 50 mV and N

sub

= 5 10

17

cm

3

. Dashed line

shows results from Ref. [16] and solid line our model.

Fig. 3. Comparison between results from Ref. [15] (j) and our model () for a thin lm SOI device with t

ox

= 5 nm, t

Si

= 50 nm,

t

box

= 500 nm and N

sub

= 4 10

17

cm

3

. (a) V

ds

= 0:1 V and (b) V

ds

= 2 V.

A. Godoy et al. / Solid-State Electronics 45 (2001) 391397 395

by Rauly et al. [16] through numerical simulation, while

the solid line shows our model. The minimum silicon

lm thickness used by these authors is 10 nm, which

corresponds to the limit of validity of classical models in

single- and double-gate SOI MOSFETs [16]. Below this

thickness, quantum eects should be taken into account.

Thinning the silicon lm enhances the controllability of

the gate potential on the channel region, resulting in a

reduction in SCE and therefore a decrease in the sub-

threshold swing, as shown in the gure.

Furthermore, it should be stressed that the sensitivity

of S to variations of the silicon lm thickness is lower in

double-gate than in single-gate SOI MOSFETs. To

show this behavior explicitly, we have represented in

Fig. 6 dS=dt

Si

where the dashed line represents a fully

depleted and the solid line, a double-gate SOI transistor.

To evaluate its magnitude, we have employed expression

(15) to simplify the calculations.

Finally, we have also reproduced the numerical re-

sults presented by Suzuki et al. [17] for double-gate SOI

MOSFETs where S is represented as a function of the

channel length. In their model, SCE are expressed by

function exp(L=2l), which is similar to our simplied

expression (15) obtained when L 2l. As shown in Fig.

2, this approximation leads to inaccuracies when short

channels are considered. Moreover, in Ref. [17] a center

potential expression w

c

(y) rather than a surface one was

used to calculate S. However, at weak inversion the

dierences between the two expressions are negligible

since for a typical device with t

Si

= 200

A and N

sub

=

10

15

cm

3

the dierence is about 80 lV.

4. Conclusions

This work presents a simple and accurate analytical

model derived from fundamental device physics for

subthreshold swing of short channel bulk and SOI

MOSFETs. The expression obtained is identical to that

used for long channels except for a factor k which in-

cludes the eects of reducing the channel length. This

term, k, is easily calculated, so that the model is com-

putationally ecient and appropriate for circuit simu-

lators where simple and accurate models are required.

This model can be used for comparison of MOSFET

scaling limits in bulk and SOI technologies.

Acknowledgements

This work has been carried out within the framework

of research project PB97-0815, supported by the Spanish

Government.

References

[1] Fiegna C, Iwai H, Wada T, Saito T, Sangiorgi E, Ricco B.

Scaling the MOS transistor below 0.1 lm: methodology,

device structures, and technology requirements. IEEE

Trans Electron Dev 1994;41:941.

[2] Agrawal B, De VK, Pimbley JM, Meindl JD. Short

channel models and scaling limits of SOI and bulk

MOSFETs. IEEE J Solid State Circuits 1994;29:1225.

[3] Deshpande DR, Dutta AK. A new unied model

for submicron MOSFETs. Microelectron J 1998;29:

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[4] Viswanathan CR, Burkey BC, Lubberts G, Tredwell TJ.

Threshold voltage in short-channel MOS devices. IEEE

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[12] Wouters DJ, Colinge DJ, Maes HE. Subthreshold slope in

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