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1. The Iliac-IV system was developed at the University of Illinois in the 1960s.
2. The system was fabricated by the Burroughs Corporation in 1972.
3. The original objective was to develop a highly parallel computer with a large
number of arithmetic units to perform vector/matrix computations at the rate of
109 operations per second.
4. The system was to employ 256 PEs under the supervision of four CUs.
5. Due to cost escalation and schedule delays , the system was limited to one
quadrant with 64 PEs under control of one CU with speed approximately 200
million operations per second.
6. The Illiac-IV computer has been applied in numerical weather forecasting and in
nuclear engineering research, among many other scientific applications.
Mode-bit line
1. This line consists of one line coming from the A register of each PE in the array.
2. These lines can transmit the mode bits of the D register in the array to the
acumulator register in the CU.
B6500 host computer & I/O subsystem
1. The IIIiac-IV communicates with the outside world through an I/O subsystem , a
disk files system, and a B6500 host computer which supervises a large laser
memory(1012 bits) and the ARPA network link.
2. The B6500 manages all programmer requests for system resources. The operating
system, including compilers, assemblers, and I/O service routines, are residing in
the B6500.
3. As a total system, the IIIiac-IV array is really a special purpose back-end machine
of the B6500.
4. The ARPA(advanced research project agency) net linkage makes the IIIiac-IV
available to all members of the ARPA network.
The control unit (CU) of the IIIiac-IV array performs the following functions needed
for the execution of programs:
1. The instruction buffer and local data buffer are 64-word fast-access buffers.
2. The PLA is associatively addressed to hold current and pending instructions.
3. The LDB is a data cache with 64 bits per word.
4. It can hold 128 instructions, sufficient to hold the inner loop of many programs.
Final queueIt is used to stack the addresses and data waiting to be transmitted to the PEs.
1. PE instructions are decoded by the advanced instruction station (ADV AST) and
then transmitted via control signals to all PEs.
2. In fact, the ADV AST decodes all instructions and executes the CU instructions.
3. The ADV AST constructs the necessary address and data operands after decoding
a PE instruction.
Routing path
1. The Illiac-IV was primarily designed for matrix manipulation and differential
equations.
2. Many ARPA net users attempt to use the IIliac-IV for their own applications.
3. The main difficulties in programming the Il1iac-IV are the exploitation of
identical arithmetic computations in user programs and the proper distribution of data sets
in the PEMs to allow parallel accesses.
DO 1001=1 ,N
100 A(I)=B(I)+C(I)
The IlIiac- IV can perform the additions in the loop simultaneously by involving
all 64 PEs in synchronous lock-step fashion. The data must be allocated in the
PEMs to support parallelism in the PEs..
Example 6.1
Note that all the 64 loads in LDA, the 64 adds in ADRN, and the 64 stores in ST A are
performed in parallel in only three machine instructions.
In this case, only a subset of the 64 PEs will be involved in the parallel operations. The
same memory allocation and machine instructions as in case 1 are needed, except some
of the memory space and PEs will be masked off. The smaller the value
N compared to 64, the severer the idleness of the disabled PEs and PEMs in the array.
Case 3: N > 64 (The problem size is greater than the array size)
The memory allocation problem becomes much more complicated in this case.
The case of N = 66.
The first 64 elements of the A, B, and C arrays are stored from
locations α , α + 2, and α + 4, respectively, in all PEMs.
The two residue elements
A(65), A(66); B(65), B(66); C(65), C(66) are stored in locations α + 1, α + 3, and
α + 5, respectively, in PEMo and PEM1•
The unused memory locations are indicated by question marks.
Six machine language instructions are needed to perform the 66 load, add, and store
operations:
The two residue data items in the A, B, and C arrays require three additional Iliac
instructions. In fact, the above six instructions can be used to perform any vector addition
of dimensions 65 ≤ N ≤ 128 in Illiac-IV.