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12. Dynamic CMOS Logic

J. A. Abraham

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of Electrical and Computer Engineering The University of Texas at Austin EE 382M.7 VLSI I Fall 2011
October 10, 2011

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Dynamic Logic
Dynamic gates use a clocked pMOS pullup Two modes of precharge and mm 40 operation:60 80 evaluate 100
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The Foot Transistor

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What if pulldown network is ON during precharge?

Use series evaluation transistor to prevent ght between pMOS and nMOS transistors
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Logical Eort
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Monotonicity
Dynamic gates require monotonically mm inputs during 40 60 80 rising evaluation
00 01 11 But not 1 0 100 120

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Monotonicity Woes
mm 60 monotonically 80 falling 100 But dynamic40 gates produce outputs 120

during evaluation Illegal for one dynamic gate to drive another!

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Domino Gates
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Follow dynamic stage with inverting static gate

40 60 80 Dynamic/static pair is called domino gate Produces monotonic outputs

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Domino Optimizations
Each domino gate triggers next one, like a string of dominos toppling over mm 40 60 80 100 120 Gates evaluate sequentially, precharge in parallel Evaluation is more critical than precharge HI-skewed static stages can perform logic
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Dual-Rail Domino
Domino only40 performs noninverting functions: mm 60 80 AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem
40 Takes true and complementary inputs Produces true and complementary outputs 100 120

sig h 0 0 1 1

sig l 60 0 1 0 1 80

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Example: AND/NAND
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Given A h, A l, B h, B l
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Compute Y h = A * B, Y l = (A * B) Pulldown networks are conduction complements

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Example: XOR/XNOR
mm 40 60 transistors 80 100 120 Sometimes possible to share Sharing works well in implementations of symmetric functions See papers on relay logic published over 50 years ago 40

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Leakage
Dynamic node oats high during evaluation
Transistors are leaky (Iof f = 0) mm Dynamic40 60away over time 80 value will leak Formerly milliseconds, now nanoseconds! 100 120

Use keeper to hold dynamic node

Must be weak enough not to ght evaluation

Leakage Power! 40

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Charge Sharing
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Dynamic gates suer from charge sharing

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Vx = Vy =

Cy VDD Cx + Cy
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Lecture 12. Dynamic CMOS Logic

Secondary Precharge
Solution: add secondary precharge transistors
need to precharge mm Typically40 60 every other 80 node 100 120

Big load capacitance on Y helps as well

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Noise Sensitivity
Dynamic gates are very sensitive to noise
Inputs: VIH Vtn oating output noise mm Outputs:40 60 susceptible80 100 120

Noise sources
Capacitive crosstalk Charge sharing Power supply noise Feedthrough noise And more! Chip power supply voltage map when executing a program 60

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Alternating N & P Domino Logic

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Cascade Voltage Switch Logic (CVSL)

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Dynamic CVSL XOR Gate

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Dual-Rail Domino Full Adder Design

Very fast, but large and power hungry
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Manchester Adders
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Domino Summary
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Domino logic is attractive for high-speed circuits

1.5 2x faster than static CMOS

Many Challenges 40
Monotonicity Leakage Charge sharing Noise 60 Used in previous generation high-performance microprocessors and in some recent embedded processors

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Domino Logic in Current Designs

Domino design from Intrinsity used in 1-GHz 0.75W ARM Cortex A8 from Samsung (Intrinsity later acquired by Apple) mm 40 60 80 100 120 Fast Domino (called Fast14 NDL) gates are inserted selectively into critical speed paths, with custom SRAMs and optimized synthesized logic elsewhere Standard power saving techniques are also used 40 Domino gates are clocked by multiphase clocks A type of super-pipeline where the domino footers form the barrier for the pipeline operation
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(Source: Electronic Design Embedded, August 29, 2009)
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Intrinsity OR/NOR Implementation with N-nary Logic

2-bit function using 1-out-of-4 signals
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Ref: U. S. Patent 6066965, Method and apparatus for a N-nary Logic Circuit Using 1 of 4 Signals
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Intrinsity XOR/Equivalence Implementation

Using 1-out-of-2 signals
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Ref: U. S. Patent 6066965, Method and apparatus for a N-nary Logic Circuit Using 1 of 4 Signals
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