Practical De-embedding for Gigabit Fixtures

Ben Chia Senior Signal Integrity Consultant 5/17/2011

Topics
Why De-Embedding/Embedding? De-embedding in Time Domain De-embedding in Frequency Domain De-embedding example Compliance test examples Accuracy consideration

Terminalolgy
De-Embedding
Remove fixture effect from the measurement Example: remove probes, SMA+traces

Embedding
Add a cable to see what happen to the signal Example: test receiver sensitivity by adding a 4-inch cable between the driver and DUT

De-embedding Example

Measurement Reference Plane

6-meter cable de-embedding

Does your scope show the real waveform? `

6

Example: De-embedding Probes

More Example: DDR2 Device Fixture

DDR2

How to remove this fixture effect?

8

DDR2 Fixture De-Embedding

Scope performs de-embedding

De-Embedding Calibration
Both VNA/TDR have firmware to simplify de-embedding process
Probe de-embedding Fixture de-embedding

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TDR De-embedding Example

Calibrate with SMA standard
Short Load Connect Port 1 to SMA to measure S11

PCB trace

SMA

How to capture S11 at the package ball?

11

TDR De-embedding Example

Agilent 54754A
Option A Step 1: Capture fixture S4P ( Pad+trace +SMA )
Calibrate using SMA standard and Probe standard Measure DUT

Port2: Probing Port1: Pad Probing SMA

Capture S4P of SMA+Trace in Time Domain

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Probing Example

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TDR De-embedding
Option A Step 1: Capture fixture S4P for trace with SMA at one end and PCB pads at the other end? Step 2: De-embedding fixture trace using ADS

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TDR De-embedding
Option B De-embedding including SMA using on-board calibration short and load standard

short Measurement 50 ohm load

DUT

15

Return Loss De-embedding

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De-Embedding using VNA

Equipment : Agilent ENA Calibration : SOLT DUT: Port 1, 2 - SMA Port 3, 4 - USB connectors
Require TRL-like PCB calibration standard

Fixture delay estimation use port extension to measure fixture delay

Port1,2 SMA USB
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Port3,4

USB3.0 De-embedding Example

How to measure S4P from A to C?

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USB3.0 De-embedding Example

A C

How to measure S4P from A to C?

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De-embedding fixture and Calibration board

C A

De-embedding fixture

Calibration Board

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Calibration Fixture
Calibration Standard

Open/Short/Load Port1, 3 use coaxial standard Port 2,4 use calibration board Delay/through
Port 1-2 use coaxial standard Port 3-4 use 2x fixture trace Prot 1-3, 2-4, 1-4, 2-3 use 1x fixture trace
1x thru trace

1x fixture trace

Open/Short/load

2x thru trace
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Example : Return Loss Measurement

Introduction Return loss measurement When return loss is not passing
Return loss fixture removal

How to fix the return loss problem Summary

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Sata Interconnect

Return Loss Specification limits the reflected energy

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Return Loss Definition

Return Loss =

or

where

Zo is the Tx/Rx differential output/input impedance ZL is the link differential impedance Vi is the differential voltage incident upon Rx/Tx Vr is the differential reflected voltage from Tx/Rx

Slid e 24

Common Mode vs. Differential Mode

Slid e 25

Return Loss Measurement

Many design can not meet return loss requirement Return loss accuracy and repeatability become crutial Both TDR ( time domain ) and VNA (frequency domain) can be used for return loss measurement Recommend VNA for marginal design
Accuracy noise floor and calibration Repeatability - calibration standard

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Return Loss Element

Termination and IO circuit
Ask circuit designer to reduce mismatch in both differential mode and common mode

Differential driver circuit state

Design special circuit to set IO to static 1 or 0 state Capable to set static de-emphasis state

Pattern Blocking Capacitor

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Blocking Caps
The 100nF off chip coupling capacitor leads to a coupling time constant of 10 us. Such a long time constant is needed to limit baseline wander with scrambled data Make sure DC blocking capacitor is in placed for active transmitter return loss measurement - TDR/VNA port may gradually get damaged

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How to Pass Return Loss

Small IO capacitance less reflection Uniform impedance less reflection Shorter and uniform impedance fixture
May not require fixture de-embedding if margin is large enough

Long fixture trace and via will have better return loss number because reflection are attenuated by the long trace You got wrong result

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Vector Network Analyzer

Frequency Domain Equipment Single ended measurement Convert to differential mode and common mode with software

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How Return Loss Are Measured today

VNA Setup
0 dbm (1mw)

Tx Setup
One driver on AC high state ( < Voh) Another driver on AC low state (> Vol)

Rx Setup
Activate terminator

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Return Loss De-embedding

Simulation to remove the SMA, PCB trace, via and fingers. The return loss after de-embedding are usually worse than the VNA data measured at the SMA or PCB fingers

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SMA Anti-pad Optimization

Antipad diameter under trace Antipad diameter above trace Signal via radius Trace moved to different layer Ground via distance SMA

Optimized Anti-pad Design

Optimization critera -- 50 ohm -- low return loss

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Return Loss Tuning Strategy : Simulation

Pkg Stub

Pkg Via

Pkg Trace

Bond Wire

Ri Ci

Rterm

Agilent ADS or any spice tool can make this simple model
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Transmit Port B Return Loss Including PCB

Red: Model Blue: Measured

An Example: XAUI

Receive Port B Return Loss Including PCB

Red: Model Blue: Measured

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Transmit Port B Return Loss

Not Including Socket

Receive Port B Return Loss

Not Including Socket

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Pink: Measured Rx Black: Model Rx

Violations at 3Ghz

What was wrong in this design?

Slide 39

Circuit for Return Loss Calculation

CL: Cell Capacitance RS: Cell Series Resistance Z0: Reference Resistance for S11 Calculation RL: Termination resistance

Z0 CL RL S11 RS

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Rx Return loss model vs measured

SMA

Pcb via 83ps

Package Pad/ball/via

Ci

Slide 41

Rx Return Loss Debugging

Identify the elements from S11 plot
3GHz = 333ps Reflection at 180 degree 165ps Round trip delay 83ps Delay from PCB pad to Pakage pad ~83ps

Fix:
Increase the impedance to 50 ohm at the PCB via and package via in the model

Slide 42

Pink: measured Rx Black: modified Rx model

Replace PCB via and Package pads to 50 ohm

Slide 43

TX : Increase PCB and Pads to 50 ohm

Slide 44

Return Loss Summary

Measurement based return loss provides accurate results after de-embedding SMA and lead-in traces on the text fixture SMA Impedance discontinuity can affect return loss significantly Optimized SMA anti-pad design can improve return loss accuracy Return loss measurement can be verified by careful modeling the package and PCB interconnect transistion
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Hands-on Lab
USB Compliance test Configuration Different fixture design comparison Insertion loss Eye diagram Conclusions

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USB 3.0 Tx Compliance Channels

Compliance Channels are defined to test Transmitter for worst case conditions. Worst Case Channel for Hosts 5 Device PCB Trace 3M Cable Worst Case Channel for Devices 11 Device PCB Trace 3M Cable
Device Tx TP1 Host Tx TP0

Host Tx TP1

3 Meter USB 3.0 Cable

Device Tx TP0

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GRL Case Study:

USB-IF Fixture with 4 USB3.0 Cable

Three USB 3.0 Probing Setups for Device Testing

TP0
INTEL_TIER2.S4P

TP0
AGILENT_TIER2.S4P

Scope

Agilent Fixture with 4 USB3.0 Cable

TP0
LITEK_TIER2.S4P

Measurement Plane

LiTek Fixture with 0 Cable

TP0 (Device Connector) Measurement Plane

FixtureX.S4P

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Embed of USB 3.0 Cable + Host Channel

Compliance Test Point
100mV Eye Mask

CTLE In Scope SW

TP1

Transmit Channel

TP0

cascade_cable_back.s4p

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Differential Insertion Loss Comparison

2.5GHz Nyquist Frequency

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Results
LiTek + 0 Cable Agilent + 4 Cable Intel + 4 Cable @ Scope Inputs

@ TP0
DUT Connector

@ TP1-Eq
Compliance Point

250mV 234mV 228mV

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Conclusions
LiTek with 0 cable provides 6-9% Higher Voltage Margin than 4 Cable based fixtures. Intel Fixture, which is recommended by the USB-IF provides the least amount of margin and represents the worst case of the three fixtures tested.

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Thank You

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Contact Information
Corporate Headquarters 3500 Thomas Road, Suite A Santa Clara, CA 95054 USA
Johnson Tan, CEO jtan@graniteriverlabs.com Mike Engbretson, Chief Technology Engineer mikeen@graniteriverlabs.com

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