COURSE DESCRIPTION

Provides the overall context and framework for the development cycle of FPGAs. This course will arm with the proper planning techniques, strategy, and FPGA tool flow to get up and designing an FPGA design. The flow will take from behavioral specification to tuning specifications for the FPGA, synthesis, verification, and onto implementation and download. Throughout the design cycle, the various tools within the Project Navigator tool are introduced. This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase overall Verilog proficiency and enhance the FPGA optimization. This course covers Verilog 1995 and 2001. Use the ISE software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow. This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. Provides an understanding to be able to create more efficient designs. This course can help to fit designs in a smaller FPGA or lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, will also be able to create design faster, shorten development time, and lower development costs.

XILINX EXAM

XILINX

180 MINUTES

SECTION A: 25 SECTION B: 10

REQUIREMENTS & PREREQUISITES

Basic knowledge of the VHDL or Verilog language Basic digital design knowledge Working hdl knowledge (VHDL or Verilog) Digital design experience Essentials of FPGA design course or equivalent knowledge of FPGA architecture features; the Xilinx implementation software flow and implementation options; reading timing reports; basic FPGA design techniques; global timing constraints and the constraints editor Intermediate hdl knowledge (VHDL or Verilog) Solid digital design background

TARGET AUDIENCE
Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the ISE design tools. Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs. Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs. FPGA designers with intermediate knowledge of HDL and some experience with the Xilinx ISE software tools.

COURSE DURATION

COURSE STRUCTURE
Module Code
Xilinx-01 Xilinx-02 Xilinx-03 Xilinx-04 Prep Xilinx Exam ISE Design Tool Flow Designing with Verilog Essentials of FPGA Design for Performance Exam Preparation Xilinxs IC Design Examination

Module Title

Days
1 4 2 3 1 1

Total Days

12

LEARNING METHODS / DELIVERY METHODS

Lectures, hands-on labs, and interactive discussions.

LEARNING OUTCOME
After completing this comprehensive training, you will have the necessary skills to: Outline a complete project planning process Create a new Project Navigator project in the ISE software Access and modify Xilinx Synthesis Technology (XST) synthesis options Assign pin locations using the I/O Planner Enter global clock constraints using the Xilinx Constraints Editor Simulate a design using the ISim Simulator Write RTL Verilog code for synthesis Write Verilog test fixtures for simulation Create a Finite State Machine (FSM) by using Verilog Target and optimize Xilinx FPGAs by using Verilog Use enhanced Verilog file I/O capability Run a timing simulation by using Xilinx Simprim libraries Create and manage designs within the ISE software design environment Download to the evaluation demo board

Take advantage of the primary features of the 7 series FPGAs Use the Xilinx Project Navigator to implement and simulate an FPGA design Read reports and determine whether your design goals were met Use the Clocking Wizard to create MMCM instantiations Use the I/O Planner to make good pin assignments Use the Xilinx Constraints Editor to enter global timing constraints Describe the architectural features of the 7 series FPGAs Create and integrate cores into your design flow by using the CORE Generator interface Describe the clocking features of the 7 series FPGAs and how they can be used to improve performance Increase performance by duplicating registers and pipelining Increase system reliability by adding an appropriate synchronization circuit Describe different synthesis options and how they can improve performance Describe a flow for obtaining timing closure Pinpoint design bottlenecks by using timing reports Apply advanced timing constraints to meet your performance goals Use advanced implementation options to increase design performance

DETAILED COURSE CONTENT

Topic: ISE Design Tool Flow
1. Course Agenda 2. Project Planning 3. Projects in the Project Navigator Lab 1: Projects in the Project Navigator Gain comprehensive hands-on experience with the HDL flow in the ISE software. Create a new project, add source files, synthesize a design, and use the error navigation feature to fix HDL code. 4. HDL Synthesis and XST Lab 2: XST Synthesis Options Modify XST synthesis properties, read synthesis reports to compare the synthesis results with the implemented results, and use the schematic viewer to evaluate the design. 5. Constraints and the I/O Planner Lab 3: I/O Pin Planning Review demo board documentation to determine the finished pinout and use the PlanAhead tool to assign pin location constraints and set other pin attributes. 6. ISim Simulator Lab 4: ISim Simulator Use the project navigator to view an HDL testbench, use the ISim Simulator to run simulation view output waveforms, add signals, and change their viewed format. 7. Additional Features

Lab Descriptions: Lab 1: Projects in the Project Navigator Gain comprehensive hands-on experience with the HDL flow in the ISE software. Create a new project, add source files, synthesize a design, and use the error navigation feature to fix your HDL code. Lab 2: Synthesis Options Modify XST synthesis properties, read synthesis reports to compare the synthesis results with the implemented results, and use the schematic viewer to evaluate the design. Lab 3: I/O Pin Planning Review demo board documentation to determine the finished pinout and use the PlanAhead tool to assign pin location constraints and set other pin attributes. Lab 4: ISim Simulator Use the project navigator to view an HDL testbench, use the ISim Simulator to run simulation view output waveforms, add signals, and change their viewed format.

Topic: Designing with Verilog

Course Outline: 1. Hardware Modeling Overview 2. Verilog Language Concepts 3. Modules and Ports - Lab 1: Building Hierarchy 4. Introduction to Testbenches - Lab 2: Verilog Simulation and RTL Verification 5. Verilog Operators and Expressions 6. Data Flow-Level Modeling - Lab 3: Memory 7. Verilog Procedural Statements - Lab 4: Clock Divider and Address Counter 8. Controlled Operation Statements - Lab 5: n-bit Binary Counter and RTL Verification 9. Verilog Tasks and Functions 10. Advanced Language Concepts - Lab 6: Timing Simulation 11. Finite State Machines - Lab 7: Finite State Machines 12. Targeting Xilinx FPGAs - Lab 8: Implement and Download 13. Advanced Verilog Testbenches - Lab 9: Using Verilog File I/O

Lab Descriptions:

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.

Topic: Essentials of FPGA Design

1. Basic FPGA Architecture 2. Xilinx Tool Flow Lab 1: Xilinx Tool Flow Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan-6 FPGA SP605 evaluation board. 3. Reading Reports Lab 2: Clocking Wizard and Pin Assignment Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into the design. Use the PlanAhead tool to assign pin locations and implement the design using the Project Navigator in the ISE software. Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules. 4. Global Timing Constraints Lab 4: Global Timing Constraints Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint. 5. Synchronous Design Techniques Lab Descriptions: Lab 1: Xilinx Tool Flow Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to the evaluation board. Lab 2: Clocking Wizard and Pin Assignment Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead tool to assign pin locations and implement the design using the Project Navigator in the ISE software. Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules. Lab 4: Global Timing Constraints Enter global timing constraints with the Xilinx Constraints Editor. Review the PostMap Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.

Topic: Designing For Performance

Course Outline: 1. Review of Fundamentals of FPGA Design 2. Designing with FPGA Resources 3. CORE Generator Software System 4. Basic FPGA Clock Resources 5. Virtex-6 and Spartan-6 FPGA Clock Resources - Lab 1: Designing with FPGA Resources Create block RAM and clocking FPGA cores using the COR E Generator tool. Instantiate these cores and other clock resources and implement the design. 6. FPGA Design Techniques 7. Synthesis Techniques - Lab 2: Synthesis Techniques Experiment with different synthesis options and view the results. Versions of this lab are available for Synplicity Synplify Pro, Precision RTL, and Xilinx XST software. 8. Achieving Timing Closure - Lab 3: Review of Global Timing Constraints Use the Constraints Editor to enter global timing constraints 9. Path-Specific Timing Constraints (Part I) 10. Path-Specific Timing Constraints (Part II) - Lab 4: Achieving Timing Closure Review timing reports and enter path-specific timing constraints to meet performance goals. 11. Advanced Implementation Options - Lab 5: Designing for Performance Improve performance and maximize results solely with implementation options and SmartXplorer.
Lab Descriptions: Lab 1: Designing with FPGA Resources Create block RAM and clocking FPGA cores using the CORE Generator tool. Instantiate these cores and other clock resources and implement the design. Lab 2: Synthesis Techniques Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results. Lab 3: Review of Global Timing Constraints Use the Constraints Editor to enter global timing constraints. Lab 4: Achieving Timing Closure Review timing reports and enter path-specific timing constraints to fully describe your performance requirements. Lab 5: Designing for Performance Improve performance and maximize results solely with implementation options and the multiple run feature. Lab 6: FPGA Editor Demo (optional) Use the FPGA Editor to view a design and add a probe to an internal net. Lab 7: ChipScope Pro Software (optional) Add an internal logic analyzer to a design to perform real-time debugging.