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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.

8, AUGUST 2010 1975


Implementation and Performance Evaluation
of a Fast Dynamic Control Scheme for
Capacitor-Supported Interline DVR
Carl Ngai-Man Ho, Member, IEEE, and Henry Shu-Hung Chung, Senior Member, IEEE
AbstractThe implementation of a fast dynamic control scheme
for capacitor-supported interline dynamic voltage restorer (DVR)
is presented in this paper. The power stage of the DVR consists
of three inverters sharing the same dc link via a capacitor bank.
Each inverter has an individual inner control loop for generating
the gate signals for the switches. The inner loop is formed by a
boundary controller with second-order switching surface, which
can make the load voltage ideally revert to the steady state in two
switching actions after supply voltage sags, and also gives output
of low harmonic distortion. The load-voltage phase reference is
commonto all three inner loops andis generatedby anouter control
loopfor regulating the dc-linkcapacitor voltage. Suchstructure can
make the unsagged phase(s) and the dc-link capacitor to restore
the sagged phase(s). Based on the steady-state and small-signal
characteristics of the control loops, a set of design procedures will
be provided. A 1.5-kVA, 220-V, 50-Hz prototype has been built and
tested. The dynamic behaviors of the prototype under different
sagged and swelled conditions and depths will be investigated. The
quality of the load voltage under unbalanced and distorted phase
voltages, and nonlinear inductive loads will be studied.
Index TermsBoundary control, dynamic voltage restoration
(DVR), inverters, power quality, voltage sag.
I. INTRODUCTION
E
LECTRONICsystems operate properly as long as the sup-
ply voltage stays within a consistent range. There are sev-
eral types of voltage uctuations that can cause the systems to
malfunction, including surges and spikes, sags, harmonic dis-
tortions, and momentary disruptions. Among them, voltage sag
is the major power-quality problem [1]. It is an unavoidable
brief reduction in the voltage from momentary disturbances,
such as lightning strikes and wild animals, on the power system.
Although most of them last for less than half a second, this is
often long enough for many types of loads to drop out. Typical
Manuscript received February 4, 2010. Date of current version June 25,
2010. This work was supported by a grant from the Research Grants Council
of the Hong Kong Special Administrative Region, China, under Project CityU
112407. This paper was presented in part at the Applied Power Electronics
Conference and Exposition 2007, Anaheim, CA, Feb. 25Mar. 1. Recommended
for publication by Associate Editor J. HR Enslin.
C. N.-M. Ho is with ABB Corporate Research, Ltd., 5405 Baden-D attwil,
Switzerland (e-mail: carl.ho@ch.abb.com).
H. S.-H. Chung is with the Centre for Power Electronics, City University of
Hong Kong, Kowloon, Hong Kong (e-mail: eeshc@cityu.edu.hk).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TPEL.2010.2044587
examples include variable speed drives, motor starter contac-
tors, control relays, and programmable logic controllers. Such
an unplanned stoppage can cause the load to take a long time to
restart and can lead to high cost of lost production [2].
Dynamic voltage restorer (DVR) is presently one of the most
cost-effective and thorough solutions to mitigate voltage sags
by establishing proper quality voltage level for utility cus-
tomers [3]. Its function is to inject a voltage in series with the
supply and compensate for the difference between the nominal
and sagged supply voltage. The injected voltage is typically pro-
vided by an inverter, which is powered by a dc source [4][7],
such as batteries, ywheels, externally powered rectiers, and
capacitors.
Voltage restoration involves determining the amount of en-
ergy and the magnitude of the voltage injected by the DVR.
Conventional voltage-restoration technique is based on inject-
ing a voltage being in-phase with the supply voltage [7][10].
The injected voltage magnitude will be the minimum, but the
energy injected by the DVR is nonminimal.
In order to minimize the required capacity of the dc source,
a minimum energy injection (MEI) concept is proposed in
[10][13]. It is based on maximizing the active power deliv-
ered by the supply mains and the reactive power handled by the
DVRduring the sag. Determination of the injected-voltage mag-
nitude is based on a real-time iterative method to minimize the
active power injection by the DVR. This can then enhance the
ride-through capability. However, the operation of each phase
is individually controlled. There is no energy interaction be-
tween the unsagged phase(s) and the sagged phase(s), in order
to enhance the voltage restoration [14], [15]. Moreover, as the
computation method is purely based on sinusoidal waveforms,
the implementation is complicated in distribution network with
nonlinear load. A sliding window over one line cycle of the fun-
damental frequency is proposed in [13] to determine the active
and reactive power at the fundamental frequency. The lengthy
computation time of the injected voltage phasor will cause out-
put distortion after a voltage sag.
Instead of using an external energy storage device, the meth-
ods in [16] and [17] take the active power for the inverter from
the transmission system via a shunt-connected rectier. The se-
ries inverter by its self has the capability to provide real-series
compensation to the line.
The rectier-based source requires a separate service supply,
while the battery-based source requires regular maintenance and
is not environment friendly. Atheoretical study of the capacitor-
supported DVR for unbalanced and distorted loads is recently
0885-8993/$26.00 2010 IEEE
1976 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Fig. 1. Structure of the proposed interline DVR and its connection to the
utility.
proposed in [18]. No external source is required in the DVR.
The required phase and magnitude of the inverter load-voltage
phasor are derived by considering the energy balance between
the supply and the load, but the advantage is offset by the lengthy
digital transformation and inversion of symmetrical components
and calculation of the power consumption. The waveshape of
the load voltage will be distorted and will take a relatively long
settling time. As the supply voltage is assumed to be sinusoidal
in the calculation, the load voltage will be affected and distorted
with nonsinusoidal supply voltage and load current [18].
A single-phase capacitor-supported DVR is proposed in [19].
The load voltage can ideally be reverted to the steady state in two
switching actions after voltage sags. By extending the concept,
an analog-based three-phase capacitor-supported interline DVR
is presented. It features the following operational characteristics.
1) By extending the fast transient control scheme proposed
in [19][21], the load voltage can ideally be restored in
two switching actions after a voltage sag. This can assure
near-seamless load voltage and power.
2) The load voltage balance and quality can be maintained,
even if the supply is unbalanced and/or has harmonic dis-
tortion, and the load is nonlinear and/or unbalanced.
3) As the three inverters share the same dc link and the con-
troller acts on the three inverters together, the unsagged
phase(s) will help restore the sagged phase(s) during the
voltage sag.
A1.5-kVA, 220-V, 50-Hz prototype has been built and tested.
The steady-state and dynamic behaviors of the prototype will
be provided.
II. PRINCIPLES OF OPERATION
Fig. 1 shows the circuit schematic of the DVR with three-
phase transmission system. It consists of inverters, output LC
lters, and injection transformers. The dc side is connected to
a capacitor bank, formed by two capacitors. Each capacitor
has the value of C
dc
. The inverter shown in Fig. 1 is a half-
bridge conguration. However, the operation is similar in the
full-bridge conguration. The DVRis operated as a controllable
voltage source v
d,n
, where n represents either phase a, b, or c. It
is connected between the supply and the load. The relationship
among the supply voltage v
s,n
, the load voltage v
o,n
, and v
d,n
is
v
d,n
(t) = v
s,n
(t) v
o,n
(t). (1)
Fig. 2 shows the phasor diagrams of v
s,n
, v
o,n
, v
d,n
, and
the load current i
o,n
in voltage sag and unbalanced conditions.
Fig. 3 shows the control block diagram of proposed control
scheme. The control scheme consists of two main loops. The
rst control loop, namely inner loop, is formed in each phase.
It is used to generate the gate signals for the switches in the
inverter, so that v
d,n
will follow the DVR output reference v

d,n
.
This loop has fast dynamic response to external disturbances. Its
operating principle is based on extending the boundary control
technique with second-order switching surface in [19][21].
The second loop, namely outer loop, is used to generate v

d,n
.
Based on (1)
v

d,n
(t) = v
s,n
(t) v

o,n
(t) (2)
where v

o,n
is the load-voltage reference and is generated by the
phase-lock loop (PLL).
The outer loop is used to regulate the dc-link voltage by
adjusting the phase of the inverter load voltage with respect to
the load current. Its bandwidth is set much lower than the line
frequency. The purpose is to attenuate the undesirable signals,
which are due to the ac component on the dc-link voltage and
the load current, getting into the loop. Since the inner and outer
loops have different dynamic behaviors, the controller will react
differently in the voltage sags of short and long durations.
If the duration of the voltage sag is short [22][25], typi-
cally less than 0.5 s, the inner loop will react immediately and
maintain the waveshape of the load voltage. The outer loop is
relatively inert during the period. The sagged phase(s) will be
supported purely by the capacitor bank. The capacitor voltage
will decrease. After the voltage sag, the outer loop will start
reacting to the decrease in the capacitor voltage. The capacitor
will be charged up from the supply by adjusting the phase angle
of the inverter output.
If the duration of the voltage sag is long, the inner loop will
keep the waveshape of the load voltage and the outer loop will
regulate the dc-link voltage. Thus, the sagged phase(s) will be
supported by the dc link, while electric energy will also be
extracted from the unsagged phase(s) through the dc link.
In the steady-state operation, as the frequency response of the
inner loop is very fast, the waveshape of the load voltage can
be kept sinusoidal, even if there are harmonic distortions in the
supply voltage and the load current. Moreover, with the interline
energy ow in the outer-loop control, the output quality can be
maintained, even if there is an unbalanced supply voltage.
At any time, the amplitude of v

o,n
is xed because the load
voltage is regulated at the nominal value. v

o,n
has the same
HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME 1977
Fig. 2. Steady-state vector diagrams with different sagged conditions.
(a) v
s, a
is changed from 220 to 120 V
rms
. (b) Unbalanced three-phase voltages
with v
s, a
= 210 V
rms
, v
s, b
= 190 V
rms
, and v
s, c
= 240 V
rms
.
frequency as v
s,n
, and the phase angle between v

o,n
and
v
s,n
is controlled by the signal v

shown in Fig. 3. The supply


voltages can be expressed as follows:
v
s,a
(t) = V
sm,a
cos t (3a)
v
s,b
(t) = V
sm,b
cos (t 120

) (3b)
v
s,c
(t) = V
sm,c
cos (t + 120

) (3c)
Fig. 3. Block diagram of the proposed controller.
where V
sm,a
, V
sm,b
, and V
sm,c
are the peak values of the supply
voltages of the phases a, b, and c, respectively, and is the
angular line frequency.
III. REVIEW OF INNER LOOP
The inner-loop control strategy is by using boundary control
with second-order switching surface. The control concept has
been well documented in [19]. A brief review will be given in
this section.
In one leg of the three-phase half-bridge inverter, which is
shown in Fig. 1, as S
1,n
and S
2,n
are operated in antiphase and
the output inductor current is continuous, two possible switching
modes are derived, and their state-space equations are shown as
follows.
When S
1,n
is OFF and S
2,n
is ON
x
n
=
_
0 1/L
1/C 1/R
L,n
C
_
x
n
+
_
1/2L 0
0 1/R
L,n
C
_
u
n
(4a)
v
d,n
= [ 0 1 ]x
n
. (4b)
When S
1,n
is ON and S
2,n
is OFF
x
n
=
_
0 1/L
1/C 1/R
L,n
C
_
x
n
+
_
1/2L 0
0 1/R
L,n
C
_
u
n
(5a)
v
d,n
= [ 0 1 ]x
n
(5b)
where x
n
= [i
L,n
v
C,n
]
T
, u
n
= [v
dc
v
s,n
]
T
, and R
L,n
is the
ctitious resistance showing the ratio between the load voltage
and load current.
Fig. 4(a) and (b) shows the equivalent circuits of the two
modes corresponding to (4) and (5). By solving (4) and (5)
with different initial values, families of state-plane trajectories
shown in Fig. 5 can be derived. The solid lines are named
as the positive trajectories, while the dotted lines are named
as the negative trajectories. The positive trajectories show the
trajectories of the state variables when S
1,n
is ON and S
2,n
is
1978 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Fig. 4. Equivalent circuits of one phase in the inverter system. (a) S
1, n
is OFF
and S
2, n
is ON. (b) S
1, n
is ON and S
2, n
is OFF.
Fig. 5. State-plane trajectories of the inverter.
OFF. The negative trajectories show the trajectories of the state
variables when S
1,n
is OFF and S
2,n
is ON.
As discussed in [20] and [21], the tangential component of
the state-trajectory velocity on the switching surface determines
the rate at which successor points approach or recede from
the operating point in the boundary control of the switches.
An ideal switching surface
i
that gives fast dynamics should
follow the only trajectory passing through the operating point
[31][33]. Although
i
can ideally go to the steady state in
two switching actions during a disturbance, its shape is load-
dependent and requires sophisticated computation to determine
the only positive and negative trajectories that pass through the
operating point.
A second-order switching surface
2
, which is close to
i
around the operating point, is derived. The concept is based
on estimating the state trajectory after a hypothesized switch-
ing action. As the switching frequency of the switches is much
higher than the signal frequency, the load current i
o
is relatively
constant over a switching cycle. The gate signals to the switches
are determined by the following criteria. For the sake of sim-
plicity and without loss of generality, v
c,n
and v
d,n
in Fig. 1 are
assumed to be equal [19].
A. Criteria for Switching S
1,n
OFF and S
2,n
ON
S
1,n
and S
2,n
are originally ON and OFF, respectively. S
1,n
and S
2,n
are going to switch OFF and ON, respectively. Thus,
according to [19], the criteria for switching S
1,n
OFF and S
2,n
ON are as follows:
v
d,n
(t
1
) v
d,n,max

L
2C
1
(v
dc
(t
1
)/2) +v
d,n
(t
1
)
i
2
C,n
(t
1
)
(6)
and
i
C,n
(t
1
) 0. (7)
B. Criteria for Switching S
1,n
ON and S
2,n
OFF
S
1,n
and S
2,n
are originally OFF and ON, respectively. S
1,n
and S
2,n
are going to switch ON and OFF, respectively. Thus,
according to [19], the criteria for switching S
1,n
ON and S
2,n
OFF are as follows:
v
d,n
(t
3
) v
d,n,min
+
L
2C
1
(v
dc
(t
3
)/2) v
d,n
(t
3
)
i
2
C,n
(t
3
)
(8)
and
i
C,n
(t
3
) 0. (9)
Based on (6)(9) and v
d,n,min
= v
d,n,max
= v

d,n
, the general
form of
2
is dened as follows:

2
[i
L,n
(t), v
d,n
(t)] =
1
k
_
v
d,n
(t) v

d,n
(t)

_
v
dc
(t)
2
+ sgn[i
C,n
(t)]v
d,n
(t)
_
+ sgn[i
C,n
(t)]i
2
C,n
(t) (10)
where k = L/2C.
Fig. 5 shows the load line and the second-order switch-
ing surface (
2
127 V
) when the required output voltage of the
DVR is 127 V. Fig. 6 shows the simulated state-plane trajec-
tory of the DVR for compensating v
s,n
changing from 220 to
130 V. The states of the rst and the second switching actions are
labeled. The switching surface described in (10) is implemented
with analog circuitry.
IV. CHARACTERISTICS OF OUTER LOOP
A. Steady-State Characteristics
The function of the outer loop is to regulate v
dc
at the refer-
ence value of V

dc
. By applying the conservation of energy [26],
the DVR will ideally have zero-average real power ow at the
HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME 1979
Fig. 6. Simulated state trajectory of the DVR for v
s, n
changing from 220 to
130 V.
steady state. Thus
P
s,a
+P
s,b
+P
s,c
= P
o,a
+P
o,b
+P
o,c
(11)
P
a
+P
b
+P
c
= 0 (12)
P
s,n
= v
s,n
i
o,n
cos(
n
) (13)
P
o,n
= v
o,n
i
o,n
cos
n
(14)
P
n
= v
d,n
i
o,n
cos
n
(15)
where P
s,n
, P
o,n
, and P
n
are the input, output powers, and
power transferred of the each phase, respectively, i
o,n
is the
load current of each phase,
n
is the phase angle between v
o,n
and i
o,n
, is the phase angle between v
s,n
and v
o,n
, and
n
is
the phase angle between v
d,n
and i
o,n
.
Under supply-voltage interruption, the outer loop will adjust
the value of . The DVR will generate the required magnitude
and phase of v
d,n
in each phase individually. The DVR will
then absorb (deliver) electric energy from (to) the dc link. As
the adjustment of is common to the three phases, the sagged
phase(s) will be supported by the capacitor bank and the un-
sagged phase(s). The corresponding equations of v
o,n
are as
follows:
v
o,a
(t) = V
om,a
cos (t ) (16a)
v
o,b
(t) = V
om,b
cos (t 120

) (16b)
v
o,c
(t) = V
om,c
cos (t + 120

) (16c)
where V
om,n
is the peak load voltage of phase n.
Fig. 2 shows the steady-state phasor diagrams with one-phase
sagged and three-phase voltage balancing, respectively. The pa-
rameters used are based on Tables IIII.
In Fig. 2(a), v
s,a
is reduced to 120 V, while the other phases
are at the nominal value of 220 V. By increasing the value of ,
v
d,a
is established by the DVR and v
o,a
can be kept at 220 V.
Thus, part of the energy supplied to phase-a load is supported
by phases b and c.
TABLE I
SPECIFICATIONS OF THE DVR
TABLE II
PARAMETERS OF THE PLL AND TRANSDUCER GAINS
TABLE III
COMPONENT VALUES OF THE DVR
In Fig. 2(b), all three phases are unbalanced, where v
s,a
=
210 V, v
s,b
= 190 V, and v
s,c
= 240 V. Again, by adjusting the
value of , v
o,a
, v
o,b
, and v
o,c
are regulated at 220 V.
For the phase transformation between and
n

n
= (
n

n
) (17)
where
n
is the phase difference between v
s,n
and v
d,n
.
Based on Fig. 2(a) and by using (15) and (17), it can be shown
that the steady-state power-transfer equation can be expressed
as follows:
P
n
= i
o,n
_
v
2
o,n
+v
2
s,n
2v
o,n
v
s,n
cos
cos
_
_

n
+cos
1
_
_
v
s,n
v
o,n
cos
_
v
2
o,n
+v
2
s,n
2v
o,n
v
s,n
cos
_
_
_
_
.
(18)
Detailed derivation of (18) is given in the Appendix.
The values of v
s,n
, v
o,n
, i
o,n
, and
n
are different in each
phase. Thus, the power ow of each phase inverter is different.
is controlled by the outer loop in order to achieve power
equilibrium in the system, and thus, satisfy (11) and (12).
B. Small Signal Modeling
Fig. 7 shows the small-signal model of the outer loop. It
consists of the transfer characteristics of the inner loop, inverter,
1980 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Fig. 7. Small-signal model of the outer loop.
PLL, and power-ow controller. As the inner loop has much
faster dynamic response than the outer loop, the small-signal
transfer function of the inner loop is unity. The transfer function
of the inverter describes the small-signal behaviors between
and v
dc
. The functional blocks of power stage and controller are
derived as follows.
1) Relationship Between v
dc
and p
dc
: The small-signal dc-
link voltage to dc-power-transfer function T
p
(s) is as follows:
T
p
(s) =
v
dc
(s)
p
dc
(s)
=
2
sC
dc
V
dc
(19)
where V
dc
is the steady-state values of v
dc
.
2) Relationship Between Power Flow and the Phase of v
d
With Respect to i
o,n
in Each Phase: The small-signal DVR-
phase-to-power transfer function T
r,n
(s) equals
T
r,n
(s) =
p
n
(s)

n
(s)
= V
d,n
i
o,n
(20)
where V
d
is the steady-state values of v
d
.
3) Phase Transformation Between and in Each Phase:
The transfer function T
pt,n
(s) representing the transformation
between and is
T
pt,n
(s) =

n
(s)
(s)
=
V
s,n
V
d,n
V
s,n
V
o,n
cos B
_
V
2
o,n
+V
2
s,n
2V
o,n
V
s,n
cos B
(21)
where V
s
, V
o
, and B are the steady-state values of v
s
, v
o
, and
, respectively.
4) Phase Transformation Between and v
dc
in Inverter:
The transfer function T
inv
(s) of the inverter is as follows:
T
inv
(s) =
v
dc
(s)
(s)
=
2
sC
dc
V
dc
(V
s,a
i
o,a
cos
a
+ V
s,b
i
o,b
cos
b
+V
s,c
i
o,c
cos
c
). (22)
Detailed derivation of (19)(22) are given in the Appendix.
Fig. 8. Circuit schematic of the power-ow controller.
5) PLL: The PLL consists of three components, including
the phase detector (PD), loop lter (LF), and the voltage-
controlled oscillator (VCO) [27]. Based on [19], the small-signal
model of the PLL is as follows:
T
PLL
(s) =
(s)
v

(s)
=
T
vco
(s)F
C
(s)
1 T
vco
(s)T
pd
(s)F
L
(s)
= A

2
n
s
2
+ 2
n
s +
2
n
(23)
where A = (R
l
/R
c
K
pd
), = 1/2
_
K
pd
K
l
K
vco
, and

n
=
_
K
pd
K
l
K
vco
/, K
pd
, K
l
, K
vco
are the constant gains
of PD, LF and VCO, respectively.
6) Power-Flow Controller: The function of the power-ow
controller is to regulate v
dc
at the reference voltage V

dc
, which
is determined by the voltage ratings of the capacitor and the
switches. Charging or discharging the capacitor C
dc
is achieved
by adjusting
n
in three phases individually. The regulation
action is performed by the error amplier shown in Fig. 8. The
transfer function T
C
(s) can be shown in (24), at the bottom of
the page.
V. SIMPLIFIED DESIGN PROCEDURES
The values of L, C, and C
dc
in the inverter, R
1
, R
2
, C
1
, and
C
2
in the power-ow controller are designed as follows.
A. Design of L and C in the Inverter
The values of L and C in the output lters are determined
by considering the maximum voltage drop across the inductor
v
L,D
at the maximumline current I
o,max
, angular line frequency
, maximum ripple current I
ripple
, and angular switching fre-
quency
sw
. As most of the load current is designed to ow
through L, the value of L is determined by considering that its
voltage drop v
L,D
is small at the maximum line current I
o,max
.
Thus
LI
o,max
< v
L,D
L <
v
L,D
I
o,max
. (25a)
As the inverter output consists of high-frequency harmonics,
the fundamental component of the ripple current through the
lter is designed to be less than I
ripple
. For the sake of simplicity
T
C
(s) =
v

v
dc
=
s
2
+ ((1/R
2
C
2
) + (1/R
2
C
1
) + (1/R
1
C
2
))s + (1/R
1
R
2
C
1
C
2
)
s (s + (C
1
+C
2
)/(R
2
C
1
C
2
))
. (24)
HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME 1981
Fig. 9. Small-signal characteristics, T
OL
(s).
in the calculation, the load impedance at the switching frequency
is assumed to be innite. Thus
2v
dc

sw
L (1/
sw
C)
< I
ripple
C >
1

sw
(
sw
L (2v
dc
/I
ripple
)
. (25b)
The nominal switching frequency is chosen to be a few hun-
dred times the line frequency. v
L,D
is chosen to be 1% of the
line voltage, and I
ripple
is chosen to one half of the peak of the
line current. As shown in Table I,
sw
= 300 , v
L,D
= 2 V,
and I
ripple
= 2.6 A for the designed prototype. Based on (25)
and stated criteria, the values of L and C in the output lters are
determined.
B. Design of C
dc
in the Inverter
The value of C
dc
is determined by
C
dc
=
4 (v
o,nor
v
s,min
) (i
o,a
cos
a
+i
o,b
cos
b
+i
o,c
cos
c
) t
res
v
2
dc,ref
8 (v
o,nor
v
s,min
)
2
(26)
where v
o,nor
and v
s,min
are nominal value of load voltage and
minimum voltage of supply voltage in specication, respec-
tively, t
res
is duration of restoration.
Detailed derivation of (26) is given in the Appendix.
C. Design of R
1
, R
2
, C
1
, and C
2
in the Power-Flow Controller
The pole and zeros are designed as follows:
log
p
= log
z2


20
(27)
Detailed derivation of (27) is given in the Appendix.
Typically, = 20 is chosen, and the ratio of
z1
and
z2
is
chosen to be at least 100, in order to avoid overlapping in the
two zeros. Therefore
log
z1
= log
z2
2. (28)
Fig. 10. Waveforms at three sagged conditions. (a) v
s, a
is changed from 220
to 120 V
rms
. (b) v
s, a
, v
s, b
, and v
s, c
are changed from 220 to 150 V
rms
.
1982 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Fig. 11. Enlarged transient waveforms in the three sagged conditions shown
in Fig. 10. (a) Single-phase sag in Fig. 10(a). (b) Three-phase sag in Fig. 10(b).
Based on (24), we have

z1
+
z2
=
1
R
2
C
2
+
1
R
2
C
1
+
1
R
1
C
2
(29)

z1

z2
=
1
R
1
R
2
C
1
C
2
(30)

P
=
C
1
+C
2
R
2
C
1
C
2
. (31)
Fig. 12. Dynamic behaviors of v
dc
in the three sagged conditions shown in
Fig. 10. (a) Single-phase sag in Fig. 10(a). (b) Three-phase sag in Fig. 10(b).
Based on (29)(31), R
1
, R
2
, C
1
, and C
2
are designed by
putting a value into one of them. Fig. 9 shows the loop gain
T
OL
(s), it is basedonthe specications anddesignedcomponent
values listed in Tables II and III. The bode plot shows operation
range, the frequency between
cross,min
, and
cross,max
within
the stable regions.
VI. EXPERIMENTAL VERIFICATIONS
A 1.5-kVA, 220-V, 50-Hz prototype has been built and
tested. The system is supplying to nonlinear inductive loads,
PF (power factor) = 0.5. The specications and the compo-
nent values are tabulated in Tables IIII. The values of the com-
ponents are designed by the procedures described in Section V.
The prototype has been tested with four different types of volt-
age disturbances, including voltage sags, voltage swells, supply
voltage distortion, and three-phase voltage unbalancing.
A. Voltage Sags
Voltage sags are programmed to occur during the supply volt-
age at the peak value in the following tests. Fig. 10(a) shows the
HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME 1983
Fig. 13. Waveforms at three swelled conditions. (a) v
s, a
is changed from 220
to 260 V
rms
. (b) v
s, a
, v
s, b
, and v
s
, c are changed from 220 to 260 V
rms
.
Fig. 14. Enlarged transient waveforms in the three swelled conditions shown in
Fig. 13. (a) Single-phase swell in Fig. 13(a). (b) Three-phase swell in Fig. 13(b).
waveforms of the DVR when there is a single-phase sag. v
s,a
is sagged from 220 to 120 V (45% sag). Fig. 2(a) shows the
phasor diagram of Fig. 10(a) in steady state. Fig. 10(b) shows
the waveform when there is three-phase sag. The three-phase
voltage sources are changed from220 to 150 V. Fig. 11 shows the
1984 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Fig. 15. Dynamic behavior of v
dc
in three voltage-swell conditions shown in
Fig. 13. (a) Single-phase swell in Fig. 13(a). (b) Three-phase swell in Fig. 13(b).
enlarged load-voltage transients in the corresponding sagged.
The transients should ideally settle into the steady state in two
switching actions. However, as the second-order switching sur-
face has discrepancies with the ideal switching surface [31],
the transients require taking three to four switching actions be-
fore settling into the steady state. The transition times are 250
and 180 s, respectively, in the aforementioned two cases. Nev-
ertheless, the transition duration is shorter than some recently
proposed control schemes [4], [6], [28][30] in similar voltage-
sag conditions. The responses of inner loop were evaluated in
the aforementioned experimental results. Fig. 12 shows the dy-
namic responses of outer loop, power-ow controller, and the
dc-link voltage variations in the two aforementioned cases. The
voltage sags start at t
1
. The capacitor bank releases energy
to the load until t
2
. Finally, v
dc
is regulated to 380 V at t
3
. In
Fig. 12, (t
2
t
1
) = 310 ms and (t
3
t
1
) = 3.8 s. In Fig. 12(b),
(t
2
t
1
) = 250 ms and (t
3
t
1
) = 7.1 s.
B. Voltage Swells
Fig. 13(a) and (b) shows the waveforms of the DVRin single-
phase and three-phase swells, respectively. The swelled phase(s)
Fig. 16. Waveforms with all three phase voltages distorted.
Fig. 17. Harmonic content of the distorted supply voltage and load voltage in
Fig. 16
is (are) changed from 220 V
rms
to 260 V
rms
. Fig. 14 shows
the enlarged load-voltage transients in the two cases. The load
voltage can be restored to the steady state in two switching
actions, taking about 180 s in the two cases.
Fig. 15 shows the dc-link voltage variations in the two afore-
mentioned cases. The voltage swells start at t
1
. The capaci-
tor bank absorbs energy from the grid until t
2
. Finally, v
dc
is
regulated to 380 V at t
3
. In Fig. 15(a), (t
2
t
1
) = 170 ms
and (t
3
t
1
) = 1.5 s. In Fig. 15(b), (t
2
t
1
) = 190 ms and
(t
3
t
1
) = 2.7 s.
C. Harmonic Distortions
Fig. 16 shows the waveforms of the DVR, when v
s,a
, v
s,b
, and
v
s,c
are seriously polluted which contain third-, fth-, seventh-,
HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME 1985
Fig. 18. Waveforms with unbalanced three-phase voltages.
and ninth-order harmonic components. The DVR acts as a
series-type harmonic-voltage compensator to lter out the har-
monic components and provide quality voltage at the output.
The waveforms of v
o,a
, v
o,b
, and v
o,c
are all sinusoidal. Fig. 17
shows the harmonic contents of the supply voltage and the load
voltage up to 19th harmonics. Even if the phase voltages have
the total harmonic distortion (THD) over 42%, the THD of v
o,a
,
v
o,b
, and v
o,c
are less than 6%. This conrms the function of the
DVR for compensating the supply voltage distortion.
D. Voltage Unbalance
Fig. 18 shows the waveforms of the DVR, when three phase
supply voltage are unbalanced. In this study, v
s,a
= 210 V
(95%), v
s,b
= 190 V(86%), and v
s,c
= 240 V(110%). Fig. 2(b)
shows the phasor diagram of the situation. The system is oper-
ating in the steady state and the load voltages are all regulated at
the nominal value. All these results are in good agreement with
the theoretical predictions.
The proposed control scheme is for DVRsupplying to at least
one phase-inductive load, it is equally applicable for resistive
load if the dc side of the inverter is powered by an external
source for compensating the inverter energy loss.
Moreover, the proposed method can be implemented by pro-
gramming the switching function in the digital controller. Fur-
ther research will be investigated into the digital implementation
of the power-ow controller [35]. This will increase the exi-
bility of the proposed method.
VII. CONCLUSION
A control scheme for three-phase capacitor-supported inter-
line DVRhas been presented. By integrating a recently proposed
boundary-control method with second-order switching surface
(inner loop), the dynamic response has been minimized to two
switching actions. The voltage sag, swell, and voltage harmonic
distortion have been compensated by this DVR. Moreover, by
using series bidirectional inverter as DVR, capacitor banks are
used to support the dc link and the sagged phase(s) could be sup-
ported by the unsagged phase(s). Long-duration voltage sags,
swell, and three-phase voltage unbalance could be overcome by
the proposed power-ow controller (outer loop). The method
has been veried with a 1.5-kVA system. The performances
of the DVR have been demonstrated and evaluated with dif-
ferent power-quality disturbances. Experimental measurements
are favorably veried with theoretical results.
APPENDIX
A. Derivation of (18)
By using the cosine law, we have
v
2
d,n
= v
2
o,n
+v
2
s,n
2v
o,n
v
s,n
cos (A1)
v
2
o,n
= v
2
d,n
+v
2
s,n
2v
d,n
v
s,n
cos
n
. (A2)
Based on (A1) and (A2), we have
cos
n
=
v
s,n
v
o,n
cos
_
v
2
o,n
+v
2
s,n
2v
o,n
v
s,n
cos
. (A3)
By substituting (A1), (A3), and (17) into (16), (18) can be
obtained.
B. Derivation of (19)
The energy E
C
stored in the dc capacitors is equal to
E
C
=
1
2
C
dc
2
v
2
dc
. (A4)
The power ow of the capacitors in the steady state is equal
to
p
dc
(t) =
1
2
C
dc
v
dc
dv
dc
dt
. (A5)
By introducing small-signal perturbations into p
dc
and v
dc
,
we have
p
dc
(t) = P
dc
+ p
dc
(t) (A6)
and
v
dc
(t) = V
dc
+ v
dc
(t) (A7)
where P
dc
and V
dc
, are the steady-state values of p
dc
and v
dc
,
respectively.
By substituting (A6) and (A7) into (A5), it can be shown that
p
dc
=
1
2
C
dc
V
dc
dv
dc
dt
. (A8)
After taking the Laplace transformation of (A8), (19) can be
obtained.
1986 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
C. Derivation of (20)
By introducing small-signal perturbations into p
n
, v
d,n
, and

n
, we have
p
n
= P
n
+ p
n
(A9)
v
d,n
= V
d,n
+ v
d,n
(A10)
and

n
=
n
+
n
(A11)
where P
n
, V
d,n
, and
n
are the steady-state values of p
n
, v
d,n
,
and
n
, respectively.
By substituting (A9)(A11) into (15) and taking the Laplace
transformation, (20) can be obtained.
D. Derivation of (21)
As the PLL adjusts the phase angle of v

o,n
, it results in
varying
n
. As depicted in Fig. 2(a), the phase relationship
between and
n
can be shown to be
v
o,n
sin
n
= v
d,n
sin
n
+v
s,n
sin(
n
). (A12)
By differentiating (A12), we have
0 = sin
n
dv
d,n
dt
+v
d,n
cos
n
d
n
dt
v
s,n
cos(
n
)
d
dt
.
(A13)
By using cosine law, we have
v
2
s,n
= v
2
d,n
+v
2
o,n
2v
o,n
v
d,n
cos(
n

n
). (A14)
By using (A1) and (A14), we have
v
o,n
= v
s,n
cos v
d,n
cos(
n
+
n
). (A15)
By differentiating (A15), we have
0 = cos(
n
+
n
)
dv
d,n
dt
+v
d,n
sin(
n
+
n
)
d
n
dt
v
s
sin
d
dt
. (A16)
By using (A13) and (A16), it can be shown that
d
n
d
=
v
s,n
v
d,n
cos(
n

n
). (A17)
By considering the small-signal variations and taking the
Laplace transformation, the transfer function of the phase trans-
formation T
pt,n
(s) is
T
pt,n
(s) =

n
(s)
(s)
=
V
s,n
V
d,n
cos(B
n

n
) (A18)
where V
s,n
, and B are the steady-state values of v
s,n
and ,
respectively.
By substituting (A3) into (A18), (21) can be obtained.
E. Derivation of (22)
By combining (20) and (A18), it can be shown that
p
n
(s)
(s)
= V
s,n
i
o,n
cos
n
. (A19)
On the ac side of the inverter, the power ow p
ac
is equal to
the sum of power in each phase
p
ac
= p
a
+p
b
+p
c
(A20)
p
ac
= p
a
+ p
b
+ p
c
. (A21)
By using the conservation of energy, we have
p
dc
= p
ac
(A22)
and combining (19) and (A19), (22) can be obtained.
F. Derivation of (26)
The design of C
dc
value is based on the restoration dura-
tion, load characteristics, and voltage rating of the DVR. The
amount of energy delivered from the capacitors in t
res
is the
difference between the three-phase total load energy and total
supply energy. By using the conservation of energy, we have
1
2
C
dc
2
_
v
2
dc,ref
v
2
dc,min
_
= [(v
o,a
v
s,a
) i
o,a
cos
a
+ (v
o,b
v
s,b
) i
o,b
cos
b
+(v
o,c
v
s,c
) i
o,c
cos
c
] t
res
. (A23)
By considering the worst case, the three-phase supply volt-
ages are sagged to the minimum voltage, as dened in the spec-
ication.
Based on (1), in order to avoid generating distorted sinusoidal
waveform at the output, when v
dc
is higher than the peak value
of v

d
. Otherwise, the situation will be similar to overmodulation
in standard pulsewidth modulation (PWM) that gives distorted
output [34]. v
dc,min
is designed to be equal to the peak value of
the injecting voltage, i.e.,
v
dc,min
= 2

2 (v
o,nor
v
s,min
) . (A24)
By combining (A23) and (A24), (26) can be obtained.
G. Derivation of (27)
As the transfer function of T
1
(s) in load-dependent, it is
necessary to design a controller that can ensure the stability
within the operating range. According to Fig. 7, the loop gain
T
OL
(s) of the control loop with power-ow controller is equal
to
T
OL
(s) = T
C
(s)T
1
(s) (A25)
where T
1
(s) = T
P LL
(s)T
inv
(s)K
T
(s) is the transfer function
of the inverter and PLL in Fig. 7. K
T
(s) is the transfer function
of the transducer shown in Fig. 7.
In order to ensure T
OL
(s) has the phase margin of 30

within
the designed operating range, the error amplier is designed to
have one pole at
p
and two zeros at the frequencies of
z1
and

z2
, respectively. The circuit schematic and T
C
(s) are shown
in Fig. 8.
By considering the upper bound of T
1
(s), T
U
1
(s),
cross,max
is chosen to be the frequency at which |T
U
1
(j
cross,max
)|
0 dB and lower than the line frequency. As the phase of T
OL
(s),

OL
, at
cross,max
must be larger than 150

for achieving
HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME 1987
sufcient phase margin, it is determined by

OL
=
1
+
C
+ 360

(A26)

z2
is chosen to be the frequency by
log
z2
= log
cross,max


C
(j
cross,max
)
C
(j
z2
)
Phase Slope
(A27)
where the typical value of phase slope in bode plot is 45

/decade,
and the phase at zero is 135

for controller shown in Fig. 8.


By considering the lower bound of T
1
(s), T
L
1
(s),
cross,min
is chosen to be the frequency at which

T
L
1
(j
cross,min
)

=
dB. By considering the phase characteristic of T
C
(s), the
relationship among
cross,min
,
p
, and
z1
is

z1
<
cross,min
<
p
(A28)

p
is determined by considering that |T
C
(
p
)| = dB. Thus,
(27) can be obtained.
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Carl Ngai-Man Ho (M07) received the B.Eng. and
M.Eng. double degrees and the Ph.D. degree in elec-
tronic engineering from the City University of Hong
Kong, Kowloon, Hong Kong, in 2002 and 2007, re-
spectively.
From 2002 to 2003, he was a Research Assistant
at the City University of Hong Kong. From 2003 to
2005, he was an Engineer at e.Energy Technology
Ltd., Hong Kong. Since May 2007, he has been a
Scientist at ABB Corporate Research, Ltd., Baden-
D attwil, Switzerland. His Ph.D. work focused on the
development of dynamic voltage regulation and restoration technology. His
current research interests include power electronics, power quality, modeling
and control of power converters, and characterization of wide bandgap (WBG)
power semiconductor devices and their applications. He holds two U.K. and one
U.S. patents in the area of lighting applications.
Dr. Ho was a Reviewer for the IEEE TRANSACTIONS ON POWER ELEC-
TRONICS, the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, the IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS, and several conferences.
1988 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Henry Shu-Hung Chung (M95SM03) received
the B.Eng. degree in electrical engineering and the
Ph.D. degree from Hong Kong Polytechnic Univer-
sity, Kowloon, Hong Kong, in 1991 and 1994, respec-
tively.
Since 1995, he has been at the City Univer-
sity of Hong Kong (CityU), where he is currently a
Professor in the Department of Electronic Engineer-
ing and Chief Technical Ofcer of e.Energy Technol-
ogy Ltd.an associated company of CityU. His re-
search interests include time- and frequency-domain
analysis of power electronic circuits, switched-capacitor-based converters,
random-switching techniques, control methods, digital audio ampliers, soft-
switching converters, and electronic ballast design. He has authored or coau-
thored six research book chapters and more than 260 technical papers, including
120 refereed journal papers in his research areas. He holds 12 patents.
Dr. Chung was IEEE Student Branch Counselor and was a Track Chair of the
technical committee on power electronics circuits and power systems of IEEE
Circuits and Systems Society in 19971998. He was an Associate Editor and
the Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPART
I: FUNDAMENTAL THEORY AND APPLICATIONS in 19992003. He is currently an
Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS. He was
the recipient of the Grand Applied Research Excellence Award in 2001 from
the CityU.