LOW-VOLTAGE CMOS CHARGEPUMP PLL ARCHITECTURE FOR LOW JITTER OPERATION

Adrian Maxim

Crystal - CIRRUS LOGIC Inc. Austin TX

OUTLINE
Jitter sources in charge-pump PLLs Sample-Reset CP-PLL architecture Process independent CP-PLL architecture Power supply partition for low jitter operation Bandwidth versus resolution (cascaded PLLs) Circuit level solutions (PFD, CP, ICO, LF) Jitter measurements Conclusions advantages / drawbacks

JITTER SOURCES IN CP-PLLs OPERATING IN LARGE VLSI ICs

Fig.1

SAMPLE-RESET LOOP FILTER ARCHITECTURE

Standard CP-PLL: stabilizing zero is given by proportional current pulses injected only during the phase difference time interval jitter / ref. spur Sample-reset CP-PLL: distribute the energy of the proportional current pulses over entire update period:
Sample phase difference Generate proportional signal Fig.2 Sample-reset versus standard Reset proportional path CP-PLLs

TYPES of SAMPLE-RESET ARCHITECTURES

Fig.3 a. 1 cap single ended, b. 2 cap single ended, c. 1 cap dif., d. 2 cap dif.

SAMPLE-RESET PLL ARCHITECTURE

Fig.4 Dual loop sample-reset PLL top level architecture

BANDGAP referenced PROCESS INDEPENDENT ARCHITECTURE

Resistors, capacitors and currents vary with process make dependent on ratios

Natural frequency:
n = K DC = K ico . I cp _ i . g m _ int 2 . C int . M

Stabilizing zero:
I cp _ i C prop g m _ int z = f update I cp _ p C int g m _ prop

Damping factor:
=

Kico I/Cgate Kico*Cint process independent Icp_i=Ibg and gm_int=1/Rbg Icp_i/gm_int=Ibg*Rbg=Vbg process independent gm_prop = Vbg/Iext = process independent gm_prop/Cprop fupdate is fupdate independent

g m _ prop 1 1 n 1 K ico . I cp _ i C int I cp _ p = I cp _ i C prop f update 2 M g m _ int 2 z 2

BANDGAP referenced PROCESS INDEPENDENT ARCHITECTURE

Fig.5 PLL architecture that assures a process independence damping factor

VOLTAGE REGULATORS COMPARISON

PMOS regulator (a.) stability at high current NMOS regulator (b.) stability at low current Cascoded regulator (c.) headroom/cascode bias Current conveyor reg. (d) VT and gm mismatches
Fig.6

POWER SUPPLY PARTITION FOR LOW JITTER OPERATION

Fig.7 analog regulator (PFD, CP, ICO, LF) digital regulator (DIV, COMP)

CASCADED PLLs RESOLUTION versus BANDWIDTH

Crystal references limited to 20-100MHz (price) High resolution (<500KHz) requires high N values lower update frequencies lower bandwidth slower locking more ICO jitter Cascaded PLLs compromise bandwidthresolution
Fig.8

PHASE-FREQUENCY-DETECTOR ARCHITECTURE
Dead-zone avoidance by generating two narrow Up & Down pulses each update period with a oneshot circuit Balance delay times at the output with pass gates that match the inverters Phase comparison gates biased from analog supply Generate non-overlapping control signals for the sample-reset proportional capacitors
Fig.9 7-NAND PFD

CHARGE-PUMP ARCHITECTURES

Fig.10

Drain sw Dummy Clock switch feed- charge through sharing

Gate Source switch switch Low high speed speed

Current steering dif/high speed

All NMOS Switches matched PFD load

Fully differential current steering high speed high PSRR

PROPOSED CHARGE-PUMP ARCHITECTURE

Source switch (Msw) high speed, low clock feed-through Two SS-CP differential mode low supply/substrate noise High swing cascoded mirrors high Zout and voltage range Dummy switches (Mdum) better current mirror matching Discharge switches (Mdchg) discharge N/P nodes C1/C2 speed-up turn-off High PSRR regulator and RC filtering reduce supply noise

Fig.11 Differential source switch CP

Fig.12

CONTROLLED OSCILLATOR ARCHITECTURES

Weighted Current starved current adder High S/N High linearity Low PSRR

Dif. Diode clamp High frequency Low S/N

Dif. triode/sat PMOS load High S/N Medium frequency

PROPOSED CONTROLLED OSCILLATOR ARCHITECTURE

Ring ICO wide frequency range Differential supply/substrate Clamped amplitude PSRR Amplitude=k*Vbg stabilize Kico Low VT MOSFETs lower substrate noise injection Cfilt reduce supply noise (1) Ring ICO jitter:
2 KT a v KT 1 2 2 = = f osc 2 2 Von I C 2 N tail total Von stage Tosc

Low W/L, high Cgate, low av Compromise: Power - Jitter Fig.13 Bandgap clamped amplitude ring ICO

SAMPLE RESET LOOP FILTER ARCHITECTURE

Integral path differential gm_int stage Proportional path dif. programmable gm_prop to assure stability with fupdate: gm_prop/Cprop fupdate
Reference process independent transconductance: gm_ref Replica gm stages create multiples of gm_ref outputs of replica stages = programmable gm_prop

the integral and proportional currents at the input of a self-biased high swing cascoded mirror (wide dynamic range) that biases the ICO ring elements

SAMPLE-RESET LOOP FILTER SCHEMATIC

Fig.14 Fully differential sample-reset current-mode loop filter

PROPOSED OUTPUT COMPARATOR ARCHITECTURE

Convert ICOs differential output into single ended drive for DIV 50% duty-cycle solutions:
Run at 2f and divide by 2 (power) Feed-forward/feedback correction

Low VT MOSFET (no VT implant) better matching, lower Voffset Low current & low gain input (decrease Cgate & Miller effect) low capacitive loading on ICO Analog supply (in)/digital supply (out) Double feedback output stage:
Rshunt restricts swing trip point INVshunt trip point tracks INVout

Fig.15 Differential comparator

SAMPLE-RESET versus STANDARD CP-PLL TRANSIENT LOCKING

Fig.16 Transient locking waveforms: a. sample-reset PLL, b. standard PLL

RMS JITTER for different BANDWIDTH and SUPPLY NOISE SETTINGS

Measurement conditions \ PLL type Low BW, quiet supply & substrate Low BW, noisy supply & substrate Low BW, noisy supply with ICO clamp High BW, quiet supply and substrate High BW, noisy supply & substrate (normal PLL operation) Std PLL SR-PLL 13.2p 21.0p 11.3p 18.7p 7.6p 12.1p 9.4p 6.2p 8.9p

0.15 CMOS TEST CHIP DIE PHOTO

Process Power supply Bias current 0.15m CMOS 2.5V/reg 1.5V < 40mA 125MHz 1.25GHz < 500KHz < 9ps @ noisy supply 800 x 200m2

SAMPLE-RESET PLL

Frequency range Resolution RMS jitter at 1GHz Silicon area

STANDARD CP-PLL

Fig.17 0.15 test chip die photo with standard and sample-reset CP-PLLs

CONCLUSIONS
Sample-reset charge-pump PLL architecture:
Staircase ICO control - minimizes reference spur & jitter Ripple-pole-less 90 phase margin, no input jitter peaking and locking overshoot Process independent - maximizes bandwidth faster looking, better reject ICO phase noise Differential architecture substrate/supply noise

Power supply partition / use high PSRR cascoded regulators minimize supply injected noise Accumulation mode capacitors and low VT devices reduce substrate noise injection