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31mW 38GHz Frequency Divider in 90 nm CMOS Technology


Guo Ting 1, 2, Zhiqun Li1, 2, Li Qin2
1 School of Integrated Circuits, Southeast University, Nanjing, China, e-mail: guotingseu@gmail.com 2 Institute of RF- & OE-ICs, Southeast University, Nanjing, China, e-mail: zhiqunli@seu.edu.cn
Abstract- In this paper, a high speed broadband divide-by-2 frequency divider is presented. The proposed divider is mainly a source-coupled logic (SCL) structure formed with two dynamicloading master-slave D latches, which enables high frequency operation, low power consumption and high input sensitivity. This divider exhibits wide locking range from 8GHz~38GHz and dissipates 1.31mW@38GHz from a 1.2V supply. The input sensitivity is only 4mV@16GHz. This chip occupies 685Pmu430Pm area with two on-chip spiral inductors in IBM 90nm CMOS process.

I.

INTRODUCTION

Frequency dividers (FDs) are the essential blocks of the phase-locked loops (PLLs) in conventional millimeter-wave transmitter/receivers and radio astronomy receivers/detectors. Because of the demand for low power, wide bandwidth and high data rates in radio astronomy receiver/detectors systems, integrated circuits tend to operate at higher frequencies, lower power consumption and higher level of integration. Thanks to the continuously decreasing feature size (transistor gate length), chip area becomes smaller and smaller while the supply voltage is lowered and lowered despite of many new challenges. For PLL in the ALMA band-1 receiver, frequency divider requires an even wider input locking range and lower power consumption while working at 27.3GHz~33GHz. There are several existing topologies for CMOS-based highfrequency FDs, such as static, dynamic and injected-locked frequency dividers (ILFDs) [1-3]. Static source-coupled logic (SCL) type FDs are considered the main vehicle in application below 10GHz. Successful current-mode logic (CML) or dynamic SCL FDs have been normally used from 10 GHz to 40 GHz. From 40GHz to 100GHz, an ILFD is suitable because of the limit of todays standard CMOS process [2]. In this paper, a dynamic SCL divide-by-2 frequency divider is proposed to achieve 27.3~33GHz high operating frequency using IBM 90nm CMOS technology. The presented divider achieves not only a very wide input locking range but also very low power dissipation at 1.2V supply voltage. Whats more, the input-sensitivity is reasonably low comparing to other FDs in both 90nm CMOS process [4-5]. II. DIVIDER STRUCTURE

A SCL frequency divider is actually a master-slave SCL Dflip-flop that is composed of two cascaded latches. The most common high-speed frequency dividers that published operating above 10GHz are dynamic SCL frequency dividers and ILFDs. ILFDs are not so suitable because it is painful to achieve wide input locking range below 40GHz operating frequency. Therefore, dynamic SCL frequency dividers are good alternatives. A. Classic Dynamic SCL FDs Fig. 1 shows the principle of a classic dynamic-loading SCL divide-by-2 FD proposed by Razavi [5]. Each latch consists of a pair of dynamic loads (MD1, MD2) which are driven by differential clock signals, a pair of sample devices (MS1, MS2) and a pair of regenerative hold devices (MH1, MH2). Input signals IN and IN are a pair of differential output signals from voltage controlled oscillator (VCO) circuit. When IN is low, MD1 and MD2 in the master (latch I) are on and latch I is in the sample mode, while MD1 and MD2 in the slave (latch II) are off and latch II is in the hold mode. When IN goes high, MD1 and MD2 in latch I are off and the master is in the regenerative hold mode. In contrast with static SCL topologies, the dynamic SCL FDs use PMOS devices as variable resistance loads instead of pure resistance loads. It is confirmed to have speeded up the operating performance and avoided the trouble of choosing appropriate pure resistance loads R that used in static SCL topologies for the reason as follow. If load resistance R is large, RC time constant will increase and it will limit the top operating frequency. If R is small, the amplitude of the FDs output signals will drop and it will not be able to drive the next circuit block. However, the dynamic SCL topologies can achieve smaller resistance loads in the sample stage to ensure small RC parasitic parameter and larger resistance loads in the hold stage to keep large output signal amplitude because of the dynamic loads resistance varying with the voltage of clock signal (VCLK) from VCO. The dynamic loads resistance rds of MD1 and MD2 is given by

Project supported by the National Basic Research Program of China (No. 2010CB327404) and the National Natural Science Foundation of China (No. 60901012). ___________________________________ 978-1-61284-307-0/11/$26.00 2011 IEEE



rds

1 g ds

1  OVDS I DO

1 Kc W ( VGS  VT ) 2 O 2L

(1)

Here, denotes the channel-length modulation factor, K is the process transconductance coefficient, W and L identify the length and width of MD1 and MD2. VGS, VT, ID are the operating parameters of MD1 and MD2. In the sample mode, VCLK is smaller than the DC voltage level, to wit, VGS= VDD VCLK is larger and rds is smaller, therefore, RC parameter is smaller and the process of discharge tends to be faster. In the hold mode, VCLK is larger than the DC voltage level and VGS=VDDVCLKis smaller and rds is larger and the output amplitude will be greater. As a result, the operating frequency will go further higher.
VDD CLK
MD1 MD2

Q QB D
MS1 MS2

DB

MH1

MH2

(a)

reverse applies. Here, some methods are considered to optimize device parameters. Firstly, find out the electron mobility of PMOS and NMOS from the PDK of IBM 90nm process and set ratio of MD1/MD2, MS1/MS2 and MC1. Secondly, estimate RC time constant with target operating frequency and decide width and length of MD1/MD2, MS1/MS2 and MC1 preliminary. Thirdly, set parameters of MH1/MH2/MC2 considering of the loop gain provided by MH1 and MH2 which increases the differential output voltage. Lastly, sweep the parameters and decide the better one by simulate the free resonating frequency. Also, a two stage output buffer in Fig. 2(b) has been used to test the output signal connecting to 50 Ohm internal impedance terminals. The first stage is differential amplifier with low load resistance and the second stage is source follower with large NMOS width and current. This two stage buffer topology yields larger output amplitude and lower limitation of operating frequency [6]. In order to improve input sensitivity of the proposed FD, a pair of on-chip spiral inductors which are connected in series with the 50 Ohm source has been used. They can resonate with their total input gate capacitances (CMD1/CMD2, CMC1/CMD2) and boost the effective clock signal swing Q times [7]. Here, Q is equivalent Q of the input circuit and it is required not very high, less than 1.5, to relax the inductor design.

D DB Latch I

Q QB

D DB CLK Latch II

Q QB

OUT1

OUT2 CLK IN+ IN (b) Fig1. Structure of Razavis FD (a) latch (b) divide-by-2 FD with two latches

B. The Proposed Dynamic SCL FD Fig. 2 shows the circuit implementation of a low power consumption dynamic SCL divide-by-2 FD. In contrast with Razavis FD, the proposed FD consists of two same latches and each latch has another two control transistors MC1 and MC2. The addition of MC1 and MC2 helps switch off the latch and shut down any current path in the latch during half the clock cycles. It ensures that sample devices (MS1, MS2) and regenerative hold devices (MH1, MH2) are off during the hold-mode, thereby the dynamic load resistances become larger and the output impedances at Q and QB increase during the regeneration mode. This large output impedance leads to higher output swing. Whats more, the large load resistance makes it reliable to design a lower gm in the latch transistor pairs to drive the load and, in this case, it is possible to design MH1 and MH2 smaller to decrease the parasitic capacitances during the sample-mode, which speeds up the dynamics of the latch. When input signal IN is low, all of the pair of dynamic loads (MD1, MD2), the pair of sample devices (MS1, MS2) and the pair of regenerative hold devices (MH1, MH2) in the master (latch I) are on and latch I is in the sample mode, while all of the devices in the slave (latch II) are off and latch II is in the hold mode. When IN goes high, the

(a)

(b)

(c) Fig2. Structure of the Proposed FD (a) latch (b) the Proposed FDs Buffer (c) divide-by-2 FD with two latches and output buffer



III.

SIMULATION RESULTS

The proposed dynamic SCL frequency divider circuit has been designed in IBM 90nm CMOS process. Fig. 3 shows the layout design. The chip core size is 685m430m. The input sinusoidal clock frequency has been swept across the working frequency range to investigate the upper and lower frequency limits while the minimum input clock signal level required for right operation of divide-by-two function has been swept in order to simulate the input sensitivity. Also, the core power consumption of the proposed FD is calculated by probing the core current. It is found that the proposed dynamic SCL is able to work in a broadband frequency range from 8GHz to 38GHz. A snap shot of the input and output differential signals of the proposed FD is shown in Fig. 4 at an input frequency of 8, 27.3, 33 and 38 GHz. Fig. 5 shows the input sensitivity and the proposed scheme exhibits high sensitivity especially at high input frequencies by the use of on-chip spiral inductors. The minimum input sensitivity is 4mV@16GHz. Due to the half circle working mode, the power consumption is extremely low, as shown in Fig. 6. The maximum power consumption is 1.31mW @38GHz and the minimum power consumption is 0.354mW @16GHz from a supply voltage of 1.2 V.

(b)

(c)

Fig3. The Proposed FDs Layout

(d) Fig4. The Proposed FDs Input/output waveforms in the operating range (a) 8GHz (b) 27.3GHz (c) 33GHz (d) 38GHz

(a)

Fig5. Frequency divider input sensitivity versus input frequency of the Proposed FD



REFERENCES
[1] J.-O. Plouchart, Jonghae Kim; H. Recoules, N. Zamdmer, Yue Tan, M. Sherony, A. Ray, L. Wagner, A power-efficient 33 GHz 2:1 static frequency divider in 0.12-m SOI CMOS, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp.329 332,2003. K.M. Sharaf, A 5mW 19-43 GHz Broadband CMOS FD, National Radio Science Conference , pp.1 8, 2008. Hsien-Ku Chen, Hsien-Jui Chen, Da-Chiang Chang, A mm-Wave CMOS Multimode Frequency Divider , IEEE International SolidState Circuits Conference, pp.280 281, Feb. 2009. Jun-Chau Chien,Liang-Hung Lu, A 40GHz Frequency Divider in 90nm CMOS Technology, IEEE International Solid-State Circuits Conference, pp.544 621, 2007. B. Razavi, K.F. Lee, R.-H. Yan, A 13.4-GHz CMOS frequency divider, IEEE International Solid-State Circuits Conference, pp.176-177, Feb.1994. Shen Yan-junFeng Jun, Design of 1037GHz CMOS divide-by-4 frequency divider, Electronic Design Engineering, pp.79-83,2009. Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Second Edition, Publishing House of Electronics Industry. K.-L.J.Wong, A. Rylyakov, C.-K.K. Yang, IEEE Compound Semiconductor Integrated Circuit Symposium, A Broadband 44-GHz Frequency Divider in 90-nm CMOS, pp.196 199,2005. U. Singh, and M. M. Green, High-Frequency CML Clock Divider in 0.13m CMOS Operating Up to 38GHz, IEEE International SolidState Circuits Conference, pp.1658-1661, Aug. 2005.

[2] [3]

[4]

[5]

Fig6. The Proposed FDs Power Consumption curve

[6] [7] [8]

The performance of this kind of FDs is summarized in Table I. Some previously published papers are also listed for comparison. The proposed FD shows wide frequency locking range, high input sensitivity with low power dissipation. Though the frequency locking range is a bit lower than [4] and [8], but the power dissipation is lower than [8] and the chip area is 0.295 mm2.
TABLE I PERFORMANCE SUMMARY AND COMPARISON

[9]

Ref. [1] [2] [4] [8] [9] This work

CMOSProcess (nm) 120 130 90 90 130 90

Freq. (GHz) 5-33 19-43 4-41 4-44 20-38 8-38 IV.

Supply (V) 2.4 1.5 1.2 1.2 1.8 1.2 CONCLUSION

PD (mW) 22.1 5 0.9 5.28 12 1.31

Area (mm2) 0.028 N/A N/A 0.00076 1 0.295

In this paper, a dynamic SCL divide-by-2 FD with low power consumption and wide frequency locking range is proposed. Analysis shows that the locking range is 8~38GHz and wide enough to cover 27.3~33GHz. The power consumption is from 0.354mW to 1.31mW across 8~38GHz from a supply voltage of 1.2 V. When working during 27.3~33GHz the power consumption is less than 1mW. Whats more, the minimum input sensitivity is 4mV across the operating frequency range. Simulation results show that the presented dynamic SCL FD is suitable used in PLL block of ALMA band-1 receivers or other ultra-wideband, low power applications. ACKNOWLEDGMENT The authors thank the support of Institute of RF- & OEICs (IROI), Southeast University. The authors also thank Zhang Li of IROI for the help with layout checking and design analysis tutoring. Technology from IBM is also appreciated.