EMBEDDED MICROCONTROLLER P89C51RD2 Bluetooth Based Temperature Control system is implemented by using P89C51RD2 microcontroller, which is the 8-bit

t microcontroller developed by Philips. 89C51 Microcontroller: The microcontroller used here is P89C51RD2BN.The expansion of the part number of this microcontroller is given below.

The P89C51RD2BN contains a non-volatile 64KB Flash program memory that is both parallel programmable and serial In-System and In-Application Programmable. In-System Programming (ISP) allows the user to download new code while the microcontroller sits in the application. In-Application Programming (IAP) means that the microcontroller fetches new program code and reprograms itself while in the system. This allows for remote programming over a modem link. A default serial loader (boot loader) program in ROM allows serial InSystem programming of the Flash memory via the UART without the need for a loader in the Flash code. For In-Application Programming, the user program erases and reprograms the Flash memory by use of standard routines contained in ROM. The device supports 6-clock/12-clock mode selection by programming a Flash bit using parallel programming or In-System Programming. In addition, an SFR bit (X2) in the clock control register (CKCON) also selects between 6-clock/12-clock mode. Additionally, when in 6clock mode, peripherals may use either 6 clocks per machine cycle or 12 clocks per machine cycle. This choice is available individually for each peripheral and is selected by bits in the CKCON register. This device is a Single-Chip 8-Bit Microcontroller manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The

instruction set is 100% compatible with the 80C51 instruction set. The device also has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of the P89C51RD2BN make it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. When the 89C51 microcontroller is connected to a crystal oscillator and is powered up, we can observe the frequency on the XTAL2 pins using the oscilloscope.
P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1

Oscillator Frequency f

State 1

State 2

State State 3 4 One Machine Cycle

State 5

State 6

CPU clock cycles The time to execute the instruction is calculated by using the following expression, T (inst) = (MC Cn) / (crystal frequency) MC Number of Machine Cycles for an instruction to execute and Cn is the number of clock cycles for one machine cycle. For 89C51RD2BN the number of clock cycles for one machine cycle is 12. For example, If the number of machine cycles to execute a instruction is 1 and the oscillator frequency used is 11.0592MHz, the time to execute an instruction is 1.085s. Basic Features of 89C51 80C51 Central Processing Unit On-chip Flash Program Memory with In-System Programming (ISP) In Application Programming (IAP) capability Boot ROM contains low-level Flash programming routines for downloading via the UART Supports 6-clock/12-clock mode via parallel programmer (default clock mode after Chip Erase is 12-clock 6-clock/12-clock mode Flash bit erasable and programmable via ISP 6-clock/12-clock mode programmable on-the-fly by SFR bit

Peripherals (PCA, timers, UART) may use either 6-clock or 12-clock mode while the CPU is in 6-clock mode Speed up to 20 MHz with 6-clock cycles per machine cycle (40 MHz equivalent performance); up to 33 MHz with 12 clocks per machine cycle Fully static operation RAM expandable externally to 64-kilo bytes Four interrupt priority levels Seven interrupt sources Four 8-bit I/O ports Full-duplex enhanced UART Framing error detection Automatic address recognition Power control modes Clock can be stopped and resumed Idle mode Power down mode Programmable clock-out pin Second DPTR register Asynchronous port reset Low EMI (inhibit ALE) Programmable Counter Array (PCA) PWM Capture/compare

Pin Description

Examining the following figure, note that of the 40 pins a total of 32 pins are set aside for the four ports P0, P1, P2 and P3, where each port takes 8 pins. The rest of the pins are designated as Vcc, GND, XTAL1, XTAL2, RST, EA, ALE, and PSEN. Of these 8 pins, all 8051

derivatives use six of them. In other words, they must be connected in order for the system to work.

Pin Diagram of 89C51 Microcontroller 18: P1.0 to P1.7 (Port 1): Each of these pins can be used as either input or output according to your needs. Port 1 is an 8-bit bi-directional I/O port with internal pull-ups on all pins. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pullups. Each pin of Port1 has an alternate function

Pin 1: T2 (P1.0)

- Clock input of counter 0

Pin 2: T2EX (P1.1) - Timer/Counter 2 Reload / Capture / Direction Control Pin 3: ECI (P1.2) - External Clock Input to the PCA

Pin 4: CEX0 (P1.3) - External I/O for PCA module 0 Pin 5: CEX1 (P1.4) - External I/O for PCA module 1

Pin 6: CEX2 (P1.5) - External I/O for PCA module 2 Pin 7: CEX3 (P1.6) - External I/O for PCA module 3 Pin 8: CEX4 (P1.7) - External I/O for PCA module 4

9: RST (Reset Signal): High logical state on this input halts the MCU and clears all the registers. Bringing this pin back to logical state zero starts the program a new as if the power had just been turned on. In another words, positive voltage impulse on this pin resets the MCU. Depending on the device's purpose and environs, this pin is usually connected to the push-button, reset-upon-start circuit or a brown out reset circuit. 10-17: P3.0 to P3.7 (Port 3): As with Port 1, each of these pins can be used as universal input or output. However, each pin of Port 3 has an alternative function: Pin 10: RxD(P3,0) - Serial input for asynchronous communication Pin 11: TxD(P3.1) - Serial output for asynchronous communication Pin 12: INT0(P3.2) - Input for interrupt 0 Pin 13: INT1(P3.3) - Input for interrupt 1 Pin 14: T0(P3.4) Pin 15: T1(P3.5) Pin 16: WR(P3.6) Pin 17: RD(P3.7) - Clock input of counter 0 - Clock input of counter 1 - Signal for writing to external RAM memory - Signal for reading from external RAM memory

18-19: XTAL2 and XTAL1 (Crystal input and output): Input and output of internal oscillator. Quartz crystal controlling the frequency commonly connects to these pins. 20: VSS: Ground 21- 28: P2.0 to P2.7 (Port 2): If external memory is not present, pins of Port 2 act as universal input/output. If external memory is connected, this is the location of the higher address byte, i.e. addresses A8 A15. It is important to note that in cases when not all the 8 bits are used for addressing the memory (i.e. memory is smaller than 64kB), the rest of the unused bits are not available as input/output.

29: PSEN (Program Store Enable): MCU activates this bit (brings to low state) upon each reading of byte instruction from program memory. If external ROM is used for storing the program, PSEN is directly connected to its control pins. 30: ALE (Address Latch Enable): Before each reading of the external memory, MCU sends the lower byte of the address register (addresses A0 A7) to port P0 ,and activates the output ALE. External Chip (eg: 74HC373), memorizes the state of port P0 upon receiving a signal from ALE pin, and uses it as part of the address for memory chip. During the second part of the MCU cycle, signal on ALE is off, and port P0 is used as Data Bus. In this way, by adding only one integrated circuit, data from port can be multiplexed and the port simultaneously used for transferring both addresses and data. 31: EA (External Access Enable): Bringing this pin to the logical state zero designates the ports P2 and P3 for transferring addresses regardless of the presence of the internal memory. This means that even if there is a program loaded in the MCU it will not be executed, but the one from the external ROM will be used instead. Conversely, bringing the pin to the high logical

state causes the controller to use both memories, first the internal, and then the external (if present). 32-39: P0.7 to P0.0 (Port 0): Similar to Port 2, pins of Port 0 can be used as universal input/output, if external memory is not used. If external memory is used, P0 behaves as address output (A0 A7) when ALE pin is at high logical level, or as data output (Data Bus) when ALE pin is at low logical level. 40: VCC: Power +5V

Architecture of 89C51 Microcontroller The architecture of the 8051 family of microcontrollers (8051 derivatives) is referred to as the MCS-51 architecture (Micro Controller Series 51), or sometimes simply as MCS-51. The block diagram of 89C51 microcontroller is shown below.

Architecture of 89C51 microcontroller

ACCUMULATOR (ACC): Accumulator is a general-purpose register, which stores runtime results. Before performing any operation upon an operand, operand has to be stored in the accumulator. Results of arithmetical operations are also stored in the accumulator. When transferring data from one register to another, it has to go through the accumulator. Due to its versatile role, this is the most frequently used register, essential part of every MCU.

B REGISTER: B Register is used along with the Accumulator for multiplication and division. This B register provides temporary storage space for the result of multiplication & division operation. Instructions of multiplication and division can be applied only to operands located in registers A and B. Other instructions can use this register as a secondary accumulator (A).

PORTS: Term "port" refers to a group of pins on a microcontroller which can be accessed simultaneously, or on which we can set the desired combination of zeros and ones, or read from them an existing status. Ports represent physical connection of Central Processing Unit with an outside world. Microcontroller uses them in order to monitor or control other components or devices. 89C51 has 4 ports; with each port have 8-bit length. All the ports are bit and byte addressable. Port 0 (P0): Port 0 has two-fold role: If external memory is used, P0 behaves as address output (A0 A7) when ALE pin is at high logical level, or as data output (Data Bus) when ALE pin is at low logical level, otherwise all bits of the port are either input or output. Another feature of this port comes to play when it has been designated as output. Unlike other ports, Port 0 lacks the "pull up" resistor (resistor with +5V on one end). This seemingly insignificant change has the following consequences:

When designated as input, pin of Port 0 acts as high impedance offering the infinite input resistance with no "inner" voltage. When designated as output, pin acts as "open drain". Clearing a port bit grounds the appropriate pin on the case (0V). Setting a port bit makes the pin act as high impedance. Therefore, to get positive logic (5V) at output, external "pull up" resistor needs to be added for connecting the pin to the positive pole.

Therefore, to get one (5V) on the output, external "pull up" resistor needs to be added for connecting the pin to the positive pole. Port 1 (P1): Port 1 is I/O port. Having the "pull up" resistor, Port 1 is fully compatible with TTL circuits. The alternate functions of Port1 are

Pin

Alternate Name

Alternate Function

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

T2 T2EX ECI CEX0 CEX1 CEX2 CEX3 CEX4

Serial input Serial output External interrupt 0 External interrupt 1 Timer 0 external input Timer 1 external input Signal write to external memory Signal read from external memory

Port 2 (P2): When using external memory, this port contains the higher address byte (addresses A8A15), similar to Port 0. Otherwise, it can be used as universal I/O port.

Port 3 (P3): Beside its role as universal I/O port, each pin of Port 3 has an alternate function. In order to use one of these functions, the pin in question has to be designated as input, i.e. the appropriate bit of register P3 needs to be set. By selecting one of the functions the other one is disabled. From a hardware standpoint, Port 3 is similar to Port 0. The alternate functions of Port 3 is given below

Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

Alternate Name RXD TXD INT0 INT1 T0 T1 WR RD

Alternate Function Serial input Serial output External interrupt 0 External interrupt 1 Timer 0 external input Timer 1 external input Signal write to external memory Signal read from external memory

Data Pointer (DPTR) : The Data pointer register is made up of two 8 bit registers, named DPH (Data Pointer High) and DPL (Data Pointer Low). These registers are used to give addresses of the internal or external memory. The DPTR is under the control of program. DPTR is also

manipulated as one 16 bit register, DPH & DPL are each assigned an address. The 89C51 microcontroller has additional DPTR. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS (bit0 in AUXR1) that allows the program code to switch between them. Stack Pointer (SP) : The stack refers to an area of internal RAM that is used in conjunction with certain opcodes to store and retrieve data quickly. The register used to access the stack is called Stack Pointer. The 8 bit stack pointer register is used by the 89C51 to hold an internal RAM address that is called then top of the stack. The stack pointer increments before storing the data on the stack. As retrieved from the stack the SP is decremented by one. The number in Stack Pointer points to the location of the last "valid" address within the Stack. With the beginning of every new routine, Stack Pointer increases by 1; upon return from routine, SP decreases by 1. Upon reset (or turning the power on), the stack pointer contains the value 07h. Program Counter (PC): Used to access code memory. Program counter always points to the address of the next instruction in memory to be executed. Upon reset (or turning the power on), the program counter resets to the starting location of the program. Instruction Register: When an instruction is fetched from the Flash memory, it is loaded in the instruction register. Timing & Control unit: The timing and control unit synchronizes the operation of the microcontroller and generates control signals necessary for communication between the microcontroller and the peripherals. Program Status Word (PSW): The Program Status Word (PSW) register is an 8 bit register. It is also referred to as the flag register. It contains the math flags, user program flag F0, and the register select bits that identify which of the four general purpose register banks is currently in use by the program. Oscillator: Oscillator circuit is used for providing a microcontroller with a clock. Clock is needed so that microcontroller could execute a program or program instructions. Stable pace provided by the oscillator allows harmonious and synchronous functioning of all other parts of MCU. The manufacturers make available 89C51 designs that can run at specified maximum and minimum frequencies, typically 1 megahertz to 33 megahertz. Minimum frequencies imply that

some internal memories are dynamic and must always operate above a minimum frequency or data will be lost. Interrupts: An interrupt is a signal from a device attached to a computer or from a program within the computer that causes the main program that operates the computer to stop and points out what to do next. In general, there are hardware interrupts and software interrupts. A hardware interrupt is related to the hardware of the system. For example, when an I/O operation is completed such as reading some data into the computer from a keyboard interrupt the main program. As the name implies the software interrupts related to the software of the system. It occurs when an application program terminates or requests certain services from the operating system. Timers/Counters: Timers are usually the most complicated parts of a microcontroller. Physically, timer is a register whose value is continually increasing to FFFFh, and then it starts all over again: 0h, 1h, 2h, 3h, 4h...FFFFh....0h, 1h, 2h, 3h......etc. The 89C51 MCU clock employs a quartz crystal. As this frequency is highly stable and accurate, it is ideal for time measuring. Since one instruction takes 12 oscillator cycles to complete, the math is easy. 89C51 has three Timers/Counters marked as T0, T1 & T2. Their purpose is to measure time and count external occurrences, but can also be used as clock in serial communication purpose called as, Baud Rate. Serial Port: Serial port is used to provide communication among two devices. Serial data communication has been widely used for long distance communication because of the ease and the economy of using only one wire to transmit data. Serial port is also referred as RS232 port. RS232 is a asynchronous way of communication. Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. Instead, the sender and receiver must agree on timing parameters in advance and special bits are added to each word, which are used to synchronize the sending and receiving units. When a word is given to the UART for Asynchronous transmissions, a bit called the "Start Bit" is added to the beginning of each word that is to be transmitted. The Start Bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter.
TRANSMITTER USES AN INTERNAL CLOCK TO DETERMINE WHEN TO SEND EACH BIT

RECEIVER DETECTS THE FALLING EDGE OF START, THEN USES ITS INTERNAL CLOCK TO READ THE FOLLOWING BITS

Data (61h )
START BIT 0 BIT BIT 7 STOP BIT

ASYNCHRONOUS TRANSMISSION SEND LSB FIRST Asynchronous Transmission

Memory Organization:

RAM (Data Memory) RAM is used for storing temporary data and auxiliary results generated during the runtime. The P89C51RD2BN has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 768 bytes expanded RAM (ERAM). The four segments are:

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. 4. The 768-bytes expanded RAM (ERAM, 00H 2FFH) are indirectly accessed by move external instruction, MOVX, and with the EXTRAM bit in the AUXR register cleared.

RAM Organization

The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. The ERAM can be accessed by indirect addressing, with EXTRAM bit in the AUXR register cleared and MOVX instructions. This part of memory is physically located onchip, logically occupies the first 7936-bytes of external data memory. With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not affect portsP0, P3.6 (WR) and P3.7 (RD). P2 SFR is output during external addressing. The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM.

Internal RAM Architecture

Flash Memory (Program Memory): 89C51 have built-in 64-kilo bytes of Flash memory. The P89C51RD2BN Flash memory augments EPROM functionality with in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Chip Erase operation will erase the entire program memory. The Block Erase function can erase any Flash block. In-system programming and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89C51RD2BN Flash reliably stores memory contents even after 10,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces

reliable cycling. The P89C51RD2BN uses a +5 V VPP supply to perform the Program/Erase algorithms.

89C51 Program Memory

Special Function Registers: Special Function Register (SFR) can be seen as a sort of control panel for managing and monitoring the microcontroller. Every register and each of the belonging bits has its name, specified address in RAM and strictly defined role (e.g. controlling the timer, interrupt, serial communication, etc). Although there are 128 available memory slots for allocating SFR registers. The rest has been left open intentionally to allow future upgrades while retaining the compatibility with earlier models. This fact makes possible to use programs developed for obsolete models long ago. SYMBOL DESCRIPTION ACC Accumulator DIRECT ADDRESS E0H

AUXR AUXR1 B CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 CCON CH CKCON CL CMOD DPH DPL IE IP IPH P0 P1 P2

Auxiliary Auxiliary 1 B register

8EH A2H F0H

Module 0 Capture High FAH Module 1 Capture High FBH Module 2 Capture High FCH Module 3 Capture High FDH Module 4 Capture High FEH Module 0 Capture Low Module 1 Capture Low Module 2 Capture Low Module 3 Capture Low Module 4 Capture Low Module 0 Mode Module 1 Mode Module 2 Mode Module 3 Mode Module 4 Mode PCA Counter Control PCA Counter High Clock control PCA Counter Low PCA Counter Mode Data Pointer High Data Pointer Low Interrupt Enable 0 Interrupt Priority Interrupt Priority High Port 0 Port 1 Port 2 EAH EBH ECH EDH EEH DAH DBH DCH DDH DEH D8H F9H 8FH E9H D9H 83H 82H A8H B8H B7H 80H 90H A0H

P3 PCON PSW RCAP2H RCAP2L SADDR SADEN SBUF SCON SP TCON T2CON T2MOD TH0 TH1 TH2 TL0 TL1 TL2 TMOD WDTRST

Port 3 Power Control Program Status Word Timer 2 Capture High Timer 2 Capture Low Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control Timer 2 Control Timer 2 Mode Control Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 Timer Mode Watchdog Timer Reset

B0H 87H D0H CBH CAH A9H B9H 99H 98H 81H 88H C8H C9H 8CH 8DH CDH 8AH 8BH CCH 89H A6H

Addressing Modes and Instruction Set The CPU can access data in various ways. The data could be in a register, or in memory, or to be provided as an immediate value. These various ways of accessing data are called

addressing modes. The various addressing modes are determined when it is designed and therefore cannot be changed by the programmer. The 89C51 provide a total of five distinct addressing modes. They are:

Immediate Addressing: Immediate addressing is so-named because the value to be stored in memory immediately follows the operation code in memory. Example: MOV A, #20H

Direct Addressing: In Direct addressing the value to be stored in memory is obtained by directly retrieving it from another memory location. Example: MOV A, 30H

Register Addressing: Register addressing accesses the eight working registers (R0 - R7) of the selected register bank. Example: MOV A, R0

Register indirect Addressing: Register indirect addressing is a very powerful addressing mode, which in many cases provides an exceptional level of flexibility. Indirect addressing is also the only way to access the extra 128 bytes of Internal RAM. Example: MOV A, @R0

Indexed Addressing: Indexed addressing mode is widely used in accessing data elements of look-up table entries located in the program ROM space of the 89C51. Example: MOVC A, @A+DPTR, MOVC A, @A+PC

The 89C51 instruction set includes 111 instructions, 49 of which are single-byte, 45 twobyte and 17 three-byte instructions. The instruction set is divided into four functional groups: Data transfer - None of the data transfer operations affects the PSW flag settings except a POP or MOV directly to the PSW. Arithmetic - The 89C51 microcontrollers have four basic mathematical operations. Only 8-bit operations using unsigned arithmetic are supported directly.

Logic - The 89C51 perform logic operations on both bit and byte operands Control transfer - All control transfer operations, some upon a specific condition, cause the program execution to continue a non-sequential location in program memory.

Data Transfer Instructions:

Mnemonic

Description

Byte

Cycle

Opcode

MOV A, R0 MOV A, R1 MOV A, R2 MOV A, R3 MOV A, R4 MOV A, R5 MOV A, R6 MOV A, R7 MOV A, direct MOV A, @R0 MOV A, @R1 MOV A, #data MOV R0, A MOV R1, A MOV R2, A MOV R3, A MOV R4, A MOV R5, A MOV R6, A MOV R7, A MOV R0, direct MOV R1, direct MOV R2, direct MOV R3, direct MOV R4, direct MOV R5, direct MOV R6, direct MOV R7, direct MOV R0, #data MOV R1, #data MOV R2, #data MOV R3, #data MOV R4, #data

Move Register R0 to Accumulator Move Register R1 to Accumulator Move Register R2 to Accumulator Move Register R3 to Accumulator Move Register R4 to Accumulator Move Register R5 to Accumulator Move Register R6 to Accumulator Move Register R7 to Accumulator Move direct byte to A Move indirect RAM to A Move indirect RAM to A Move immediate data to A Move Accumulator to Register R0 Move Accumulator to Register R1 Move Accumulator to Register R2 Move Accumulator to Register R3 Move Accumulator to Register R4 Move Accumulator to Register R5 Move Accumulator to Register R6 Move Accumulator to Register R7 Move direct byte to Register R0 Move direct byte to Register R1 Move direct byte to Register R2 Move direct byte to Register R3 Move direct byte to Register R4 Move direct byte to Register R5 Move direct byte to Register R6 Move direct byte to Register R7 Move immediate data to Register R0 Move immediate data to Register R1 Move immediate data to Register R2 Move immediate data to Register R3 Move immediate data to Register R4

1 1 1 1 1 1 1 1 2 1 1 2 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1

E8 E9 EA EB EC ED EE EF E5 E6 E7 74 F8 F9 FA FB FC FD FE FF A8 A9 AA AB AC AD AE AF 78 79 7A 7B 7C

MOV R5, #data MOV R6, #data MOV R7, #data MOV direct, A MOV direct, R0 MOV direct, R1 MOV direct, R2 MOV direct, R3 MOV direct, R4 MOV direct, R5 MOV direct, R6 MOV direct, R7 MOV direct, direct MOV direct, @R0 MOV direct, @R1 MOV direct, #data MOV @R0, A MOV @R1, A MOV @R0, direct MOV @R1, direct MOV @R0, #data MOV @R1, #data MOV DPTR, #da16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @R0 MOVX A, @R1 MOVX A, @DPTR MOVX @R0, A MOVX @R1, A MOVX @DPTR, A PUSH direct POP direct XCH A, R0 XCH A, R1 XCH A, R2 XCH A, R3 XCH A, R4

Move immediate data to Register R5 Move immediate data to Register R6 Move immediate data to Register R7 Move Accumulator to direct byte Move Register R0 to direct byte Move Register R1 to direct byte Move Register R2 to direct byte Move Register R3 to direct byte Move Register R4 to direct byte Move Register R5 to direct byte Move Register R6 to direct byte Move Register R7 to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move indirect RAM to direct byte Move immediate data to direct byte Move A to indirect RAM Move A to indirect RAM Move direct byte to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Move immediate data to indirect RAM Load data pointer with 16-bit Move code byte related to Data pointer to Accumulator Move code byte related to PC to A Move External RAM (8-bit) to A Move External RAM (8-bit) to A Move External RAM (16-bit) to A Move A to External RAM (8-bit) Move A to External RAM (8-bit) Move A to External RAM (16-bit) Push direct byte onto stack Pop direct byte from stack Exchange Register R0 with A Exchange Register R1 with A Exchange Register R2 with A Exchange Register R3 with A Exchange Register R4 with A

2 2 2 2 2 2 2 2 2 2 2 2 3 2 2 3 1 1 2 2 2 2 3 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1

1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1

7D 7E 7F F5 88 89 8A 8B 8C 8D 8E 8F 85 86 87 75 F6 F7 A6 A7 76 77 90 93 83 E2 E3 E0 F2 F3 F0 C0 D0 C8 C9 CA CB CC

XCH A, R5 XCH A, R6 XCH A, R7 XCH A, direct XCH A, @R0 XCH A, @R1 XCHD A, @R0 XCHD A, @R1

Exchange Register R5 with A Exchange Register R6 with A Exchange Register R7 with A Exchange direct byte with A Exchange indirect RAM with A Exchange indirect RAM with A Exchange lower-order nibble of indirect RAM with A Exchange lower-order nibble of indirect RAM with A

1 1 1 2 1 1 1 1

1 1 1 1 1 1 1 1

CD CE CF C5 C6 C7 D6 D7

Arithmetic Instructions:

Mnemonic ADD A, R0 ADD A, R1 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7 ADD A, direct ADD A, @R0 ADD A, @R1 ADD A, #data ADDC A, R0 ADDC A, R1 ADDC A, R2 ADDC A, R3 ADDC A, R4 ADDC A, R5 ADDC A, R6 ADDC A, R7 ADDC A, direct ADDC A, @R0 ADDC A, @R1 ADDC A, #data SUBB A, R0

Description Add Register R0 to Accumulator Add Register R1 to Accumulator Add Register R2 to Accumulator Add Register R3 to Accumulator Add Register R4 to Accumulator Add Register R5 to Accumulator Add Register R6 to Accumulator Add Register R7 to Accumulator Add direct byte to Accumulator Add indirect RAM in R0 to A Add indirect RAM in R1 to A Add immediate data to A Add Register R0 to A with carry Add Register R1 to A with carry Add Register R2 to A with carry Add Register R3 to A with carry Add Register R4 to A with carry Add Register R5 to A with carry Add Register R6 to A with carry Add Register R7 to A with carry Add direct byte to A with carry Add indirect RAM to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract Register R0 from A with borrow

Byte 1 1 1 1 1 1 1 1 2 1 1 2 1 1 1 1 1 1 1 1 2 1 1 2 1

Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Opcode 28 29 2A 2B 2C 2D 2E 2F 25 26 27 24 38 39 3A 3B 3C 3D 3E 3F 35 36 37 34 98

SUBB A, R1 SUBB A, R2 SUBB A, R3 SUBB A, R4 SUBB A, R5 SUBB A, R6 SUBB A, R7 SUBB A, direct SUBB A, @R0 SUBB A, @R1 SUBB A, #data INC A INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7 INC direct INC @R0 INC @R1 DEC A DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7

Subtract Register R1 from A with borrow Subtract Register R2 from A with borrow Subtract Register R3 from A with borrow Subtract Register R4 from A with borrow Subtract Register R5 from A with borrow Subtract Register R6 from A with borrow Subtract Register R7 from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment Accumulator Increment Register R0 Increment Register R1 Increment Register R2 Increment Register R3 Increment Register R4 Increment Register R5 Increment Register R6 Increment Register R7 Increment direct byte Increment indirect RAM Increment indirect RAM Decrement Accumulator Decrement Register R0 Decrement Register R1 Decrement Register R2 Decrement Register R3 Decrement Register R4 Decrement Register R5 Decrement Register R6 Decrement Register R7

1 1 1 1 1 1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

99 9A 9B 9C 9D 9E 9F 95 96 97 94 04 08 09 0A 0B 0C 0D 0E 0F 05 06 07 14 18 19 1A 1B 1C 1D 1E 1F

DEC direct DEC @R0 DEC @R1 INC DPTR MUL AB

DIV AB DA A

Decrement direct byte Decrement indirect RAM Decrement indirect RAM Increment data pointer Multiply A and B and put the lowerbyte of the product in A and the higher-byte in B. Divide A by B and put the Quotient in A and the Remainder in B Adjust the sum of two packed numbers found in A

2 1 1 1 1

1 1 1 2 4

15 16 17 A3 A4

1 1

4 1

84 D4

Logical Instructions: Mnemonic ANL A, R0 ANL A, R1 ANL A, R2 ANL A, R3 ANL A, R4 ANL A, R5 ANL A, R6 ANL A, R7 ANL A, direct ANL A, @R0 ANL A, @R1 ANL A, #data ANL direct, A ANL direct, #data ORL A, R0 ORL A, R1 ORL A, R2 ORL A, R3 ORL A, R4 ORL A, R5 ORL A, R6 ORL A, R7 ORL A, direct ORL A, @R0 ORL A, @R1 ORL A, #data Description AND Register R0 to Accumulator AND Register R1 to Accumulator AND Register R2 to Accumulator AND Register R3 to Accumulator AND Register R4 to Accumulator AND Register R5 to Accumulator AND Register R6 to Accumulator AND Register R7 to Accumulator AND direct byte to A and put the result in A AND indirect RAM to A AND indirect RAM to A AND immediate data to A AND Accumulator to direct byte and put the result in memory AND immediate data to direct byte OR Register R0 to Accumulator OR Register R1 to Accumulator OR Register R2 to Accumulator OR Register R3 to Accumulator OR Register R4 to Accumulator OR Register R5 to Accumulator OR Register R6 to Accumulator OR Register R7 to Accumulator OR direct byte to A and put the result in A OR indirect RAM to A OR indirect RAM to A OR immediate data to A Byte 1 1 1 1 1 1 1 1 2 1 1 2 2 3 1 1 1 1 1 1 1 1 2 1 1 2 Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 Opcode 58 59 5A 5B 5C 5D 5E 5F 55 56 57 54 52 53 48 49 4A 4B 4C 4D 4E 4F 45 46 47 44

ORL direct, A ORL direct, #data XRL A, R0 XRL A, R1 XRL A, R2 XRL A, R3 XRL A, R4 XRL A, R5 XRL A, R6 XRL A, R7 XRL A, direct XRL A, @R0 XRL A, @R1 XRL A, #data XRL direct, A XRL direct, #data CLR A CPL A RL A RLC A RR A RRC A SWAP A

OR Accumulator to direct byte and put the result in memory OR immediate data to direct byte Exclusive OR Register R0 to A Exclusive OR Register R1 to A Exclusive OR Register R2 to A Exclusive OR Register R3 to A Exclusive OR Register R4 to A Exclusive OR Register R5 to A Exclusive OR Register R6 to A Exclusive OR Register R7 to A Ex - OR direct byte to A Exclusive OR indirect RAM to A Exclusive OR indirect RAM to A Exclusive OR immediate data to A Exclusive OR Accumulator to direct byte and put the result in memory Ex - OR immediate data to direct byte Clear Accumulator Complement Accumulator Rotate Accumulator Left Rotate Accumulator left through carry Rotate Accumulator Right Rotate Accumulator Right through carry Swap the nibbles of Accumulator

2 3 1 1 1 1 1 1 1 1 2 1 1 2 2 3 1 1 1 1 1 1 1

1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1

42 43 68 69 6A 6B 6C 6D 6E 6F 65 66 67 64 62 63 E4 F4 23 33 03 13 C4

Boolean Variable Manipulation Instructions: Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C Description Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry OR direct bit to carry flag OR complement of direct bit to carry Move direct bit to carry flag Move carry flag to direct bit Byte 1 2 1 2 1 2 2 2 2 2 2 2 Cycle 1 1 1 1 1 1 2 2 2 2 1 2 Opcode C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92

Program and Machine Control Instructions: Mnemonic Description ACALL addr11 ACALL addr11 ACALL addr11 ACALL addr11 ACALL addr11 ACALL addr11 ACALL addr11 ACALL addr11 LCALL addr16 RET RETI AJMP addr11 AJMP addr11 AJMP addr11 AJMP addr11 AJMP addr11 AJMP addr11 AJMP addr11 AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel CJNE A, direct, rel Absolute Subroutine call (If the calling Address is within FFh) Calling Address is within 1FFh Calling Address is within 2FFh Calling Address is within 3FFh Calling Address is within 4FFh Calling Address is within 5FFh Calling Address is within 6FFh Calling Address is within 7FFh Long Subroutine call Return from Subroutine Return from Interrupt Absolute jump (If the jumping Address is within 0FFh) Absolute jump (If the jumping Address is within 0FFh) Absolute jump (If the jumping Address is within 1FFh) Absolute jump (If the jumping Address is within 2FFh) Absolute jump (If the jumping Address is within 3FFh) Absolute jump (If the jumping Address is within 4FFh) Absolute jump (If the jumping Address is within 5FFh) Absolute jump (If the jumping Address is within 6FFh) Long jump Short jump to relative address Jump indirect relative to DPTR Jump if Accumulator is zero Jump if Accumulator is not zero Jump if carry flag is set Jump if carry flag is reset Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct byte to A and jump if not equal

Byte 2 2 2 2 2 2 2 2 3 1 1 2 2 2 2 2 2 2 2 3 2 1 2 2 2 2 3 3 3 3

Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Opcode 11 31 51 71 91 B1 D1 F1 12 22 32 01 21 41 61 81 A1 C1 E1 02 80 73 60 70 40 50 20 30 10 B5

CJNE A, #data, rel CJNE R0, #data, rel CJNE R1, #data, rel CJNE R2, #data, rel CJNE R3, #data, rel CJNE R4, #data, rel CJNE R5, #data, rel CJNE R6, #data, rel CJNE R7, #data, rel CJNE @R0, #data, rel CJNE @R1, #data, rel DJNZ R0, rel DJNZ R1, rel DJNZ R2, rel DJNZ R3, rel DJNZ R4, rel DJNZ R5, rel DJNZ R6, rel DJNZ R7, rel DJNZ direct, rel NOP

Compare immediate data to A and jump if not equal Compare immediate data to Register R0 and jump if not equal Compare immediate data to Register R1 and jump if not equal Compare immediate data to Register R2 and jump if not equal Compare immediate data to Register R3 and jump if not equal Compare immediate data to Register R4 and jump if not equal Compare immediate data to Register R5 and jump if not equal Compare immediate data to Register R6 and jump if not equal Compare immediate data to Register R7 and jump if not equal Compare immediate data to RAM and jump if not equal Compare immediate data to RAM and jump if not equal Decrement Register R0 and jump if not zero Decrement Register R1 and jump if not zero Decrement Register R2 and jump if not zero Decrement Register R3 and jump if not zero Decrement Register R4 and jump if not zero Decrement Register R5 and jump if not zero Decrement Register R6 and jump if not zero Decrement Register R7 and jump if not zero Decrement direct byte and jump if not zero No Operation

3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 3 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1

B4 B8 B9 BA BB BC BD BE BF B6 B7 D8 D9 DA DB DC DD DE DF D5 00

Liquid Crystal Display (LCD) Liquid crystals are a phase of matter whose order is intermediate between that of a liquid and that of a crystal. The molecules are typically rod-shaped organic matters about 25 Angstroms in length and their ordering is a function of temperature. The molecular orientation can be controlled with applied electric fields. LCD is made up of two sheets of polarizing material with the liquid crystal solution between them. An electric current passed through the liquid causes the crystals to align so that light cannot pass through them, which results in display of character as per the applied voltage in its data lines. The driver is provided to drive the LCD. It stores the display data transferred from the microcontroller in the internal display RAM and generates dot matrix liquid crystal driving signals. Each bit data of display RAM corresponds to on/off state of a dot of a liquid crystal display.

LCD pin description

LCD is used in widespread applications replacing LEDs (Seven segment LEDs or other multisegment LEDs) nowadays. This is due to the following reasons:

1. The declining prices of LCDs. 2. The ability to display numbers, characters, and graphics. This is in contrast to LEDs, which are limited to numbers and a few characters.

3. Incorporation of a refreshing controller into the LCD, thereby relieving the CPU of the task of refreshing the LCD. 4. Ease of programming for characters and graphics.

Pin Description:

Pin 1 2 3 4

Symbol GND VCC V0 RS

I/O ---I Ground

Description

+5V Power Supply LCD driving voltage RS = 0 to select command register RS = 1 to select data register

RW

RW = 0 for write RW = 1 for read

6 7-14 15 16

EN D0-D7 VCC GND

I I/O ---

Enable The 8-bit Data Bus +5V Power Supply Ground

VCC, GND AND V0: While VCC and VSS provide +5V and ground, respectively, V0 is used for controlling LCD contrast. RS (Register Select): If RS = 0, the instruction command code register is selected, allowing the user to send a command such as clear display, cursor at home, etc. If RS = 1, the data register is selected, allowing the user to send data to be displayed on the LCD. RW (Read/Write): RW allows the user to write information to the LCD or read information from it. RW=1 when reading; RW=0 when writing. EN (Enable): The LCD to latch information presented to its data pins uses the enable pin. When data is supplied to data pins, a high to low pulse must be applied to this pin in order for the LCD to latch in the data present at the data pins.

D0 D7: The 8-bit data pins, are used to send information to the LCD or read the contents of the LCDs internal registers. To display letters and numbers, we send ASCII codes for the letters AZ, a-z, and numbers 0-9 to these pins while making RS = 1.

89C51 Interfacing with LCD