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INDEX

CHAPTER1. INTRODUCTION CHAPTER2. DESCRIPTION OF HARDWARE COMPONENTS 2.1 LPC2103


2.1.1 Introduction 2.1.2 Features 2.1.3 Applications 2.1.4 Architectural overview 2.1.5 Block Diagram 2.1.6 Pin Description of LPC2103 2.1.7 GPIO 2.1.8 Pin connect block

2.2 POWER SUPPLY

2.2.1 Introduction 2.2.2 Power Supply Circuit 2.2.3 Transformer 2.2.4 Rectifier 2.2.5 Filter capacitor 2.2.6 Regulator

2.3 DTMF DECODER (HT9170B) 2.3.1 Features 2.3.2 Block diagram 2.3.3 Functional description 2.3.4 Timing diagram 2.3.5 Applications

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2.4 HARD WARE

2.4.1 Wireless camera 2.4.2 MAX232 2.4.4 L293D 2.4.5 DC GARE Motor

CHAPTER3. CIRCUITS AND THEIR OPERATION

3.1 Circuit diagram 3.2 Operation of circuit

CHAPTER4. SOFTWARE DEVELOPMENT

4.1.1 Introduction 4.1.2 Tools used

CHAPTER 5. RESULTS AND CONCLUSION

5.1 Advantages 5.2 Disadvantages 5.3 Applications 5.4 Conclusion

REFERENCES

Mobile SPY Robot Using Wireless webcam

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INTRODUCTION:
We cannot forget 9/11 when 101 people including nine foreigners and 14 policemen have lost their lives while about 300 people were injured in the worst terror attack seen in the country in which desperate men fired indiscriminately at people. Being an ex defense person, my blood was boiling as our brave solders were fighting the militants to free all the hostages from Mumbai hotels. It struck an idea in my mind, why cant we make a robot to tackle such type of situation.

Out new Combat robot is pc operated , it has got two barrel turret through bullet can be fired, pc camera in synchronization with the turret can rotate up and down ,left and right up to a safe firing limit. turret and camera mechanism has been installed on my spy robot vehicle, which has all the function like tank, Turing to any angle on its axis, moving forward and reverse turning left and right, running instantly into reverse direction.

This robot is mobile operated self powered, and has all the controls like a normal car. A pair of laser gun has been installed on it, so that it can fire on enemy remotely when required this is not possible until a wireless camera is installed. Wireless camera will send real time video and audio signals which could be seen on a remote monitor and action can be taken accordingly. It can silently enter into enemy area and send us all the information through its tiny camera eyes. It is designed for, fighting as well as suicide attack.

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BLOCK DIAGRAM:

POWER SUPPLY

L P C 2 1

U L N 2 0 0 3

MOTOR1

MOTOR2

MOBILE HEAD PHONE

DTMF HT9170

0 3

U L N 2 0 0 3
WIRELESS WEBCAM

MOTOR1

MOTOR2

RELAY

LASER GUN

DESCRIPTION OF HARDWARE COMPONENTS:

LPC2103
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1. General description
The LPC2101/2102/2103 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of embedded high-speed ash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.

Due to their tiny size and low power consumption, the LPC2101/2102/2103 are ideal for applications where miniaturization is a key requirement. A blend of serial communications interfaces ranging from multiple UARTs, SPI to SSP and two I2C-buses, combined with on-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication gateways and protocol converters. The superior performance also makes these devices suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved 10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems.

2.

Features
16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package. 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip ash program memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation. ISP/IAP via on-chip bootloader software. Single ash sector or full chip erase in 100 ms and programming of 256 bytes in 1 ms. EmbeddedICE RT offers real-time debugging with the on-chip RealMonitor software. The 10-bit A/D converter provides eight analog inputs, with conversion times as low as s to minimize interrupt overhead. Two 32-bit timers/external event counters with combined seven capture and seven compare channels. Two 16-bit timers/external event counters with combined three capture and seven compare channels.

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Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz clock input. Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses (400 kbit/s), SPI and SSP with buffering and variable data length capabilities. Vectored addresses. interrupt controller with congurable priorities and vector

Up to thirty-two 5 V tolerant fast general purpose I/O pins. Up to 13 edge or level sensitive external interrupt pins available. 70 MHz maximum CPU clock available from programmable on-chip PLL with a possible

On-chip integrated oscillator operates with an external crystal in the range from 1 MHz to 25 MHz. Power saving modes include Idle mode, Power-down mode with RTC active, and Powerdown mode. Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization. Processor wake-up from Power-down mode via external interrupt or RTC.

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2.Ordering information
Table 1: Type number LPC2101FBD48 LPC2102FBD48 LPC2103FBD48 LPC2103FA44
Ordering information

Package Name LQFP48 LQFP48 LQFP48 PLCC44 Description Version plastic low prole quad at package; 48 leads; SOT313-2 body 7 7 1.4 mm plastic low prole quad at package; 48 leads; SOT313-2 body 7 7 1.4 mm plastic low prole quad at package; 48 leads; SOT313-2 body 7 7 1.4 mm plastic leaded chip carrier; 44 leads SOT187-2

3.1 Ordering options


Table 2: Type number LPC2101FBD48 LPC2102FBD48 LPC2103FBD48 LPC2103FA44
Ordering options

Flash memory 8 kB 16 kB 32 kB 32 kB

RAM 2 kB 4 kB 8 kB 8 kB

ADC 8 inputs 8 inputs 8 inputs 8 inputs

Temperature range (C) 40 to +85 40 to +85 40 to +85 40 to +85

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4. Block diagram
XTAL2 V
TMS TRST TCK TDI TDO XTAL1 RST
DD(3V3)

V V
DD(1V8) SS

LPC2101/2102/2103
HIGH SPEED

TEST/DEBUG INTERFACE
SYSTEM

P0[31:0]

GENERAL PURPOSE I/O

8 kB BOOT ROM

ARM7TDMI-S
AHB BRIDGE system clock

PLL

FUNCTIONS

ARM7 local bus

VECTORED INTERRUPT CONTROLLER

AMBA AHB (Advanced High-performance Bus) INTERNAL SRAM CONTROLLER MEMORY ACCELERATOR

2 kB/4 kB/ 8 kB SRAM

8 kB/16 kB/ 32 kB FLASH

AHB TO APB BRIDGE APB (ARM peripheral bus)

EINT2 to EINT0

(1) (1)
(1)
(1)
(1)

EXTERNAL INTERRUPTS

I C-BUS SERIAL INTERFACES 0 AND 1

SCL0, SCL1

(1) (1) (1)

SDA0, SDA1

3 CAP0

4 CAP1

3 CAP2

3 MAT0

4 MAT1

(1)
(1)
(1)

3 MAT2

CAPTURE/COMPARE EXTERNAL COUNTER TIMER 0/TIMER 1/ TIMER 2/TIMER 3

SCK0, SCK1

SPI AND SSP SERIAL INTERFACES


MISO1

MOSI0, MOSI1

(1)

(1)

MISO0,

4 MAT3

SSEL0, SSEL1 TXD0, TXD1 ADC UART0/UART1

(1)

(1) (1)

AD0[7:0]

RXD0, RXD1
RTS1, DCD1, RI1

DSR1, CTS1, DTR1

P0[31:0]

GENERAL PURPOSE I/O

REAL-TIME CLOCK

RTXC1 RTXC2 VBAT

WATCHDOG TIMER

SYSTEM CONTROL

002aab814

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5.2 Pin description


Table 3:Pin description Symbol P0.0 to P0.31 LQFP48 PLCC44 Type I/O Description Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. A total of 31 pins of the Port 0 can be used as general purpose bidirectional digital I/Os while P0.31 is an output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block. P0.0 General purpose Input/output digital pin (GPIO). TXD0 Transmitter output for UART0. MAT3.1 PWM output 1 for Timer 3. P0.1 General purpose Input/output digital pin (GPIO). RXD0 Receiver input for UART0. MAT3.2 PWM output 2 for Timer 3. P0.2 General purpose Input/output digital pin (GPIO).
2 SCL0 I C0 clock Input/output. Open-drain output (for

P0.0/TXD0/ MAT3.1

13 [1]

18 [1]

I/O O O

P0.1/RXD0/ MAT3.2

14 [2]

19 [2]

I/O I O

P0.2/SCL0/ CAP0.0

18

[3]

22

[3]

I/O I/O I

2 I C-bus compliance). CAP0.0 Capture input for Timer 0, channel 0.

P0.3/SDA0/ MAT0.0

21

[3]

25

[3]

I/O I/O

P0.3 General purpose Input/output digital pin (GPIO).


2 SDA0 I C0 data input/output. Open-drain output (for

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O P0.4/SCK0/ CAP0.1 22
[4]

2 I C-bus compliance). MAT0.0 PWM output for Timer 0, channel 0. P0.4 General purpose Input/output digital pin (GPIO). SCK0 Serial clock for SPI0. SPI clock output from master or input to slave. CAP0.1 Capture input for Timer 0, channel 1. P0.5 General purpose Input/output digital pin (GPIO). MISO0 Master In Slave OUT for SPI0. Data input to SPI master or data output from SPI slave. MAT0.1 PWM output for Timer 0, channel 1. P0.6 General purpose Input/output digital pin (GPIO). MOSI0 Master Out Slave In for SPI0. Data output from SPI master or data input to SPI slave. CAP0.2 Capture input for Timer 0, channel 2. P0.7 General purpose Input/output digital pin (GPIO). SSEL0 Slave Select for SPI0. Selects the SPI interface as a slave. MAT2.0 PWM output for Timer 2, channel 0. P0.8 General purpose Input/output digital pin (GPIO). TXD1 Transmitter output for UART1. MAT2.1 PWM output for Timer 2, channel 1. P0.9 General purpose Input/output digital pin (GPIO). RXD1 Receiver input for UART1. MAT2.2 PWM output for Timer 2, channel 2.

26

[4]

I/O I/O I

P0.5/MISO0/ MAT0.1

23

[4]

27

[4]

I/O I/O O

P0.6/MOSI0/ CAP0.2

24

[4]

28

[4]

I/O I/O I

P0.7/SSEL0/ MAT2.0

28

[2]

31

[2]

I/O I O

P0.8/TXD1/ MAT2.1

29

[4]

32

[4]

I/O O O

P0.9/RXD1/ MAT2.2

30 [2]

33 [2]

I/O I O

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Symbol P0.10/RTS1/ CAP1.0/AD0.3

PLCC44
[4]

Type 38 [4] I/O O I I

Description P0.10 General purpose Input/output digital pin (GPIO). RTS1 Request to Send output for UART1. CAP1.0 Capture input for Timer 1, channel 0. AD0.3 ADC 0, input 3. P0.11 General purpose Input/output digital pin (GPIO). CTS1 Clear to Send input for UART1. CAP1.1 Capture input for Timer 1, channel 1. AD0.4 ADC 0, input 4. P0.12 General purpose Input/output digital pin (GPIO). DSR1 Data Set Ready input for UART1. MAT1.0 PWM output for Timer 1, channel 0. AD0.5 ADC 0, input 5. P0.13 General purpose Input/output digital pin (GPIO). DTR1 Data Terminal Ready output for UART1. MAT1.1 PWM output for Timer 1, channel 1. P0.14 General purpose Input/output digital pin (GPIO). DCD1 Data Carrier Detect input for UART1. SCK1 Serial Clock for SPI1. SPI clock output from master or input to slave. EINT1 External interrupt 1 input. P0.15 General purpose Input/output digital pin (GPIO). RI1 Ring Indicator input for UART1. EINT2 External interrupt 2 input. P0.16 General purpose Input/output digital pin (GPIO). EINT0 External interrupt 0 input. MAT0.2 PWM output for Timer 0, channel 2. P0.17 General purpose Input/output digital pin (GPIO). CAP1.2 Capture input for Timer 1, channel 2. 2 I C-bus compliance). P0.18 General purpose Input/output digital pin (GPIO). CAP1.3 Capture input for Timer 1, channel 3.
2 SDA1 I C1 data Input/output. Open-drain output (for 2 SCL1 I C1 clock Input/output. Open-drain output (for

P0.11/CTS1/ CAP1.1/AD0.4

[3]

39 [3]

I/O I I I

P0.12/DSR1/ MAT1.0/AD0.5

[4]

40 [4]

I/O I O I

P0.13/DTR1/ MAT1.1

[4]

43 [4]

I/O O O

P0.14/DCD1/ SCK1/EINT1

[3]

[3]

I/O I I/O I

P0.15/RI1/ EINT2

[4]

3 [4]

I/O I I

P0.16/EINT0/ MAT0.2

[2]

[2]

I/O I O

P0.17/CAP1.2/ SCL1

[1]

[1]

I/O I I/O

P0.18/CAP1.3/ SDA1

[1]

6 [1]

I/O I I/O

P0.19/MAT1.2/ MISO1

[1]

7 [1]

I/O O I/O

2 I C-bus compliance). P0.19 General purpose Input/output digital pin (GPIO). MAT1.2 PWM output for Timer 1, channel 2. MISO1 Master In Slave Out for SSP. Data input to SPI master or data output from SSP slave. P0.20 General purpose Input/output digital pin (GPIO). MAT1.3 PWM output for Timer 1, channel 3. MOSI1 Master Out Slave for SSP. Data output from SSP master or data input to SSP slave.

P0.20/MAT1.3/ MOSI1

[2]

8 [2]

I/O O I/O

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Table 3:Pin description continued Symbol P0.21/SSEL1/ MAT3.0 LQFP48 3 [4] PLCC44 9 [4] Type I/O I O P0.22/AD0.0 P0.23/AD0.1 P0.24/AD0.2 P0.25/AD0.6 P0.26/AD0.7 P0.27/TRST/ CAP2.0 32 33 34 38
[4]

Description P0.21 General purpose Input/output digital pin (GPIO). SSEL1 Slave Select for SPI1. Selects the SPI interface as a slave. MAT3.0 PWM output for Timer 3, channel 0. P0.22 General purpose Input/output digital pin (GPIO). AD0.0 ADC 0, input 0. P0.23 General purpose Input/output digital pin (GPIO). AD0.1 ADC 0, input 1. P0.24 General purpose Input/output digital pin (GPIO). AD0.2 ADC 0, input 2. P0.25 General purpose Input/output digital pin (GPIO). AD0.6 ADC 0, input 6. P0.26 General purpose Input/output digital pin (GPIO). AD0.7 ADC 0, input 7. P0.27 General purpose Input/output digital pin (GPIO). TRST Test Reset for JTAG interface. CAP2.0 Capture input for Timer 2, channel 0. P0.28 General purpose Input/output digital pin (GPIO). TMS Test Mode Select for JTAG interface. CAP2.1 Capture input for Timer 2, channel 1. P0.29 General purpose Input/output digital pin (GPIO). TCK Test Clock for JTAG interface. CAP2.2 Capture input for Timer 2, channel 2. P0.30 General purpose Input/output digital pin (GPIO). TDI Test Data In for JTAG interface. MAT3.3 PWM output 3 for Timer 3. P0.31 General purpose output only digital pin (GPIO). TDO Test Data Out for JTAG interface. Input to the RTC oscillator circuit. Output from the RTC oscillator circuit. Returned test clock output: Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up. Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplier. Debug select: When LOW, the part operates normally. When HIGH, debug mode is entered. Input with internal pull-down. External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. Ground: 0 V reference.

35 36 37 41

[4]

I/O I I/O I I/O I I/O I I/O I I/O I I

[1]

[1]

[1]

[1]

[1]

[1]

39 [1] 8
[4]

n.c. 13
[4]

P0.28/TMS/ CAP2.1

[4]

14

[4]

I/O I I

P0.29/TCK/ CAP2.2

10 [4]

15 [4]

I/O I I

P0.30/TDI/ MAT3.3

15 [4]

20 [4]

I/O I O

P0.31/TDO RTXC1 RTXC2 RTCK

16

[4]

21

[4]

O O I O I/O

20 [5] 25 26
[5] [5]

24 [5] 29
[5]

n.c.

X1 X2 DBGSEL RST

11 12 27 6

16 17 30 11

I O I I

V
SS

7, 19, 43

1, 12, 23

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Table 3: Symbol

Pin description continued LQFP48 31 PLCC44 34 Type I Description Analog ground: 0 V reference. This should be nominally the
same voltage as VSS but should be isolated to minimize noise

SSA

and error. V
DDA

42

44

Analog 3.3 V power supply: This should be nominally the


same voltage as VDD(3V3) but should be isolated to minimize

noise and error. This voltage is used to power the on-chip PLL. This pin also provides a voltage reference level for the ADC. V
DD(1V8)

5 17, 40 4

10 42 n.c.

I I I

1.8 V core power supply: This is the power supply voltage for internal circuitry. 3.3 V pad power supply: This is the power supply voltage for the I/O ports. RTC power supply: 3.3 V on this pin supplies the power to the RTC.

V
DD(3V3)

VBAT

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. [2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If congured for an input function, this pad utilizes built-in glitch lter that blocks pulses shorter than 3 ns. [3] Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specication compatible pad. It requires external pull-up to provide an output functionality. [4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If congured for an input function, this pad utilizes built-in glitch lter that blocks pulses shorter than 3 ns. When congured as an ADC input, digital section of the pad is disabled. [5] Pad provides special analog functionality.

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6.FUNCTIONAL DESCRIPTION: Control overview:The ARM7TDMI-S is a general purpose 32-bit microprocessor,


which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: The standard 32-bit ARM set. A 16-bit Thumb set. The Thumb sets 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARMs performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The particular ash implementation in the LPC2101/2102/2103 allows for full speed execution also in ARM mode. It is recommended to program performance critical and short code sections in ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30 % over Thumb mode. 6.2 On-chip ash program memory The LPC2101/2102/2103 incorporate a 8 kB, 16 kB or 32 kB ash memory system respectively. This memory may be used for both code and data storage. Programming of the ash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the ash while the application is running, allowing a great degree of exibility for data storage eld rmware upgrades, etc. The entire ash memory is available for user code as the bootloader.

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6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/2102/2103 provide 2 kB, 4 kB or 8 kB of static RAM. 6.4 Memory map The LPC2101/2102/2103 memory map incorporates several distinct regions, as shown in Figure 4. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either ash memory (the default) or on-chip static RAM. This is described in Section 6.17 System control.
4.0 GB AHB PERIPHERALS 3.75 GB APB PERIPHERALS 3.5 GB 0xE000 0000 0xF000 0000 0xFFFF FFFF

3.0 GB RESERVED ADDRESS SPACE

0xC000 0000

2.0 GB BOOT BLOCK RESERVED ADDRESS SPACE 8 kB ON-CHIP STATIC RAM (LPC2103) 4 kB ON-CHIP STATIC RAM (LPC2102) 2 kB ON-CHIP STATIC RAM (LPC2101) 1.0 GB RESERVED ADDRESS SPACE 32 kB ON-CHIP NON-VOLATILE MEMORY (LPC2103) 16 kB ON-CHIP NON-VOLATILE MEMORY (LPC2102) 8 kB ON-CHIP NON-VOLATILE MEMORY (LPC2101) 0.0 GB

0x8000 0000 0x7FFF FFFF

0x7FFF E000 0x7FFF DFFF 0x4000 2000 0x4000 1FFF 0x4000 1000 0x4000 0FFF 0x4000 0800 0x4000 07FF 0x4000 0000 0x0000 8000 0x0000 7FFF 0x0000 4000 0x0000 3FFF 0x0000 2000 0x0000 1FFF 0x0000 0000
002aab822

Fig 4. LPC2101/2102/2103 memory map

6.5 Interrupt controller The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored
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IRQ, and non-vectored IRQ as dened by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classied as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.
Interrupt sources

Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt ags. Individual interrupt ags may also represent more than one interrupt source. Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Conguration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undened. The Pin Control Module with its pin select registers denes the functionality of the microcontroller in a given hardware environment. After reset all pins of Port 0 are congured as input with the following exceptions: If debug is enabled, the JTAG pins will assume their JTAG functionality. The pins associated with the I2C0 interface are open-drain. 6.7 Fast general purpose parallel I/O
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Device pins that are not connected to a specic peripheral function are controlled by the GPIO registers. Pins may be dynamically congured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins. LPC2101/2102/2103 introduce accelerated GPIO functions over prior LPC2000 devices: GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing. Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. All GPIO registers are byte addressable. Entire port value can be written in one instruction.
Features

Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. Direction control of individual bits. Separate control of output set and clear. All I/O default to inputs after reset. 10-bit A/D converter The LPC2101/2102/2103 contain one analog to digital converter. It is a single 10bit successive approximation analog to digital converter with eight channels.
Features

Measurement range of 0 V to 3.3 V. Each converter capable of performing more than 400,000 10-bit samples per second. Burst conversion mode for single or multiple inputs. Optional conversion on transition on input pin or Timer Match signal. Every analog input has a dedicated result register to reduce interrupt overhead. UARTs The LPC2101/2102/2103 each contain two UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2101/2102/2103 include a fractional baud rate generator for both UARTs. Standard baud rates such as 115200 can be achieved with any crystal frequency above 2 MHz.

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Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. Transmission FIFO control enables implementation of software (XON/XOFF) ow control on both UARTs. UART1 is equipped with standard modem interface signals. This module also provides full support for hardware ow control (auto-CTS/RTS).
2 I C-bus serial I/O controllers

The LPC2101/2102/2103 each contain two I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line (SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., LCD driver) or a transmitter with the capability to both receive and send information such as serial memory. Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2101/2102/2103 supports bit rates up to 400 kbit/s (Fast I2C).
Features

o o o o o

Compliant with standard I2C-bus interface. Easy to congure as Master, Slave, or Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master).

o Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. o Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. o Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. o The I2C-bus can also be used for test and diagnostic purposes. SPI serial I/O controller The LPC2101/2102/2103 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master.

SSP serial I/O controller


[Type text]

The LPC2101/2102/2103 each contain one SSP. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. However, only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to 16 bits owing from the master to the slave and from the slave to the master. Often only one of these data streams carries meaningful data.
Features

o Compatible with Motorola SPI, 4-wire TIs SSI and National Semiconductors Microwire buses. o Synchronous Serial Communication. o Master or slave operation. o 8-frame FIFOs for both transmit and receive. o Four bits to 16 bits per frame. General purpose 32-bit timers/external event counters The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specied timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with or and and, as well as broadcast functions among them. The LPC2101/2102/2103 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this conguration, unused capture lines can be selected as regular timer capture inputs or used as external interrupts.
Features

o A 32-bit timer/counter with a programmable 32-bit prescaler. o External event counter or timer operation. o Four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. o Four 32-bit match registers that allow: Continuous operation with optional interrupt generation on match. Stop timer on match with optional interrupt generation. Reset timer on match with optional interrupt generation.

o Four external outputs per timer/counter corresponding to match registers, with the following capabilities: Set LOW on match.

[Type text]

General purpose 16-bit timers/external event counters The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specied timer values, based on four match registers. It also includes three capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with or and and, as well as broadcast functions among them. The LPC2101/2102/2103 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this conguration, unused capture lines can be selected as regular timer capture inputs or used as external interrupts.

Features

o Two 16-bit timer/counters with a programmable 16-bit prescaler. o External event counter or timer operation. o Three 16-bit capture channels that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. o Four 16-bit match registers that allow: Continuous operation with optional interrupt generation on match. Stop timer on match with optional interrupt generation. Reset timer on match with optional interrupt generation.

o Four external outputs per timer/counter corresponding to match registers, with the following capabilities: Set LOW on match. Set HIGH on match. Toggle on match. Do nothing on match.

Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. o o o o Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal pre-scaler. 32 Selectable time period from (TPCLK PCLK TPCLK

Real-time clock
[Type text]

The Real-Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode).
Features

o Measures the passage of time to maintain a calendar and clock. o Ultra-low power design to support battery powered systems. o Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. o Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the external crystal/oscillator input at XTAL1. Programmable Reference Clock Divider allows ne adjustment of the RTC. o Dedicated power supply pin can be connected to a battery or the main 3.3 V.
Crystal oscillator

On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running and connected. Refer to Section 6.17.2 PLL for additional information.
PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 70 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must congure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The

Reset and wake-up timer

Reset has two sources on the LPC2101/2102/2103: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch lter. Assertion of chip reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator
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is running, a xed number of clocks have passed, and the on-chip ash controller has completed its initialization. When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined reset values. The wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer. The wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufcient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
Code security

This feature of the LPC2101/2102/2103 allow an application to control whether it can be debugged or protected from observation. If after reset on-chip bootloader detects a valid checksum in ash and reads 0x8765 4321 from address 0x1FC in ash, debugging will be disabled and thus the code in ash will be protected from observation. Once debugging is disabled, it can only be enabled by performing a full chip erase using the ISP.
External interrupt inputs

The LPC2101/2102/2103 include up to three edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as three independent interrupt signals. The External Interrupt Inputs can optionally be used to wake-up the processor from Power-down mode. Additionally all 10 capture input pins can also be used as external interrupts without the option to wake the device up from Power-down mode.

Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip ash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts.
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Power control

The LPC2101/2102/2103 supports two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specic interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip RTC will enable the microcontroller to have the RTC active during Power-down mode. Power-down current is increased with RTC active. However, it is signicantly lower than in Idle mode. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings during active and Idle mode.
APB bus

The APB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB divider serves two purposes. The rst is to provide peripherals with the desired PCLK via APB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB bus may be slowed down to 1 2 to 1 4 of the processor clock rate. Because the APB bus must work properly at power-up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB bus), the default condition at reset is for the APB bus to run at 1 4 of the processor clock rate. The second purpose of the APB divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode. Emulation and debugging The LPC2101/2102/2103 support emulation and debugging via a JTAG serial port.
EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core.
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7. Limiting values
Table 4:limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol [1] Min
[2] [3]

V DD(1V8) V DD(3V3) V DDA V i(VBAT) V


IA

Parameter supply voltage (1.8 V) supply voltage (3.3 V) analog 3.3 V pad supply voltage input voltage on pin VBAT analog input voltage input voltage

Conditions

Max +2.5 +3.6 4.6 4.6 5.1 6.0 VDD + 0.5 100 100 125 1.5
[9] [9] [7]

Unit V V V V V V V mA mA C W

0.5 0.5 0.5 0.5

for the RTC


[4]

VI

5 V tolerant I/O pins other I/O pins

[5] [6]

0.5 0.5 0.5 40 -

[5] [8] [10] [11]

I DD I SS T
P
stg
tot(pack)

supply current ground current storage temperature total power dissipation (per package) based on package heat transfer, not device power consumption

[1]

The following applies to the Limiting values:


a) This product includes circuitry specically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specied. All voltages are with respect to V SS unless otherwise noted. [2] [3] [4] [5] [6] [7] [8] [9] Core and internal rail. External rail. On ADC related pins. Including voltage on outputs in 3-state mode. Only valid when the VDD(3V3) supply voltage is present. Not to exceed 4.6 V. Per supply pin. The peak current is limited to 25 times the corresponding maximum current.

[10] Per ground pin. [11] Dependent on package type.

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8. STATIC CHARACTERISTICS:
Table 5: static characteristics
Ta = 40 C to +85 C for commercial applications, unless otherwise specied. Symbol Parameter Conditions
[2] [3]

V DD(1V8) supply voltage (1.8 V) V


V
DD(3V3)
DDA

Min 1.65 3.0 3.0 2.0


[4]

Typ [1] 1.8 3.3 3.3 3.3

Max 1.95 3.6 3.6 3.6

Unit V V V V

supply voltage (3.3 V) analog 3.3 V pad supply voltage

input voltage on pin VBAT Standard port pins, RESET, RTCK


i(VBAT)

I IL I
I I

LOW-state input current HIGH-state input current OFF-state output current I/O latch-up current

IH
OZ

VI = 0 V; no pull-up VI = VDD(3V3); no pull-down VO = 0 V, VO = VDD(3V3); no pull-up/down (0.5VDD(3V3)) < V <

3 3 3 100

A A A mA

latch

(1.5V

DD(3V3)

VI VO

input voltage output voltage HIGH-state input voltage LOW-state input voltage

Tj < 125 C pin congured to provide a digital function output active

[5] [6] [7]

0 0 2.0 V

DD(3V3)

5.5

V V V V V V V mA mA mA mA A A A

V
DD(3V3)

V IH V IL V
V
hys
OH

0.8 0.4 45 50 150 85 0

hysteresis voltage HIGH-state output voltage IOH = 4 mA LOW-state output voltage HIGH-state output current LOW-state output current HIGH-state short-circuit output current LOW-state short-circuit output current pull-down current pull-up current active mode supply current IOL = 4 mA

[8]

0.4 50 50 0

V OL I OH I
I I
OLS

0.4
[8]

=V

OH

DD(3V3)

0.4 V

4 4 10

[8] [8] [9]

OL
OHS

VOL = 0.4 V VOH = 0 V V


OL

=V
DDA

[9]

I pd I
pu

VI = 5 V [10] VI = 0 V
[11]
I

<V<5V

15 0

I
DD(act)

DD(3V3)

[10]

VDD(1V8) = 1.8 V, Ta = 25 C, code

while(1){}
executed from ash, no active peripherals CCLK = 10 MHz CCLK = 70 MHz (other parameters as above) I
DD(pd)

<tbd> <tbd> <tbd> <tbd>

7 41 7 <tbd>

<tbd> <tbd> <tbd> <tbd>

mA mA A A

Power-down mode supply VDD(1V8) = 1.8 V, Ta = +25 C current VDD(1V8) = 1.8 V, Ta = +85 C

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offset error EO 1023

gain error EG

1022

1021

1020

1019

1018

(2)

7 code out 6
(1)

5
(5)

4
(4)

3
(3)

1 LSB (ideal)

0 1 offset error E
O

6
IA

1018

1019

1020 V V

1021

1022

1023 1024

V (LSB
ideal

)
DDA SSA
1 LSB =

1024
002aac046

(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve.

Fig 5. A/D conversion characteristics

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9. Dynamic characteristics
Table 7: Dynamic characteristics Ta = 0 C to +70 C for commercial applications, 40 C to +85 C for industrial applications, VDD(1V8), VDD(3V3) over [1] specied ranges Symbol Parameter External clock Conditions Min Typ [2] Max Unit

f osc T cy(clk) t CHCX t CLCX t CLCH t t r(o) t


f(o)

oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time

10 40

10 10

25 100 5 5 -

MHz ns ns ns ns ns ns ns ns

T 0.4 cy(clk) T 0.4


cy(clk)

CHCL clock fall time Port pins (except P0.2 and P0.3)

output rise time output fall time output fall time

I C-bus pins (P0.2 and P0.3)

V to V
IH IL

f(o)

20 + 0.1 Cb [3] -

[1] [2] [3]

Parameters are valid over operating temperature range unless otherwise specied. Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), nominal supply voltages. Bus capacitance Cb in pF, from 10 pF to 400 pF.

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2.2 POWER SUPPLY:

2.2.1 Introduction:
All digital circuits require regulated power supply. In this article we are going to learn how to get a regulated positive supply from the mains supply.

The basic block diagram of a fixed regulated power supply

2.2.2 Power supply circuit:

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2.2.3 TRANSFORMER:

A transformer consists of two coils also called as WINDINGS namely PRIMARY & SECONDARY. They are linked together through inductively coupled electrical conductors also called as CORE. A changing current in the primary causes a change in the Magnetic Field in the core & this in
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turn induces an alternating voltage in the secondary coil. If load is applied to the secondary then an alternating current will flow through the load. If we consider an ideal condition then all the energy from the primary circuit will be transferred to the secondary circuit through the magnetic field.

So

The secondary voltage of the transformer depends on the number of turns in the Primary as well as in the secondary.

2.2.4 Rectifier:

A rectifier is a device that converts an AC signal into DC signal. For rectification purpose we use a diode, a diode is a device that allows current to pass only in one direction i.e. when the anode of the diode is positive with respect to the cathode also called as forward biased condition & blocks current in the reversed biased condition.

Rectifier can be classified as follows:

1)

Half Wave rectifier.

[Type text]

This is the simplest type of rectifier as you can see in the diagram a half wave rectifier consists of only one diode. When an AC signal is applied to it during the positive half cycle the diode is forward biased & current flows through it. But during the negative half cycle diode is reverse biased & no current flows through it. Since only one half of the input reaches the output, it is very inefficient to be used in power supplies.

2)

Full wave rectifier.

[Type text]

Half wave rectifier is quite simple but it is very inefficient, for greater efficiency we would like to use both the half cycles of the AC signal. This can be achieved by using a center tapped transformer i.e. we would have to double the size of secondary winding & provide connection to the center. So during the positive half cycle diode D1 conducts & D2 is in reverse biased condition. During the negative half cycle diode D2 conducts & D1 is reverse biased. Thus we get both the half cycles across the load.

One of the disadvantages of Full Wave Rectifier design is the necessity of using a center tapped transformer, thus increasing the size & cost of the circuit. This can be avoided by using the Full Wave Bridge Rectifier.

3)

Bridge Rectifier

[Type text]

As the name suggests it converts the full wave i.e. both the positive & the negative half cycle into DC thus it is much more efficient than Half Wave Rectifier & that too without using a center tapped transformer thus much more cost effective than Full Wave Rectifier.

Full Bridge Wave Rectifier consists of four diodes namely D1, D2, D3 and D4. During the positive half cycle diodes D1 & D4 conduct whereas in the negative half cycle diodes D2 & D3 conduct thus the diodes keep switching the transformer connections so we get positive half cycles in the output.

If we use a center tapped transformer for a bridge rectifier we can get both positive & negative half cycles which can thus be used for generating fixed positive & fixed negative voltages.

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2.2.5 FILTER CAPACITOR:

Even though half wave & full wave rectifier give DC output, none of them provides a constant output voltage. For this we require to smoothen the waveform received from the rectifier. This can be done by using a capacitor at the output of the rectifier this capacitor is also called as FILTER CAPACITOR or SMOOTHING CAPACITOR or RESERVOIR CAPACITOR. Even after using this capacitor a small amount of ripple will remain. We place the Filter Capacitor at the output of the rectifier the capacitor will charge to the peak voltage during each half cycle then will discharge its stored energy slowly through the load while the rectified voltage drops to zero, thus trying to keep the voltage as constant as possible.

[Type text]

If we go on increasing the value of the filter capacitor then the Ripple will decrease. But then the costing will increase. The value of the Filter capacitor depends on the current consumed by the circuit, the frequency of the waveform & the accepted ripple.

Where, Vr= accepted ripple voltage.( should not be more than 10% of the voltage) I= current consumed by the circuit in Amperes. F= frequency of the waveform. A half wave rectifier has only one peak in one cycle so F=25hz Whereas a full wave rectifier has Two peaks in one cycle so F=100hz.

2.2.6 VOLTAGE REGULATOR:

A Voltage regulator is a device which converts varying input voltage into a constant regulated output voltage. Voltage regulator can be of two types 1) Linear Voltage Regulator Also called as Resistive Voltage regulator because they dissipate the excessive voltage resistively as heat. 2) Switching Regulators. They regulate the output voltage by switching the Current ON/OFF very rapidly. Since their output is either ON or OFF it dissipates very low power thus achieving higher efficiency as compared to linear voltage regulators. But they are more complex & generate high noise due to their switching action. For low level of output power switching regulators tend to be costly but for higher output wattage they are much cheaper than linear regulators.
[Type text]

The most commonly available Linear Positive Voltage Regulators are the 78XX series where the XX indicates the output voltage. And 79XX series is for Negative Voltage Regulators.

After filtering the rectifier output the signal is given to a voltage regulator. The maximum input voltage that can be applied at the input is 35V.Normally there is a 2-3 Volts drop across the regulator so the input voltage should be at least 2-3 Volts higher than the output voltage. If the input voltage gets below the Vmin of the regulator due to the ripple voltage or due to any other reason the voltage regulator will not be able to produce the correct regulated voltage.

IC 7805:

7805 is an integrated three-terminal positive fixed linear voltage regulator. It supports an input voltage of 10 volts to 35 volts and output voltage of 5 volts. It has a current rating of 1 amp although lower current models are available. Its output voltage is fixed at 5.0V. The 7805 also has a built-in current limiter as a safety feature. 7805 is manufactured by many companies, including National Semiconductors and Fairchild Semiconductors. The 7805 will automatically reduce output current if it gets too hot.The last two digits represent the voltage; for instance, the 7812 is a 12-volt regulator. The 78xx series of regulators is designed to work in complement with the 79xx series of negative voltage regulators in systems that provide both positive and negative regulated voltages, since the 78xx series can't regulate negative voltages in such a system.

[Type text]

The 7805 & 78 is one of the most common and well-known of the 78xx series regulators, as it's small component count and medium-power regulated 5V make it useful for powering TTL devices.

Specifications of IC7805:

SPECIFICATIONS

IC 7805

Vout

5V

Vein - Vout Difference

5V - 20V

Operation Ambient Temp

0 - 125C

Output Imax

1A

DTMF RECIEVER

(HT9170B):

The HT9170B/D are Dual Tone Multi Frequency (DTMF) receivers integrated with digital decoder and band split filter functions as well as power-down mode and inhibit mode operations. Such devices use digital counting techniques to detect and decode all the 16 DTMF tone pairs into a 4-bit code output. Highly accurate switched capacitor filters are implemented to divide tone signals into low and high group signals. A built-in dial tone rejection circuit is provided to eliminate the need for pre-filtering. The DTMF (Dual Tone Multiple Frequency) application is associated with digital telephony, and provides two selected output frequencies (one high band, one low band) for a duration of 100 ms. A benchmark subroutine has been written for the COP820C/840C microcontrollers, and is outlined in detail in this application note. This DTMF subroutine takes 110 bytes of COP820C/840C code, consisting of 78 bytes
[Type text]

of program code and 32 bytes of ROM table. The timings in this DTMF subroutine are based on a 20 MHz COP820C/840C clock, giving an instruction cycle time of 1 ms.The matrix for selecting the high and low band frequencies associated with each key is shown in Figure 1 . Each key is uniquely referenced by selecting one of the four low band frequencies associated with the matrix rows, coupled with selecting one of the four high band frequencies associated with the matrix columns. The low band frequencies are 697, 770, 852, and 941 Hz, while the high band frequencies are 1209, 1336, 1477, and 1633 Hz. The DTMF subroutine assumes that the key decoding is supplied as a low order hex digit in the accumulator. The COP820C/840C DTMF subroutine will then generate the selected high band and low band frequencies on port G output pins G3 and G2 respectively for a duration of 100 ms. The COP820C/840C each contain only one timer. The problem is that three different times must be generated to satisfy the DTMF application. These three times are the periods of the two selected frequencies and the 100 ms duration period. Obviously the single timer can be used to generate any one (or possibly two) of the required times, with the program having to generate the other two (or one) times. The solution to the DTMF problem lies in dividing the 100 ms time duration by the half periods (rounded to the nearest micro second) for each of the eight frequencies, and then examining the respective high band and low band quotients and remainders. The results of these divisions are detailed in Table I. The low band frequency quotients range from 139 to 188, while the high band quotients range from 241 to 326. The observation that only the low band quotients will each fit in a single byte dictates that the high band frequency be produced by the 16 bit (2 byte) COP820C/840C timer running in PWM (Pulse Width Modulation) Mode. TL/

2.3.1 FEAUTURES:

Operating voltage: 2.5V~5.5V Minimal external components


[Type text]

No external filter is required Low standby current (on power down mode) Excellent performance Tristate data output for MCU interface 3.58MHz crystal or ceramic resonator 1633Hz can be inhibited by the INH pin HT9170B: 18-pin DIP package

[Type text]

PIN ASSIGMENT:

PIN DESCRIPTION:

[Type text]

2.3.2 BLOCK DIAGRAM:

2.3.3 FUNCTIONAL DESCRIPTION:

The HT9170B/D tone decoders consist of three band pass filters and two digital decode circuits to convert a tone (DTMF) signal into digital code output. An operational amplifier is built-in to adjust the input signal. The pre-filter is a band rejection filter, which reduces the dialing tone from 350Hz to 400Hz.
[Type text]

The low group filter filters low group frequency signal output whereas the high group filter filters high group Frequency signal output. A zero-crossing detector with follows each filters output hysteretic. When each signal amplitude at the output exceeds the specified level, it is transferred to full swing logic signal. When input signals are recognized to be effective, DV becomes high, and the correct tone code (DTMF) digit is transferred.

Steering control circuit:

The steering control circuit is used for measuring the effective signal duration and for protecting against drop out of valid signals. It employs the analog delay by external RC time-constant controlled by EST. The EST pin is normally low and draws the RT/GT pin to keep low through discharge of external RC. When a valid tone input is detected, EST goes high to charge RT/GT through RC.

When the voltage of RT/GT changes from 0 to VTRT (2.35V for 5V supply), the input signal is effective, and the code detector will create the correct code. After D0~D3 are completely latched, DV output becomes high. When the voltage of RT/GT falls down from VDD to VTRT (i.e. when there is no input tone), DV output becomes Low, and D0~D3 keeps data until a next valid tone input is produced. By
[Type text]

selecting adequate external RC value, the minimum acceptable input tone duration (tACC) and the minimum acceptable inter-tone rejection (tIR) can be set. External Components (R, C) are chosen by the formula.

2.3.4 TIMING DIAGRAM:

[Type text]

2.3.5 Applications:

PABX Central office Mobile radio Remote control Remote data entry Call limiting

[Type text]

2.1.4 WIRELESS CAMARA:

Description:
Features:
1) Classical design for family 2) 380 TV Line 1.2GHz; 3) Tiny size for portability and observation; 4) Built-in microphone for audio monitoring; 5) Min 100 meters transmission distance without block. 6) Including adjustable bracket, easy installation.

Specification: 1) Imaging sensor: 1/3" CMOS 2) CMOS total pixels: Pal 628 x 582; NTSC 510 x 492 3) Horizontal resolution: 380 TV lines 4) View angle:62 5) Minimum illumination: 1.0 Lux / F2.0 6) Transmission power: 50mW 7) Modulation mode: FM 8) Unobstructed effective range: 100m 9) Frequency: 900~1230MHz 10)Scanning Frequency: PAL/CCIR: 50Hz NTSC/EIA: 60Hz 11)Camera Size:36x28x36mm; 12)Camera weight:60g

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Specification: 1) Frequency: 900~1230MHz 2) Scanning Frequency: PAL/CCIR: 50Hz NTSC/EIA: 60Hz 3) Receiving Sensitivity: -85dBm 4) Video Output:1Vp-p@75; S/N>38dB Audio; Output: 1Vpp@600 5) Modulation mode: FM 6) Receiver Size: 7) weight: 130g 1X Receiver 1X Camera 2X Adaptor 1X AV cable 1X Battu 1X Manual

Accessories:

Related Categories

IP Camera Baby Monitor Wireless Camera &... Two Way Radio CCTV Camera CCD Camera spy camera

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2.4.2 MAX 232

RS-232 WAVEFORM

TTL/CMOS Serial Logic Waveform

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The diagram above shows the expected waveform from the UART when using the common 8N1 format. 8N1 signifies 8 Data bits, No Parity and 1 Stop Bit. The RS-232 line, when idle is in the Mark State (Logic 1). A transmission starts with a start bit which is (Logic 0). Then each bit is sent down the line, one at a time. The LSB (Least Significant Bit) is sent first. A Stop Bit (Logic 1) is then appended to the signal to make up the transmission. The data sent using this method, is said to be framed. That is the data is framed between a Start and Stop Bit.

RS-232 Voltage levels +3 to +25 volts to signify a "Space" (Logic 0) -3 to -25 volts for a "Mark" (logic 1). Any voltage in between these regions (i.e. between +3 and -3 Volts) is undefined. The data byte is always transmitted least-significant-bit first. The bits are transmitted at specific time intervals determined by the baud rate of the serial signal. This is the signal present on the RS-232 Port of your computer, shown below.

RS-232 Logic Waveform

2.4.2.1 RS-232 LEVEL CONVERTER


Standard serial interfacing of microcontroller (TTL) with PC or any RS232C Standard device , requires TTL to RS232 Level converter . A MAX232 is used for this purpose. It provides 2-channel RS232C port and requires external 10uF capacitors. The driver requires a single supply of +5V.
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MAX-232 includes a Charge Pump, which generates +10V and -10V from a single 5v supply. Serial communication When a processor communicates with the outside world, it provides data in byte sized chunks. Computers transfer data in two ways: parallel and serial. In parallel data transfers, often more lines are used to transfer data to a device and 8 bit data path is expensive. The serial communication transfer uses only a single data line instead of the 8 bit data line of parallel communication which makes the data transfer not only cheaper but also makes it possible for two computers located in two different cities to communicate over telephone. Serial data communication uses two methods, asynchronous and synchronous. The synchronous method transfers data at a time while the asynchronous transfers a single byte at a time. There are some special IC chips made by many manufacturers for data communications. These chips are commonly referred to as UART (universal asynchronous receiver-transmitter) and USART (universal synchronous asynchronous receiver transmitter). The AT89C51 chip has a built in UART. In asynchronous method, each character is placed between start and stop bits. This is called framing. In data framing of asynchronous communications, the data, such as ASCII characters, are packed in between a start and stop bit. We have a total of 10 bits for a character: 8 bits for the ASCII code and 1 bit each for the start and stop bits. The rate of serial data transfer communication is stated in bps or it can be called as baud rate. To allow the compatibility among data communication equipment made by various manufacturers, and interfacing standard called RS232 was set by the Electronics industries Association in 1960. Today RS232 is the most widely used I/O interfacing standard. This standard is used in PCs and numerous types of equipment. However, since the standard was set long before the advent of the TTL logic family, its input and output voltage levels are not TTL compatible. In RS232, a 1 bit is represented by -3 to -25V, while a 0 bit is represented +3 to +25 V, making -3 to +3 undefined. For this reason, to connect any RS232 to a microcontroller system we must use voltage converters such as MAX232 to connect the TTL logic levels to RS232 voltage levels and vice versa. MAX232 ICs are commonly referred to as line drivers.
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The RS232 cables are generally referred to as DB-9 connector. In labeling, DB-9P refers to the plug connector (male) and DB-9S is for the socket connector (female). The simplest connection between a PC and microcontroller requires a minimum of three pin, TXD, RXD, and ground. Many of the pins of the RS232 connector are used for handshaking signals. They are bypassed since they are not supported by the UART chip.

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IBM PC/ compatible computers based on x86(8086, 80286, 386, 486 and Pentium) microprocessors normally have two COM ports. Both COM ports have RS232 type connectors. Many PCs use one each of the DB-25 and DB-9 RS232 connectors. The COM ports are designated as COM1 and COM2. We can connect the serial port to the COM 2 port of a PC for serial communication experiments. We use a DB9 connector in our arrangement.

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2.4.3 DC GARE MOTORS:

GEAR MOTOR
What Is a Gear Motor? Gear motors are complete motive force systems consisting of an electric motor and a reduction gear train integrated into one easy-to-mount and -configure package. This greatly reduces the complexity and cost of designing and constructing power tools, machines and appliances calling for high torque at relatively low shaft speed or RPM. Gear motors allow the use of economical low-horsepower motors to provide great motive force at low speed such as in lifts, winches, medical tables, jacks and robotics. They can be large enough to lift a building or small enough to drive a tiny clock.

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12V High Torque DC GEAR MOTOR Operation Principle


Most synchronous AC electric motors have output ranges of from 1,200 to 3,600 revolutions per minute. They also have both normal speed and stall-speed torque specifications. The reduction gear trains used in gear motors are designed to reduce the output speed while increasing the torque. The increase in torque is inversely proportional to the reduction in speed. Reduction gearing allows small electric motors to move large driven loads, although more slowly than larger electric motors. Reduction gears consist of a small gear driving a larger gear. There may be several sets of these reduction gear sets in a reduction gear box.

Gear
Toothed wheel that transmits the turning movement of one shaft to another shaft. Gear wheels may be used in pairs or in threes if both shafts are to turn in the same direction. The gear ratio the ratio of the number of teeth on the two wheels determines the torque ratio, the turning force on the output shaft compared with the turning force on the input shaft. The ratio of the angular velocities of the shafts is the inverse of the gear ratio. The common type of gear for parallel shafts is the spur gear, with straight teeth parallel to the shaft axis. The helical gear has teeth cut along sections of a helix or corkscrew shape; the double form of the helix gear is the most efficient for energy transfer. Bevel gears, with tapering teeth set on the base of a cone, are used to connect intersecting shafts.
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The toothed and interlocking wheels which make up a typical gear movement. Gear ratio is calculated by dividing the number of teeth on the driver gear by the number of teeth on the driven gear (gear ratio = driver/driven); the idler gears are ignored. Idler gears change the direction of rotation but do not affect speed. A high driven to driver ratio (middle) is a speedreducing ratio.

Different gears are used to perform different engineering functions depending on the change in direction of motion that is needed. Rack and pinion gears are the commonest gears and are used in car steering mechanics.

Speed Reduction
Sometimes the goal of using a gear motor is to reduce the rotating shaft speed of a motor in the device being driven, such as in a small electric clock where the tiny synchronous motor may be spinning at 1,200 rpm but is reduced to one rpm to drive the second hand, and further reduced in the clock mechanism to drive the minute and hour hands. Here the amount of driving force is irrelevant as long as it is sufficient to overcome the frictional effects of the clock mechanism.
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Torque Multiplication
Another goal achievable with a gear motor is to use a small motor to generate a very large force albeit at a low speed. These applications include the lifting mechanisms on hospital beds, power recliners, and heavy machine lifts where the great force at low speed is the goal.

Motor Varieties
Most industrial gear motors are AC-powered, fixed-speed devices, although there are fixed-gear-ratio, variable-speed motors that provide a greater degree of control. DC gear motors are used primarily in automotive applications such as power winches on trucks, windshield wiper motors and power seat or power window motors.

Many Applications
What power can openers, garage door openers, stair lifts, rotisserie motors, timer cycle knobs on washing machines, power drills, cake mixers and electromechanical clocks have in common is that they all use various integrations of gear motors to derive a large force from a relatively small electric motor at a manageable speed. In industry, gear motor applications in jacks, cranes, lifts, clamping, robotics, conveyance and mixing are too numerous to count.

L293D
L293D is a dual H-bridge motor driver integrated circuit (IC). Motor drivers act as current amplifiers since they take a low-current control signal and provide a higher-current signal. This higher current signal is used to drive the motors. L293D contains two inbuilt H-bridge driver circuits. In its common mode of operation, two DC motors can be driven simultaneously, both in forward and reverse direction. The motor operations of two motors can be controlled by input logic at pins 2 & 7 and 10 & 15. Input logic 00 or 11 will stop the corresponding motor. Logic 01 and 10 will rotate it in clockwise and anticlockwise directions, respectively.

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Enable pins 1 and 9 (corresponding to the two motors) must be high for motors to start operating. When an enable input is high, the associated driver gets enabled. As a result, the outputs become active and work in phase with their inputs. Similarly, when the enable input is low, that driver is disabled, and their outputs are off and in the high-impedance state.

Description/ordering information (continued)

1.On the L293, external high-speed output clamp diodes should be used for inductive transient suppression. 2.A VCC1 terminal, separate from VCC2, is provided for the logic inputs to minimize device power dissipation. 3.The L293and L293D are characterized for operation from 0 C to 70C.

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Pin Diagram:

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The L293 and L293D are quadruple high-currenthalf-H drivers. The L293 is designed to providebidirectional drive currents of up to 1 A at voltages from 4.5 V to 36 V. The L293D is designed toprovide bidirectional drive currents of up to600-mA at voltages from 4.5 V to 36 V. Bothdevices are designed to drive inductive loads suchas relays, solenoids, dc and bipolar stepping motors, as well as other high-current/highvoltage loads in positive-supply applications. All inputs are TTL compatible. Each output is acomplete totem-pole drive circuit, with a Darlington transistor sink and a pseudo-Darlington source. Drivers are

enabled in pairs, with drivers 1 and 2 enabled by 1,2EN and drivers 3 and 4 enabled by 3,4EN. When an enable input is high, the associated drivers are enabled, and their outputs are activeand in phase with their inputs. When the enable input is low, those drivers are disabled, and their outputs areoff and in the high-impedance state. With the proper data inputs, each pair of drivers forms a full-H (or bridge) reversible drive suitable for solenoid or motor applications.

Features

Featuring Unitrode L293 and L293D Products Now From Texas Instruments Wide Supply-Voltage Range: 4.5 V to 36 V Separate Input-Logic Supply Internal ESD Protection Thermal Shutdown High-Noise-Immunity Inputs Functional Replacements for SGS L293 and SGS L293D Output Current 1 A Per Channel (600 mA for L293D) Peak Output Current 2 A Per Channel (1.2 A for L293D) Output Clamp Diodes for Inductive Transient Suppression (L293D)

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Controlling Motors While turning a motor on and off requires only one switch (or transistor) controlling the direction is deceptively difficult. It requires no fewer than four switches (or transistors) arranged in a clever way. H-Bridges These four switches (or transistors) are arranged in a shape that resembles an 'H' and thus called an H-Bridge. Each side of the motor has two transistors, one is responsible for pushing that side HIGH the other for pulling it LOW. When one side is pulled HIGH and the other LOW the motor will spin in one direction. When this is reversed (the first side LOW and the latter HIGH) it will spin the opposite way. DC Motor Example Confused? that's alright it all starts making sense with an example. Cut out the breadboard layout sheet below and download the example code from http://tinyurl.com/qcpah9 and play around. Stepper Motor Example (for use with 4, 5,6 & 8 wire motors) The Arduino IDE has an included library for controlling stepper motors. To test it out with this setup, plug the stepper motor in with coil A across OUT 1 & 2, and coil B across OUT 3 & 4. Then download example code from http://tinyurl.com/nyylun and play around.

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1. CIRCUITS AND THEIR OPERATION: 1.1 Circuit diagram:

3.2 Circuit operation:


Out new Combat robot is pc operated , it has got two barrel turret through bullet can be fired, pc camera in synchronization with the turret can rotate up and down ,left and right up to a safe firing limit. turret and camera mechanism has been installed on my spy robot vehicle, which has all the function like tank, Turing to any angle on its axis, moving forward and reverse turning left and right, running instantly into reverse direction.

This robot is mobile operated self powered, and has all the controls like a normal car. A pair of laser gun has been installed on it, so that it can fire on enemy remotely when required this is not possible until a wireless camera is installed. Wireless camera will send real time video and audio signals which could be seen on a remote monitor and action can be taken accordingly. It can silently enter into enemy area and send us all the information through its tiny camera eyes. It is designed for, fighting as well as suicide attack.

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1.1.1 SOFTWARE DEVELOPMENT: 1.1.2 Introduction:


4.1 Introduction: In this chapter the software used and the language in which the program code is defined is mentioned and the program code dumping tools are explained. The chapter also documents the development of the program for the application. This program has been termed as Source code. Before we look at the source code we define the two header files that we have used in the code. 4.2 Tools Used:

Figure 4.1 Keil Software- internal stages [Type text]

Keil development tools for the 8051 Microcontroller Architecture support every level of software developer from the professional applications 2.

Step1:

open the NEW Uversion project which is in the project option in

the tool bar.

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3.

Step2: save the project with the required name and click save button

Step:3 select the device


after saving the project.

from NXP options the window which comes

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Step 4: select the LPC 2148 from the NXP options

Step 5: click yes in the startup code of LPC 2148 window

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Step 6: select the new file from the file options to write the C code

Step 7: a new text file will open which we have to write the following code

Step 8 : write the code require for ur applications


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Step 9:save the text file as .C file

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Step 10: Add the saved .C file p by right clicking the Source Group Option1
and u will get drop down window in that select Add Files to Group

Step 11: select the saved .c file from the window which is showing to add
the file by clicking the add tab.

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Step 12: thus .C file is added to the Source Group is clearly seen

Step 13: press the icon that shows Rebuilt Target which proceeds for the
Linking if the .C file.

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Step 14:Re-built All Target files for complete process of assembling>Compiling ->linking-> generating .hex file

Step 15: press the start/stop debug icon for debugging of the code which
written. Following are debugging windows press F11 for step by step debug

Window:1

Window2

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4.1.2 Tools used:


The KEIL MDK-ARM is a complete software development environment for ARM7 (LPC 2148) and ARM9 processor-based devices. Flash the device using FLASH MAGIC, a free software utility sponsored by NXP.

LANGUAGE: All editions provide a complete Embedded C/C++ development environment and KEIL includes extensive middleware libraries. PLATFORM: WINDOWS XP

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5. RESULTS AND CONCLUSION: 5.1 Advantages:


As it can hit the targets (enemies) accurately help camera assembled to it.

Controlled remotely hence no loss of life during combat. Maneuvering in hazardous environment.

5.2 Disadvantages :

5.3 Applications:
1. This method can be implemented in OUR ARMY for attacking on enemies in Critical situations. 2. With this method enemy can be identified clearly by ROBOT wireless camera and attack by remote signals.

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5.4 Conclusion:

The project Mobile SPY Robot Using Wireless webcam has been successfully designed and tested. Integrating features of all the hardware components used have developed it. Presence of every module has been reasoned out and placed carefully thus contributing to the best working of the unit. Secondly, using highly advanced ICs and with the help of growing technology the project has been successfully implemented. .

BIBLIOGRAPHY

1 2 3 4 5 6 7

WWW.MITEL.DATABOOK.COM WWW.ATMEL.DATABOOK.COM WWW.FRANKLIN.COM WWW.KEIL.COM www.ask.com www.wikipedia.com www.palowireless.com/zigbee

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www.howstuffworks.com

REFERENCES 9 8051-MICROCONTROLLER AND EMBEDDED SYSTEM. Mohd. Mazidi. 10 EMBEDDED SOFTWARE PRIMER. David .E. Simon.

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