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R.M.

D ENGINEERING COLLEGE
R.S.M NAGAR, KAVARAIPETTAI 601206 GUMMIDIPOONDI TALUK, THIRUVALLUR DIST.

Certified

that

this

is

bonafide with He

record

work

done

by

Roll/Reg. /She is a

Number student of

in the R.M.D Engineering College, Kavaraipettai.

Faculty-in-Charge

Head of the Department

Date of Examination

Internal Examiner

External Examiner

INDEX
Sl. No. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. Date of Experiment Name of the Experiment Date of Submission Marks Page No. Signature of Staff

Full adder 4 to 1 multiplexer 3 to 8 address decoder 8 bit ripple carry adder 4 bit multiplier 4 bit counter 4 bit PRBS generator Test bench - full adder Test bench - Multiplexer Test bench 3 to 8 decoder Test bench 4 bit counter Test bench PRBS generator Implementation of Full adder Implementation of Multiplexer Implementation of Decoder Implementation of 8 bit adder Implementation of 4 bit multiplier Implementation of 4 bit counter Implementation of PRBS generator Implementation of Accumulator Simulation and Implementation of ALU SPICE simulation of MOS differential amplifier Inverter Layout and Simulation

Signature of the Head of the Dept. & date:

Full Adder
Ex. No: 1 Aim: To simulate Full adder using Verilog HDL using Structural and Dataflow modeling. Software Required: Xilinx ISE, ModelSim Theory: A combinational circuit that performs the addition of three bits is called a Full adder. The Circuit needs three binary inputs and produces two binary outputs namely sum and carry. The simplified Boolean expressions for sum and carry are Sum S = A B C Carry Cout = AB+BC+CA Date:

Program: // Structural Modeling module fuladins1(a, b, c, s, cr); input a; input b; input c; output s; output cr; xor (s,a,b,c); or (cr,a&b,b&c,c&a); endmodule // Data Flow Modeling 3

module fulad1(a, b, c, s, cr); input a; input b; input c; output s; output cr; assign s=a^b^c; assign cr=a&b|b&c|c&a; endmodule

Output:

Result:
Thus Full Adder was designed and simulated in Verilog HDL. 4 to 1 Multiplexer Ex.No:2 Aim: To simulate 4 to 1 multiplexer using Verilog HDL using Structural and Dataflow modeling. Software Required: Xilinx ISE, ModelSim Theory: A digital multiplexer is a combinational circuit that selects binary information from one of many inputs and directs it as a single output based on the selector lines. The 4:1 multiplexer has 4 inputs,2 selector lines and a single output

Date:

The simplified Boolean expression for output is Y = S0 S1A+S0S1B+S0S1C+S0S1D Program: // Structural Modeling module multiplexer (y,i,s); output y; input [3:0]i; input [1:0]s; wire a,b,c,d,e,f; not (a,s[0]); not (b,s[1]); and (c,i[0],a,b); and (d,i[1],a,s[1]); and (e,i[2],s[0],b); and (f,i[3],s[0],s[1]); or (y,c,d,e,f); endmodule 5

// Dataflow modeling module Mux(d, s, y); input [3:0] d; input [1:0] s; output y; wire a,b,c,e,f,g,h,i; assign a=~s[0]; assign b=~s[1]; assign c=(d[0]&b&a); assign e=(d[1]&s[0]&a); assign f=(d[2]&b&s[0]); assign g=(d[3]&s[0]&s[1]); assign h=c|e; assign i=g|f; assign y=h|i endmodule Output:

Result:
Thus a 4:1 multiplexer was designed and simulated using Verilog HDL.

3 to 8 Address Decoder
Ex. No: 3 Aim: To simulate 3:8 address decoder using verilog HDL using structural and dataflow modeling Software Required: Xilinx ISE, ModelSim Theory: A decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. e.g. n-to-2n, binary-coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding. Date:

Program: // Structural modeling module decoder(a,b,c,y0,y1,y2,y3,y4,y5,y6,y7); input a,b,c; output y0,y1,y2,y3,y4,y5,y6,y7 ; not(an,a); not(bn,b); not(cn,c); and(y0,an,bn,cn); and(y1,an,bn,c); and(y2,an,b,cn); and(y3,an,b,c); and(y4,a,bn,cn); and(y5,a,bn,c); and(y6,a,b,cn); 7

and(y7,a,b,c); endmodule

// Dataflow Modeling module decoder(y,x) output [7:0]y; input [2:0]x; wire a,b,c; assign a=x[0]; assign b=x[1]; assign c=x[2]; assign y[0]=a&b&c; assign y[1]=a&b&x[2]; assign y[2]=a&x[1]&c; assign y[3]=a&x[1]&x[2]; assign y[4]=x[0]&b&c; assign y[5]=x[0]&b&x[2]; assign y[6]=x[0]&x[1]&c; assign y[7]=x[0]&x[1]&x[2]; endmodule Output:

Result:
Thus a 3:8 decoder was designed and simulated using Verilog HDL.

8 bit Ripple Carry Adder


Ex.No:4 Aim: To simulate eight bit ripple carry adder using Verilog HDL using Structural and Dataflow modeling. Software Required: Xilinx ISE, ModelSim Theory : A combinational circuit that performs the addition of eight bits. b[7:0] a[7:0] Date:

ci n

Full adder

Full adder

Full adder

Full adder

Full adder

Full adder

Full adder

Full adder

cout

s[7:0] Program: module carryripple(a,b,cin,s,cout); input [7:0] a; input [7:0] b; input cin; output [7:0] s; wire [6:0] c; output cout; fa s0(a[0],b[0],cin,s[0],c[0]); fa s1(a[1],b[1],c[0],s[1],c[1]); fa s2(a[2],b[2],c[1],s[2],c[2]); fa s3(a[3],b[3],c[2],s[3],c[3]); fa s4(a[2],b[2],c[3],s[4],c[4]); fa s5(a[2],b[2],c[4],s[5],c[5]); 9

fa s6(a[2],b[2],c[5],s[6],c[6]); fa s7(a[2],b[2],c[6],s[7],cout); endmodule

module fulad1(a, b, c, s, cr); input a; input b; input c; output s; output cr; assign s=a^b^c; assign cr=a&b|b&c|c&a; endmodule OUTPUT:

10

Result:
Thus a ripple carry adder was designed and simulated using Verilog HDL.

4 bit Multiplier
Ex.No:5 Aim: To simulate four bit multiplier using Verilog HDL. Software Required: Xilinx ISE, ModelSim Theory : A combinational circuit that performs the multiplication of two four bit numbers to obtain a eight bit product. Date:

Program: module multiplier(m,q,pp); input [3:0]m; input [3:0]q; output [7:0]pp; wire [8:0]ppr; wire [14:0]cpr; base b11(m[0],q[0],0,0,pp[0],cpr[0]); base b12(m[1],q[0],0,cpr[0],ppr[0],cpr[1]); base b13(m[2],q[0],0,cpr[1],ppr[1],cpr[2]); 11

base b14(m[3],q[0],0,cpr[2],ppr[2],cpr[3]); base b21(m[0],q[1],ppr[0],0,pp[1],cpr[4]); base b22(m[1],q[1],ppr[1],cpr[4],ppr[3],cpr[5]); base b23(m[2],q[1],ppr[2],cpr[5],ppr[4],cpr[6]); base b24(m[3],q[1],cpr[3],cpr[6],ppr[5],cpr[7]); base b31(m[0],q[2],ppr[3],0,pp[2],cpr[8]); base b32(m[1],q[2],ppr[4],cpr[8],ppr[6],cpr[9]); base b33(m[2],q[2],ppr[5],cpr[9],ppr[7],cpr[10]); base b34(m[3],q[2],cpr[7],cpr[10],ppr[8],cpr[11]); base b41(m[0],q[3],ppr[6],0,pp[3],cpr[12]); base b42(m[1],q[3],ppr[7],cpr[12],pp[4],cpr[13]); base b43(m[2],q[3],ppr[8],cpr[13],pp[5],cpr[14]); base b44(m[3],q[3],cpr[7],cpr[14],pp[6],pp[7]); endmodule // Basic cell module module base(mi,qi,ppi,cin,pout,cout); input mi,qi,ppi,cin; output pout,cout; wire in; and(in,mi,qi); fulladder f1(in,ppi,cin,pout,cout); endmodule // Full adder module module fulladder(a, b, c, s, cr); input a; input b; input c; output s; output cr; assign s=a^b^c; assign cr=a&b|b&c|c&a; endmodule Output:

12

Result:
Thus a 4 bit multiplier was designed and simulated using Verilog HDL.

4 bit counter
Ex.No:6 Aim: To simulate four bit ripple counter using Verilog HDL. Software Required: Xilinx ISE, ModelSim Theory: A binary ripple counter consists of a series of four complementary flip-flops in which the output is given as a clock for the next higher order flip-flops. The complementary flip flops can be obtained using a T flip-flop. Q1 Clock input clk T Q clk T Q Q2 clk T Q Q3 clk T Q Q4 Date:

Program: // counter module module counter11(in, clkm,q); input in; input clkm; output [3:0]q; tff t1(in,clkm,q[0]); tff t2(in,q[0],q[1]); tff t3(in,q[1],q[2]); tff t4(in,q[2],q[3]); endmodule // T flip-flop module module tff(t,clk,q); input t,clk; output q; 13

reg q; initial q=1'b0; always @(negedge clk) begin if(t==1) q=~q; else q=q; end endmodule Output:

14

Result:
Thus a 4 bit counter was designed and simulated using Verilog HDL.

4 bit PRBS generator


Ex.No:7 Aim: To simulate four bit Pseudo random binary sequence generator. Software Required: Xilinx ISE, ModelSim Theory: A Pseudo random binary sequence generator is realize with the help of Maximal length Linear feedback shift register. It is constructed with the help of 4 bit shift register with a linear feedback. The linear feedback is made possible by an Ex-OR gate whose inputs are of maximal length. Date:

D CLK CLK

D CLK

D CLK

D CLK

Program: module prbs(clk,q); input clk; output [3:0]q; reg q; reg p; initial q = 4b0101; always @(posedge clk) begin p = q[3]^q[2]; q[3]=q[2]; q[2]=q[1]; q[1]=q[0]; q[0]=p; end 15

endmodule

Result:
16

Thus a pseudo random binary sequence generator was synthesized and simulated using Verilog HDL. Test Bench - Full Adder Ex.No:8 Aim: To create test bench to simulate full adder using behavioral modeling. Software Required: ModelSim Program: module fa(a,b,c,s,cy); input a,b,c; output s,cy; reg s,cy; always@(a or b or c) begin s=a^b^c; cy=a&b&c; end endmodule // Test bench module module testbench(); reg [2:0]a; wire s,cy; fa fa1 (a[0],a[1],a[2],s,cy); // Instantiate full adder module initial begin #10 a=3'b000; #10 a=3'b001; #10 a=3'b010; #10 a=3'b011; #10 a=3'b100; #10 a=3'b101; #10 a=3'b110; #10 a=3'b111; end endmodule Date:

17

Result: Thus test bench for full adder is created and simulated 18

Test Bench -Multiplexer Ex.No:9 Aim: To create test bench to simulate 4:1 multiplexer using behavioral modeling. Software Required: ModelSim Program: module multi ( d, s, y); input [3:0] d; input [1:0] s; output y; reg y; always @ (s or d) case (s) 2'b00: y = d[0]; 2'b01: y = d[1]; 2'b10: y = d[2]; 2'b11: y = d[3]; endcase endmodule // Test bench module module testbench; reg [3:0]d; reg [1:0]s; wire y; multi m1(d, s, y); // Instantiate multiplexer module initial begin #10 d = 4b0011; s = 2b00; #10 d = 4b1100; s = 2b01; #10 d = 4b1110; s = 2b10; #10 d = 4b1001; s = 2b11; end endmodule Date:

19

Result: Thus test bench for 4:1 multiplexer is created and simulated.

20

Test Bench - 3 to 8 address decoder Ex.No:10 Aim: To create test bench for 3 to 8 address decoder using behavioral modeling. Software Required: ModelSim Program: module adddecode (s,d); input [2:0] s; output[7:0] d; always @ (s) case (s) 3b000: d= 8h01; 3b001: d= 8h02; 3b010: d= 8h04; 3b011: d= 8h08; 3b100: d= 8h10; 3b101: d= 8h20; 3b110: d= 8h40; 3b111: d= 8h80; endcase endmodule module test_adddecode; reg [2:0] s; wire[7:0] d; adddecode decode_tb (s,d); initial begin #10 s= 3b000; #10 s= 3b001; #10 s= 3b010; #10 s= 3b011; #10 s= 3b100; #10 s= 3b101; #10 s= 3b110; #10 s= 3b111; end endmodule Date:

21

Result: Thus test bench for 3 to 8 address decoder was created and simulated. 22

Test Bench - 4 Bit Counter Ex.No:11 Aim: To create test bench to simulate four bit counter using behavioral modeling. Software Required: ModelSim Program: // counter module module countr (clk, q); input clk; output q; reg [3:0] q; initial q = 4'b0000; always @ (negedge clk) if (q == 4'b1111) q= 4'b0000; else q = q +1; endmodule // Test Bench module module testcountr; reg clk; wire [3:0] q; countr c1 (clk,q); initial clk = 1'b0; always #5clk = ~clk; endmodule Date:

23

Result: Thus test bench for four bit counter is created and simulated.

24

Test Bench - PRBS generator Ex.No:12 Aim: To create test bench to simulate 4 bit PRBS generator. Software Required: ModelSim Program: // counter module module prbs(clk,q); input clk; output q; reg [3:0]q; reg p; initial q = 4b0101; always @(posedge clk) begin p = q[3]^q[2]; q[3]=q[2]; q[2]=q[1]; q[1]=q[0]; q[0]=p; end endmodule // Test Bench module module testprbs; reg clk; wire [3:0] q; prbs p1 (clk,q); initial clk = 1'b0; always #5clk = ~clk; endmodule Date:

25

Result: Thus test bench for four bit counter is created and simulated. 26

Implementation of Full Adder


Ex.No:13 Aim: To synthesize and implement full adder circuit using Verilog HDL in the FPGA. Software Required: Xilinx ISE Hardware Required: 1. FPGA kit. Specifications: Family : Spartans 3 Device : XC3S400 Package : TQ144 2. General purpose I/O kit Program: module fulasd11(a, b, c, s, cr); input a; input b; input c; output s; output cr; reg s,cr; always @(a or b or c) begin s=a^b^c; cr=a&b|b&c|c&a; end endmodule Pin Details: Pin Input Output CLK Connector FRC1 74 FRC2 84 52 76 85 77 86 Pin number 79 78 87 89 82 90 80 92 83 96 Date:

Result:
Thus a full adder was synthesized and implemented using Verilog HDL. 27

Implementation of Multiplexer
Ex.No:14 Aim: To synthesize and implement 4:1 multiplexer circuit using Verilog HDL in the FPGA. Software Required: Xilinx ISE Hardware Required: 1. FPGA kit. Specifications: Family : Spartans 3 Device : XC3S400 Package : TQ144 2. General purpose I/O kit Program: module multiplexer( x,y,s ); input [3:0]x; input [1:0]s; output y; reg y; always @(d or s) begin case(s) 2b00: y=x[0]; 2b01: y=x[1]; 2b10: y=x[2]; 2b11: y=x[3]; endcase end endmodule Pin Details: Pin Input Output CLK Connector FRC1 74 FRC2 84 52 76 85 77 86 Pin number 79 78 87 89 82 90 80 92 83 96 Date:

Result:
Thus a 4:1 multiplexer was synthesized and implemented using Verilog HDL. 28

Implementation of Decoder
Ex.No:15 Aim: To synthesize and implement 3:8 decoder using Verilog HDL in the FPGA. Software Required: Xilinx ISE Hardware Required: 1. FPGA kit. Specifications: Family : Spartans 3 Device : XC3S400 Package : TQ144 2. General purpose I/O kit Program: module decoder(a,y); input [2:0]a; output [7:0]y; reg y; always @(a) case(a) 3'b000:y=8'h01; 3'b001:y=8'h02; 3'b010:y=8'h04; 3'b011:y=8'h08; 3'b100:y=8'h10; 3'b101:y=8'h20; 3'b110:y=8'h40; 3'b111:y=8'h80; endcase endmodule Pin Details: Pin Input Output CLK Connector FRC1 74 FRC2 84 52 76 85 77 86 Pin number 79 78 87 89 82 90 80 92 83 96 Date:

Result:
Thus a 3:8 decoder was synthesized and implemented using Verilog HDL. 29

Implementation of 8 Bit Adder


Ex.No:16 Aim: To synthesize and implement eight bit adder using Verilog HDL in the FPGA. Software Required: Xilinx ISE Hardware Required: 1. FPGA kit. Specifications: Family : Spartans 3 Device : XC3S400 Package : TQ144 2. General purpose I/O kit Program: module eightbitadder(a,s); input [7:0]a; output [7:0]s; reg s; reg [7:0]b; initial b=8'b00000000; always @(a or b) s=a+b; endmodule Date:

Pin Details: Pin Input Output CLK Connector FRC1 74 FRC2 84 52 76 85 77 86 Pin number 79 78 87 89 82 90 80 92 83 96

Result:
Thus a eight bit adder was synthesized and implemented using Verilog HDL. 30

Implementation of 4 bit Multiplier


Ex.No:17 Aim: To synthesize and implement four bit multiplier using Verilog HDL in the FPGA. Software Required: Xilinx ISE Hardware Required: 1. FPGA kit. Specifications: Family : Spartans 3 Device : XC3S400 Package : TQ144 2. General purpose I/O kit Program: module multiplier(a,b,p); input [3:0]a; input [3:0]b; output [7:0]p; reg p; always @(a or b) p=a*b; endmodule Pin Details: Pin Input Output CLK Connector FRC1 74 FRC2 84 52 76 85 77 86 Pin number 79 78 87 89 82 90 80 92 83 96 Date:

Result:
Thus a four bit multiplier was synthesized and implemented using Verilog HDL. 31

Implementation of 4 bit Counter


Ex.No:18 Aim: To synthesize and implement four bits counter using Verilog HDL in the FPGA. Software Required: Xilinx ISE Hardware Required: 1. FPGA kit. Specifications: Family : Spartans 3 Device : XC3S400 Package : TQ144 2. General purpose I/O kit Program: module countfpga1(clk, q); input clk; output [3:0]q; reg q; reg z; reg [19:0]c; initial begin q=4'b0000; c=20'h00000; z=1b0; end always @(posedge clk) if(c==20'hfffff) begin c=20'h00000; z=~z; end else c=c+1; always @(posedge z) if(q==4'b1111) q=4'b0000; else q=q+1; endmodule Date:

32

Pin Details: Pin Input Output CLK Connector FRC1 74 FRC2 84 52 76 85 77 86 Pin number 79 78 87 89 82 90 80 92 83 96

Result:
Thus a four bit counter was synthesized and implemented using Verilog HDL. 33

Implementation of Pseudo Random Binary Sequence Generator


Ex.No:19 Aim: To synthesize and implement four bits pseudo random sequence generator using Verilog HDL in the FPGA. Software Required: Xilinx ISE, IMPACT Hardware Required: 1. FPGA kit. Specifications: Family : Spartans 3 Device : XC3S400 Package : TQ144 2. General purpose I/O kit Circuit Diagram: Date:

D CLK CLK

D CLK

D CLK

D CLK

Program: module prbs(clk,q); input clk; output [3:0]q; reg q; reg [19:0]c; reg p; reg ck; initial begin ck=1'b0; q=4'b0111; c=20'h00000; end always @(posedge clk) if(c==20'hfffff) begin 34

c=20'h00000; ck=~ck; end else c=c+1; always @(posedge ck) begin p = q[3]^q[2]; q[3]=q[2]; q[2]=q[1]; q[1]=q[0]; q[0]=p; end endmodule Pin Details: Pin Input Output CLK Connector FRC1 74 FRC2 84 52 76 85 77 86 Pin number 79 78 87 89 82 90 80 92 83 96 -

Result:
Thus a pseudo random binary sequence generator was synthesized and implemented using Verilog HDL. 35

Implementation of Accumulator
Ex.No:20 Aim: To synthesize, simulate and implement accumulator using Verilog HDL in the FPGA. Software Required: Xilinx ISE, iMPACT Hardware Required: 1. FPGA kit. Specifications: Family : Spartans 3 Device : XC3S400 Package : TQ144 2. General purpose I/O kit Block diagram: Date:

Input

Accumulator Result

Arithmetic Logic Unit

Program: module accumulator(a,q); input [3:0]a; output reg [3:0]q; initial q=4'b0000; always@(a) q=q+a; endmodule Pin Details: Pin Connector Input FRC1 74 Output FRC2 84 CLK 52

76 85

77 86

Pin number 79 78 87 89

82 90

80 92

83 96

Result:
Thus a accumulator was synthesized and implemented using Verilog HDL. 36

Simulation and Implementation of Arithmetic Logic Unit


Ex.No:21 Aim: To synthesize, simulate and implement Arithmetic Logic Unit using Verilog HDL in the FPGA. Software Required: Xilinx ISE, iMPACT Hardware Required: 1. FPGA kit. Specifications: Family : Spartans 3 Device : XC3S400 Package : TQ144 2. General purpose I/O kit Control Logic: OPCODE decode logic Date:

37

module opcod (op, os, bs,cs); input [2:0]op; output reg [2:0]os; output reg bs; output reg [1:0] cs; always @ (op) begin os[0] = ~op[0] &op[2]; os[1] = (op[0] &~op[1]&op[2])|( ~op[0]&op[1]&op[2]); os[2]= op[0]&op[1]&op[2]; bs=op[1]&~op[2]; cs[0]=~op[0]&op[1]&~op[2]; cs[1]=op[0]&~op[2]; end endmodule

38

Arithmetic Logic Unit

Program: module alu (a,b,cin,op,result, cout); input a,b,cin; input [2:0]op; output result, cout; reg result; reg cout; reg clocal; reg blocal; reg [2:0]os; reg bs; reg [1:0] cs; always @ (op) begin os[0] = ~op[0] &op[2]; os[1] = (op[0] &~op[1]&op[2])|( ~op[0]&op[1]&op[2]); os[2]= op[0]&op[1]&op[2]; bs=op[1]&~op[2]; cs[0]=~op[0]&op[1]&~op[2]; cs[1]=op[0]&~op[2]; end always @(op or a or b or cin) case (cs) 2'b00:clocal=1'b0; 39

2'b01:clocal = 1'b1; 2'b10:clocal=cin; endcase always @ (op or a or b or cin) case (bs) 1'b0:blocal=b; 1'b1:blocal= ~b; Endcase always @ (op or a or b or cin) case (os) 3'b000: begin result = a^blocal^clocal; cout = a&blocal |blocal&clocal|a&clocal; end 3'b001:result = a& blocal; 3'b010:result= a|blocal; 3'b011: result = a^blocal; 3'b100:result= ~a; endcase endmodule

40

Pin Details: Pin Input Output CLK Connector FRC1 74 FRC2 84 52 76 85 77 86 Pin number 79 78 87 89 82 90 80 92 83 96

Result:
Thus a arithmetic logic unit was synthesized, simulated and implemented using Verilog HDL. 41

Spice Simulation of MOS Differential Amplifier


Ex.No:22 Aim: To simulate MOS differential amplifier in schematic entry and SPICE program using PSPICE. Software Required: OrCAD Capture ,AD student Schematic Entry: // Transient analysis Date:

0
12V V3

R 2 1MEG M1 VO FF = 0 V A M P L = .1 FR EQ = 10K V1 M b re a k N

1M EG R 1 M2 M b r e a kV NO F F = 0 V A M P L = .1 1 FR EQ = 10K V2

R 3 400

12V V4

42

// Frequency Analysis
0V

0
12V V3

R 2 M 1 .1 V a c 0Vdc V5 0V

1 2 .0 0 V

1M EG R 1 M2

1M EG
V+

V-

M b re a k N

0V -7 2 3 .5 m V

M b re a k N

0V .1 V a c 0Vdc

V6

R 3 400

12V V4

43

Program: // Transient Analysis MOS differential amplifier R1 1 2 9K R2 1 5 9K R3 4 7 4K V1 1 0 DC 12 V2 0 7 DC 12 V3 3 0 SIN 0 0.1 10K 0 1E-4 0 V4 6 0 SIN 0 0.11 10K 0 1E-4 180 M1 2 3 4 4 NMOD W=1u L=1u M2 5 6 4 4 NMOD w = 1u L=1u .Model NMOD NMOS (Kp=2 Vto=.7 Rg=0 Rds=1MEG Rb=0 Rs=5 Rd=5 CBD=5PF CBS=2pf CGSO=1pf CGDO=1pf CGBO=1pf) .Tran (0.1m 1m) .plot Tran v(2) v(5) .PROBE .end

44

// Frequency Analysis MOS differential amplifier R1 1 2 9K R2 1 5 9K R3 4 7 4K V1 1 0 DC 12 V2 0 7 DC 12 V3 3 0 AC 0.1 V4 6 0 AC -0.1 M1 2 3 4 4 NMOD W=1u L=1u M2 5 6 4 4 NMOD w = 1u L=1u .Model NMOD NMOS (Kp=2 Vto=.7 Rg=0 Rds=1MEG Rb=0 Rs=5 Rd=5 CBD=5PF CBS=2pf CGSO=1pf CGDO=1pf CGBO=1pf) .AC dec 10K 10 10MEG .plot ac vm(2) vm(5) .PROBE .end

45

Result: Thus MOS differential Amplifier is designed and simulated by giving schematic and program input using PSPICE. 46

Inverter Layout and Simulation


Ex.No:23 Step I- Layout The basic transistor circuit of inverter is given in figure below Date:

Inverter Circuit
Select coms0.25.rul foundry file from file menu. Click new and it with name Inverter.msk Begin to draw your layout with Microwind layout editor. You have already drawn NMOS layout and draw PMOS layout. (You can draw them similarly or there is a shortcut for MOS generator in the palette menu) Keep the dimensions as follows: nMOS L = 0.25m W = 0.5m pMOS L = 0.25m W = 1.25m Width of pMOS should be kept 2.5 time more than nMOS to have matching delays. Run DRC by selecting: >Analysis>Design Rule Checker If your layout is correct, then no messages will appear. If there are some errors, then the warning messages will appear near the errors. Please modify your layout until no error messages appear. Your layout should look like figure 1: Save your layout.

Step II - Add properties to input signals for simulation Click on the clock icon and then click on the input of the inverter in the layout then double click the clock of layout. A clock window appears & make sure the properties on the windows is below: Low-level 0.0V High Level 2.5V Time low 1.95 Rise time 0.05 Time high 1.95 Fall time 0.05 ns Push Assign Similarly assign the output node name Out Also assign the Vdd+ and Vss- to the PMOS and NMOS respectively (Make sure that n-well is also assigned Vdd) Finally save your layout.

Step III- Simulation Click on Run simulation 47

You will see the desired output of the inverter. The output waveform is shown in the given figure 2:

Figure 1: Inverter Layout

Figure 2: Inverter Output

Result: 48

Thus layout of CMOS inverter is designed and simulated.

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