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4, JULY 2006
I. INTRODUCTION
Fig. 1. Synchronous buck converter proof-of-concept prototype: V = 5 V,
V = 1 V, 0< I = =
<5 A, L 4.3 H, C 705 F, f = 200 kHz,
B ECAUSE of significantly lower conduction losses,
synchronous rectifiers are now used in essentially all
low-voltage dc power supplies including converters for
MOSFETs: Si4888DY.
Fig. 4. Measured efficiency and duty-cycle command D as functions of the Fig. 5. Experimental prototype.
dead-time t in the experimental prototype.
i d
Fig. 6. Load transient simulation. Inductor current , duty cycle command ,
D
average value of the duty cycle command , output voltage v .
duty cycle with the previous one. The wait block ensures that the
system has reached a new steady state in each step of the search.
Decreasing the dead-time continues until an increase in the
duty cycle command is detected. Then, the dead-time search
stops and provides the final optimum dead-time commands to
the DPWM. In our prototype, the same dead-time search algo-
rithm is performed for first, and then for .
There are two issues that should be discussed in more detail:
the precision of the dead time algorithm with respect to the true
optimum efficiency, and the selection of the final value of the
optimum dead-time.
(12)
and initial values of the inductor currents at the time when the
switch is turned off. In the circuit of Fig. 10(b), the energy
stored in the parasitic inductors is dissipated in the resonant cir-
cuit formed by and . An upper bound for the
net increase in the average switch-node voltage compared to
the case of zero overlap is obtained by solving the circuit in
Fig. 10(b), and integrating over the time long enough for
the ringing to subside
(13)
The result, (14), shows that the overlap, even in the worst case
of relatively large parasitic inductances, results in a net negative
contribution to the average switch-node voltage . However,
as a result of , (14) also shows that larger parasitic in-
ductances result in a slower decrease in the average
switch-node voltage. As a result, the duty cycle command as
a function of the dead time has a shallower minimum compared
to the efficiency, which exhibits a sharp drop when the overlap in
conduction occurs. To mitigate this problem, the converter cir-
cuit should be designed with the parasitic inductances as small
as possible, which is a very common practice for a number of
other reasons.
The optimization algorithm (as shown in Fig. 8) approaches
the optimum dead time starting from a safe value , and
stops at the last point where a decrease in the duty cycle
Fig. 11. Switch node voltage v (t), waveform and the gate drive signals v is observed. As a result, even if the parasitic inductances have
and v . relatively large values, the algorithm results in the dead times
away from the overlap conduction of the switches, and achieves
efficiency close to the true optimum.
the converter circuit during (a) the overlap time and (b) Fig. 12 shows experimental digital data collected from the
immediately after the switch turns off. FPGA digital controller during the operation of the optimization
In Fig. 10, and are the parasitic series inductances, algorithm of Fig. 8. The figure shows the optimization search for
and are the on-resistances of the two switches and the dead-time commands and and the resulting changes
is the parasitic output capacitance of the switch . For in the average duty cycle command . The algorithm starts from
simplicity, the output filter inductor is replaced by a constant the safe dead-time values typical for constant dead-time realiza-
current source . The circuit analysis is simplified by assuming tions: 200 ns and 220 ns. The efficiency of
that , which represents the the converter at this operating point is 88%.
worst case of relatively large parasitic inductances. The system is triggered before time 0. At the point “a,” the
During the cross-conduction overlap the current builds dead-time search algorithm for starts decreasing the value
up through the series connection of the switch on resistances of with a step change of 10 ns. At the points where
and the parasitic inductances. The switch-node voltage the steady state duty cycle is decreased, the value of is
is significantly reduced compared the ideal , as stored in the register. At the point “c” the dead-time is
shown in Fig. 11 waveform. By solving the circuit in Fig. 10(a), too short, which results in a decrease of the average value of
and integrating the voltage during , we obtain an the switch node voltage. As a result, the compensator increases
1000 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006
Fig. 12. Experimental digital data collected from the FPGA digital controller
for the values of t ; t commands, and the average duty cycle command D .
The data were collected by the Xilinx “Chipscope,” which functions as a logic
analyzer module embedded on the FPGA.
V. DYNAMIC OPERATION
In this section, we discuss several options for triggering the
optimization algorithm of Section IV. In principle, the complete
optimization that starts from sufficiently long, safe dead times
should be performed upon power up or reset of the converter.
In normal operation, there are several options of triggering the
optimization. For example, the optimization can be performed To avoid triggering the dead-time optimization algorithm
periodically, starting from the previously determined optimum upon relatively small changes in operating conditions, activa-
values for the dead-time commands. Another option is to uti- tion of the signal trans according to (15) can be delayed by a
lize the flexibility of the digital controller implementation and short interval from the time a difference between and
trigger the optimization algorithm only when a change in the occurs. Once the trans signal is activated, the dead-times
operating condition is detected. An implementation of this op- and are increased to the safe values, and ,
tion is described in this section. respectively. After the converter reaches a new steady-state
A transient in the duty cycle command can be used as an operating point , the signal trans is deactivated, which
indication of a change in the operating conditions. A difference triggers the optimization algorithm.
between the duty cycle command and its average value Table I summarizes the definitions of the optimization
indicates that a transient occurs. The corresponding logic signal algorithm and transient detection parameters. The
trans is generated as follows: values are chosen as in constant dead-time realizations: to
ensure non-overlapping switch commutation under worst-case
combination of gate-drive delays and operating conditions.
(15) In the experimental prototype switching at 200 KHz,
YOUSEFZADEH AND MAKSIMOVIĆ: SENSORLESS OPTIMIZATION OF DEAD TIMES IN DC–DC CONVERTERS 1001
optimum values could be stored in a look-up table addressed [6] J. Kimbal and P. T. Krein, “Continuous-time optimization of gate
by the average duty-cycle command (or by other available timing for synchronous rectification,” in Proc. IEEE Midwest Symp.,
1997, pp. 1015–1018.
signals), thus eliminating the need to retrigger the dead-time [7] A. V. Peterchev and S. R. Sanders, “Digital loss-minimizing multi-
search. Current research efforts are directed towards evaluating mode synchronous buck converter control,” in Proc. IEEE PESC, 2004,
these and other options in the presence of repeated or unpre- pp. 3694–3699.
[8] J. A. Abu Qahouq, H. Mao, H. J. Al Atrash, and I. Batarseh, “Maximum
dictable load or input voltage transients. efficiency point tracking (MEPT) method and dead time control,” in
Proc. IEEE PESC, 2004, pp. 3700–3706.
VI. CONCLUSION [9] V. Yousefzadeh, N. Wang, D. Maksimovic, and Z. Popovic, “Digitally
controlled DC–DC converter for RF power amplifier,” in Proc. IEEE
This paper introduces an approach to achieve optimum dead APEC, 2004, pp. 81–87.
[10] A. Syed, E. Ahmed, and D. Maksimovic, “Digital PWM controller
times in dc–dc converters with synchronous rectifiers without with feed-forward compensation,” in Proc. IEEE APEC’04, 2004, pp.
sensing any of the power-stage signals other than the output 60–66.
voltage (which is sensed for the purpose of closed-loop dc [11] H. Peng and D. Maksimovic, “Digital current mode controller for
DC–DC converters,” in Proc. 20th Annu. IEEE APEC, Mar. 2005, pp.
voltage regulation anyway). The dead-times are adjusted to 899–905.
minimize the average duty-cycle command, which coincides [12] B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-fre-
with maximization of the converter efficiency in steady state quency digital PWM controller IC for DC–DC converters,” IEEE
Trans. Power Electron., vol. 18, no. 1, pp. 438–446, Jan. 2003.
operation. The performance is unaffected by parameter or
temperature variations, operating conditions, zero-voltage or Vahid Yousefzadeh (S’03) received the B.S. degree
hard-switching operation, size or type of the power devices, or in electrical engineering from Amirkabir University
any gate-drive or circuit implementation details. The method of Technology, Tehran, Iran, in 1994 and the M.S. de-
gree from the University of Colorado at Boulder in
is particularly well suited for digital controller implementa- 2004 where he is currently pursuing the Ph.D. degree.
tion, requiring only relatively small additional digital logic From 1994 to 2002, he was a Design and Research
resources. No additional analog components or modifications Engineer with Namvaran, and Bina-Afzar Engi-
neering, Tehran, where he was involved with power
of standard gate-drive circuitry are needed. A proof-of-concept system and power electronics design engineering.
digitally controlled 5 V-to-1 V, 5-A, 200-KHz synchronous His research interests include modeling, simulation,
and digital control techniques in power electronics.
buck converter has been constructed to demonstrate prac-
tical implementation of the sensorless dead-time optimization
algorithm.
Dragan Maksimovic (M’89) received the B.S. and
M.S. degrees in electrical engineering from the Uni-
REFERENCES versity of Belgrade, Belgrade, Yugoslavia, in 1984
[1] S. Mapus, “Predictive Gate Drive Boosts Synchronous dc/dc Power and 1986, respectively, and the Ph.D. degree from
Converter Efficiency,” Appl. Rep. SLUA281, Texas Instruments, Apr. the California Institute of Technology, Pasadena, in
2003. 1989.
[2] P.T. Krein and R.M. Bass, “Autonomous control technique for high- From 1989 to 1992, he was with the University of
performance switches,” IEEE Trans. Ind. Electron., vol. 39, no. 3, pp. Belgrade. Since 1992, he has been with the Depart-
215–222, Jun. 1992. ment of Electrical and Computer Engineering, Uni-
[3] B. Acker, C. R. Sullivan, and S. R. Sanders, “Synchronous rectification versity of Colorado at Boulder, where he is currently
with adaptive timing control,” in Proc. IEEE PESC, 1995, pp. 88–95. an Associate Professor and Co-Director of the Col-
[4] W. Lau and S. R. Sanders, “An integrated controller for a high fre- orado Power Electronics Center (CoPEC). His current research interests include
quency buck converter,” in Proc. IEEE PESC, 1997, pp. 246–254. power electronics for low-power, portable systems, digital control techniques,
[5] O. Trescases, W. T. Ng, and S. Chen, “Precision gate drive timing in and mixed-signal integrated circuit design for power electronics.
a zero-voltage switching DC–DC converter,” in Proc. IEEE Int. Symp. Dr. Maksimovic received the NSF CAREER Award in 1997 and the Power
Power Semicond. Devices ICs, 2004, pp. 55–58. Electronics Society Transactions Prize Paper Award.