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UC284XA UC384XA

HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER


NOT FOR NEW DESIGN

FEATURES TRIMMED OSCILLATOR DISCHARGE CURRENT CURRENT MODE OPERATION TO 500kHz AUTOMATIC FEED FORWARD COMPENSATION LATCHING PWM FOR CYCLE-BY-CYCLE CURRENT LIMITING INTERNALLY TRIMMED REFERENCE WITH UNDERVOLTAGE LOCKOUT HIGH CURRENT TOTEM POLE OUTPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LOW START-UP CURRENT (< 0.5mA) DOUBLE PULSE SUPPRESSION

Figure 1. Package

DIP-8

SO-8

Table 1. Order Codes


Part Number UC2842AD1; UC3842AD1; UC2843AD1; UC3843AD1; UC2844AD1; UC3844AD1; UC2845AD1; UC3845AD1 UC2842AN; UC3842AN; UC2843AN; UC3843AN; UC2844AN; UC3844AN; UC2845AN; UC3845AN Package SO-8

2 DESCRIPTION The UC384xA family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lockout featuring start-up current less than 0.5mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off-state.

t e l o s Ob

Figure 2. Block Diagram (toggle flip flop used only in UC3844A and UC3845A)
Vi 7

o r P e
GROUND 5 RT/CT 4

c u d
34V

) s t(

o s b O -

Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842A and UC3844A have UVLO thresholds of 16V (on) and 10V (off), ideally suited off-line applications The corresponding thresholds for the UC3843A and UC3845A are 8.5 V and 7.9V. The UC3842A and UC3843A can operate to duty cycles approaching 100%. A range of the zero to < 50 % is obtained by the UC3844A and UC3845A by the addition of an internal toggle flip flop which blanks the output off every other clock cycle.

P e t e l

ro

c u d

) s t(

DIP-8

UVLO S/R 5V REF INTERNAL BIAS VREF GOOD LOGIC OSC ERROR AMP. 2R R 1V T

VREF 5V 50mA

2.50V

OUTPUT

VFB COMP CURRENT SENSE

2 1 3

+ -

S R CURRENT SENSE COMPARATOR


D95IN331

PWM LATCH

May 2004

REV. 5 1/16

UC384XA - UC284XA
Table 2. Absolute Maximum Ratings
Symbol Vi Vi IO EO Supply Voltage (Ii < 30mA) Output Current Output Energy (capacitive load) Analog Inputs (pins 2, 3) Error Amplifier Output Sink Current Ptot Ptot Tstg TJ TL Power Dissipation at Tamb 25 C (DIP-8) Power Dissipation at Tamb 25 C (SO-8) Storage Temperature Range Junction Operating Temperature Lead Temperature (soldering 10s) Parameter Supply Voltage (low impedance source) Value 30 Self Limiting 1 5 0.3 to 5.5 10 1.25 800 65 to 150 40 to 150 300 A J V mA W mW C C C Unit V

* All voltages are with respect to pin 5, all currents are positive into the specified terminal.

Figure 3. DIP-8/SO-8 Pin Connection (Top view)

COMP VFB ISENSE RT/CT

1 2 3 4
D95IN332

8 7 6 5

VREF

Table 3. Pin Description


N 1 2 3 Pin COMP VFB

o s Ob
4 5 6 7 8

let

ISENSE RT/CT

d o r P e

This pin is the Error Amplifier output and is made available for loop compensation. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible. This pin is the combined control circuitry and power ground. This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin. This pin is the positive supply of the control IC. This is the reference output. It provides charging current for capacitor CT through resistor RT.

uc

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b O -

so

e t le

Vi

OUTPUT

o r P

c u d

) s t(

GROUND

Function

GROUND OUTPUT VCC Vref

2/16

UC384XA - UC284XA
Table 4. Thermal Data
Symbol Rth j-amb Parameter Thermal Resistance Junction-ambient Max. DIP-8 100 SO-8 150 Unit C/W

Table 5. Electrical Characteristcs ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85C for UC284XA; 0 < Tamb < 70C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
Symbol Parameter Test Condition UC284XA Min. 4.95 Typ. 5.00 2 3 0.2 4.9 50 5 -30 Tj = 25C VCC = 12V to 25V TA = Tlow to Thigh (peak to peak) TJ = 25C 47 -100 52 5 25 5.1 4.82 50 5 Max. 5.05 20 25 UC384XA Min. 4.90 Typ. 5.00 2 3 0.2 Max. 5.10 20 25 5.18 Unit

REFERENCE SECTION VREF VREF VREF Output Voltage Line Regulation Load Regulation Total Output Variation eN Output Noise Voltage Long Term Stability Tj = 25C Io= 1mA 12V Vi 25V 1 Io 20mA (Note 2) Line, Load, Temperature 10Hz f 10KHz Tj = 25C (note 2)
Tamb

V mV mV mV/C V V

VREF/T Temperature Stability

= 125C, 1000Hrs

(note 2)

ISC
fOSC

Output Short Circuit Frequency

-180 57 1 8.8 2.55 -1

OSCILLATOR SECTION fOSC/V Frequency Change with Volt. VREF/T Frequency Change with Temp. VOSC Idischg V2 Ib BW PSRR Io Oscillator Voltage Swing Discharge Current (VOSC =2V) Input Voltage Input Bias Current AVOL Unity Gain Bandwidth Output Sink Current

ERROR AMP SECTION

Power Supply Rejec. Ratio

t e l o s Ob
Io GV V3 SVR Ib Gain

o r P e

c u d

VPIN1 = 2.5V

VFB = 5V

2V Vo 4V TJ = 25C

) s t(

b O -

so
7.8 65 0.7 60 2

e t le
0.2 1.6 8.3 2.50 -0.1 90 1 70 12 -1 6.2 0.8

o r P
-30 47 7.8

c u d
-100 52 0.2 5 1.6 8.3 2.50 -0.1 90 1 70 12 -1 6.2 0.8

) s t(
25 57 1 8.8

mV mA KHz % % V mA V A dB MHz dB mA mA V

-180

2.45

2.42 65 0.7 60 2 -0.5 5

2.58 -2

12V Vi 25V VPIN2 = 2.7V VPIN1= 1.1V VPIN2 = 2.3V VPIN1 = 5V VPIN2 = 2.3V;RL = 15K to Ground VPIN2 = 2.7V;RL = 15K to Pin 8 (note 3 & 4) VPIN1 = 5V (note 3) 12 Vi 25V (note 3)

Output Source Current VOUT High VOUT Low

-0.5 5

1.1

1.1

CURRENT SENSE SECTION 2.85 0.9 3 1 70 -2 150 -10 300 3.15 1.1 2.85 0.9 3 1 70 -2 150 -10 300 3.15 1.1 V/V V dB A ns Maximum Input Signal Supply Voltage Rejection Input Bias Current Delay to Output

3/16

UC384XA - UC284XA
Table 5. Electrical Characteristcs (continued) ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85C for UC284XA; 0 < Tamb < 70C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
Symbol Parameter Test Condition UC284XA Min. Typ. 0.1 1.6 13 12 13.5 13.5 0.7 50
(2)

UC384XA Min. Typ. 0.1 1.6 13 12 1.2 150 150 13.5 13.5 0.7 50 50 1.2 150 150 Max. 0.4 2.2

Max. 0.4 2.2

Unit

OUTPUT SECTION VOL VOH VOLS tr tf Output Low Level Output High Level UVLO Saturation Rise Time Fall Time ISINK = 20mA ISINK = 200mA ISOURCE = 20mA ISOURCE = 200mA VCC = 6V; I SINK = 1mA Tj = 25C CL = 1nF Tj = 25C CL = 1nF UNDER-VOLTAGE LOCKOUT SECTION Start Threshold Min Operating Voltage After Turn-on PWM SECTION Maximum Duty Cycle Minimum Duty Cycle TOTAL STANDBY CURRENT Ist Start-up Current X842A/3A X844A/5A 94 X842A/4A X843A/5A X842A/4A 15 7.8 9 16 8.4 10 17 9.0 11
(2)

V V V V V ns ns

50

14.5 7.8 8.5

Vi = 6.5V for UCX843A/ 45A

Vi = 14V for UCX842A/44A Ii Viz Operating Supply Current Zener Voltage

t e l o s Ob

Notes: 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close to Tamb as possible. 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VPIN2 = 0. 4. Gain defined as : A = VPIN1/VPIN3; 0 VPIN3 0.8V 5. Adjust Vi above the start threshold before setting at 15 V.

o r P e

c u d

VPIN2 = VPIN3 = 0V Ii = 25mA 30

) s t(

b O -

so
47

e t le
96 48 0.3 0.3 12 36

o r P
94 47 0

c u d
16 8.4 10 96 48

17.5 9.0

) s t(
50 0

V V V

11.5

100 50

100

% % % mA mA mA V

0.5 0.5 17 30

0.3 0.3 12 36

0.5 0.5 17

4/16

UC384XA - UC284XA
Figure 4. Open Loop Test Circuit.
VREF 4.7K 2N2222 100K ERROR AMP. ADJUST 4.7K 1K ISENSE ADJUST 5K COMP VFB ISENSE RT/CT RT VREF 1 2 3 4 8 7 Vi 0.1F 6 5 OUTPUT GROUND 1W 1K OUTPUT A 0.1F Vi

CT
D95IN343

GROUND

High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 K potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Figure 5. Oscillator Frequency vs Timing Resistance
fo (Hz)
D96IN362

Figure 7. Oscillator Discharge Current vs. Temperature.


Idischg (mA)

1M
CT =4 70

1nF

pF

100K

2.2

nF

4.7

nF

10K

1K 300

1K

Figure 6. Maximum Duty Cycle vs Timing Resistor

o s Ob
80 60 40 20

fo (Hz)

let

o r P e
3K

10K

c u d
30K

) s t(
RT()

o s b O 8.0 7.5 7.0

8.5

e t le

o r P

c u d

) s t(

D95IN335

Vi=15V VOSC=2V

-55

-25

25

50

75

100 TA(C)

Figure 8. Error Amp Open-Loop Gain and Phase vs. Frequency.


(dB) 80
D95IN337

D96IN363

30 60 90 120 150

Gain
60 40 20 0 -20 10

Vi=15V VO=2V to 4V RL=100K TA=25C

Phase

0 300 1K 3K 10K 30K

RT()

100

1K

10K

100K

1M

180 f(Hz)

5/16

UC384XA - UC284XA
Figure 9. Current Sense Input Threshold vs. Error Amp Output Voltage.
Vth (V) 1.0
D95IN338

Figure 12. Output Saturation Voltage vs. Load Current.


Vsat (V)
D95IN341

Vi=15V
-1

Vi

TA=25C
0.8
-2

Source Saturation (Load to Ground) TA=25C TA=-40C

TA=125C
0.6
3

Vi=15V 80s Pulsed Load 120Hz Rate

0.4

TA=-40C TA=25C Sink Saturation (Load to Vi)


0 200 400 600

TA=-40C
0.2 0.0
1 0

GND
IO(mA)

VO(V)

Figure 10. Reference Voltage Change vs. Source Current..


60
D95IN339

Figure 13. Supply Current vs. Supply Voltage.


Ii (mA) 20

Vi=15V
50 40

TA=-40C TA=125C
15

30 20 10 0 0 20 40 60 80

Figure 11. Reference Short Circuit Current vs. Temperature..


ISC (mA)

t e l o s Ob
90 80 70 60 50 -55 -25

100

d o r P e

t c u

100 Iref(mA)

) s (

o s b O 10 5 0 0

TA=25C

UCX843/45

10

UCX842/44

P e t e l

d o r

uc

D95IN342

) s t(

RT=10K CT=3.3nF VFB=0V ISense=0V TA=25C

20

30

Vi(V)

D95IN340

Vi=15V RL0.1

25

50

75

100 TA(C)

6/16

UC384XA - UC284XA
Figure 14. Output Waveform. Figure 15. Output Cross Conduction

Figure 16. Oscillator and Output Waveforms.


Vi 7 8 5V REG PWM RT CLOCK 4 OSCILLATOR ID CT 5 OUTPUT 6 OUTPUT CT

GND

Figure 17. Error Amp Configuration.

t e l o s Ob

o r P e
Zi

c u d

) s t(

o s b O 2.5V

e t le
CT OUTPUT

o r P

LARGE RT/SMALL CT

c u d

) s t(

SMALL RT/LARGE CT

D95IN344

1mA + VFB COMP Zf


D95IN345

2 1

7/16

UC384XA - UC284XA
Figure 18. Under Voltage Lockout.
7 ON/OFF COMMAND TO REST OF IC

Vi

ICC

UC3842A UC3843A UC3844A UC3845A VON VOFF 16V 10V 8.4V 7.6V

<17mA

<0.5mA VOFF VON

VCC

D95IN346mod

Figure 19. Current Sense Circuit.


ERROR AMPL. IS COMP R RS C CURRENT SENSE 5 GND 1

2R R 1V

D95IN347

Peak current (is) is determined by the formula

A small RC filter may be required to suppress switch transients. Figure 20. Slope Compensation Techniques.

o s Ob

let
R1

o r P e
RT CT

c u d
8 4

) s t(

1.0V I Smax -----------RS

o s b O -

e t le

o r P

CURRENT SENSE COMPARATOR

c u d

) s t(

VREG

VREG RT IS RSLOPE RT/CT CT ISENSE

IS RSLOPE

RT/CT

ISENSE

3 5 GND RS

R1

3 5 GND
D95IN348

RS

8/16

UC384XA - UC284XA
Figure 21. Isolated MOSFET Drive and Current Transformer Sensing.
VCC Vin

5.0Vref

+ -

ISOLATION BOUNDARY VGS Waveforms

+ S R + COMP/LATCH

Q1

+ 0 -

50% DC

+ 0 -

25% DC

Ipk =

V(pin 1) -1.4 3RS

(N ) N
S P

3 C
D95IN349

R RS NS NP

Figure 22. Latched Shutdown.

OSC

t e l o s Ob

r P e

od

t c u

) s (
2 1 2N 3903

o s b O R BIAS R + 1mA + EA

e t le
2R R

o r P

c u d

) s t(

2N 3905

D95IN350

SCR must be selected for a holding current of less than 0.5mA at TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.

9/16

UC384XA - UC284XA
Figure 23. Error Amplifier Compensation
+ 1mA Ri 2 Rd Cf Rf 1 5 + EA 2R

From VO

2.5V

Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current.
+ 1mA RP Ri 2 CP Rd Cf Rf 1 5
D95IN351

From VO

2.5V

+ EA

2R

Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current.

Figure 24. External Clock Synchronization.

VREF

t e l o s Ob

EXTERNAL SYNC INPUT

o r P e

du

ct

RT

) s (

o s b O 8 4 + +

e t le
R R

o r P

c u d

) s t(

BIAS

OSC

CT

0.01F 47 2 1

2R EA

5
D95IN352

The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300mV below ground

10/16

UC384XA - UC284XA
Figure 25. External Duty Cycle Clamp and Multi Unit Synchronization.
VREF RA 8 4 8 R BIAS R 3 4 + Q + 5K 1 7 + EA 2R

RB 6 5

5K

+ 5K

OSC

2 C

NE555

f=

1.44 (RA + 2RB)C

Dmax =

RB RA + 2RB

TO ADDITIONAL UCX84XAs

Figure 26. Soft-Start Circuit

t e l o s Ob
C

d o r P e
4 2 1

uc
-

) s t(
R R +

o s b O BIAS OSC

e t le
5Vref

o r P

c u d

) s t(
5

D95IN353

+ -

1mA 2R + EA R 1V -

S Q R

1M

5
D95IN354

11/16

UC384XA - UC284XA
Figure 27. Soft-Start and Error Amplifier Output Duty Cycle Clamp.
VCC Vin

7 + -

8 R BIAS R 4 + 1mA 2 R2 + EA 2R R 1V

5Vref + -

OSC

Q1

VClamp +

S Q R Comp/Latch 5

1 5

R1

BC109 VCLAMP = R1 R1 + R 2 where 0 <VCLAMP <1V Ipk(max) = VCLAMP RS

t e l o s Ob

o r P e

c u d

) s t(

o s b O -

P e t e l

ro

c u d
D95IN355

RS

) s t(

12/16

UC384XA - UC284XA
Figure 28. SO-8 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 B C D (1) E e H h L k ddd 5.80 0.25 0.40 1.35 0.10 1.10 0.33 0.19 4.80 3.80 1.27 6.20 0.50 1.27 0.228 0.010 0.016 TYP. MAX. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 MIN. 0.053 0.004 0.043 0.013 0.007 0.189 0.15 0.050 0.244 0.020 0.050 TYP. MAX. 0.069 0.010 0.065 0.020 0.010 0.197 0.157 inch

OUTLINE AND MECHANICAL DATA

0 (min.), 8 (max.) 0.10 0.004

Note: (1) Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side).

t e l o s Ob

o r P e

c u d

) s t(

o s b O -

SO-8 e t le

o r P

c u d

) s t(

0016023 C

13/16

UC384XA - UC284XA
Figure 29. DIP-8 Mechanical Data & Package Dimensions
mm DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 0.100 0.300 0.300 0.260 0.200 0.150 0.060 TYP. 3.32 0.020 0.045 0.014 0.008 0.065 0.022 0.012 0.430 0.384 MAX. MIN. TYP. 0.131 MAX. inch

OUTLINE AND MECHANICAL DATA

t e l o s Ob

o r P e

c u d

) s t(

o s b O -

DIP-8 e t le

o r P

c u d

) s t(

14/16

UC384XA - UC284XA
Table 6. Revision History
Date March 1999 May 2004 Revision 4 5 First Issue in EDOCS NOT FOR NEW DESIGN Description of Changes

t e l o s Ob

o r P e

c u d

) s t(

o s b O -

e t le

o r P

c u d

) s t(

15/16

UC384XA - UC284XA

t e l o s Ob

o r P e

c u d

) s t(

o s b O -

e t le

o r P

c u d

) s t(

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com

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