ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : NIT Hamirpur Himachal Pradesh B.

Coordinator :Dr. (Mrs.) Rajeevan Chandel C. Co-coordinator : Dr. Lalit K. Awasthi Activities 1. India Chip Programme Design Tape out Action Adder Designs Submitted to DIT for Integration Modules for Operational Amplifier Design Testing Type-I = 03 Type-II = 16 Type-III =43 Type-IV = 153 Type-I = 02 Type-II = 14 Type-III =32 Type-IV = 178 Draft report Shall be prepared timely IEPs floated by RCs shall be attended & Paper presentation Timeline 31st Mar. 2012

Design to be undertaken/Integrated

July 2012

Testing of Fabricated Chips 2. Estimated Manpower Generation in current academic year at various levels (Type-I,II,III,IV) (Both RCs & PIs) (Indicated nos. shall pass out)

Dec 2012 May 2012

2013

3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others

Jan. 2013

June-July & Dec 2012

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : National Institute of Technology Calicut B. Coordinator :Dr.Elizabeth Elias C. Co-coordinator :B.Bhuvan Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Action Two operational amplifier circuits were taped out Our first PCB board failed. We made a new board. From our initial testing, we found the circuit working. Timeline

--

Testing of Fabricated Chips

By the end of May 2012

2. Estimated Manpower Generation in current Type-I = 0 Type-II = 19 academic year at various levels (TypeType-III = 20 I,II,III,IV) (Both RCs & PIs) Type-IV = 60 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others Draft report To conduct a workshop on VLSI in

By August 2013

Feb. 2013 December 2012

ANNUAL ACTION PLAN for FY 2012-13 RESOURCE CENTRES A. Name of the Institute: Indian Institute of Science, Bangalore B. Coordinator: Prof HS Jamadagni C. Co-coordinator: Prof Amruthur Bharadwaj Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action Already completed many Many have been fabricated. At least one more multi-design ready for fabrication Timeline 31st Mar. 2012 Sept 2012

2. IEP IEP to be conducted, giving topic,duration and schedule dates

Dec 2012 Nothing has been requested. However a course on packaging by a new faculty member is most likely to be offered Name of Expert Many visitors When visiting Almost one every month till March 2013

3. International Guest Faculty Workshop IGF workshop to be conducted, giving topic, Expert name and schedule dates

4. Upload Instruction Enhancement Programe/International Guest Faculty workshop proceeding/ppt on RCs website 5. Estimated Manpower Generation in current academic year at various levels (TypeI,II,III,IV)

As and when they happen

Continuously till March 2013 By August 2013

Type-I = 10 Type-II = 40 Type-III = 100 Type-IV = NA

6. PI Visits for review and monitoring

Two visits each July 2012 till mar 2013 and Jan 2013 Draft report Feb. 2013

7. Preparation of closure report and draft submission

ANNUAL ACTION PLAN for FY 2012-13 RESOURCE CENTERS A. Name of the Institute :INDIAN INSTITUTE OF TECHNOLOGY DELHI B. Coordinator : Prof. G. S. VISWESWARAN C. Co-coordinator : Prof. BASABI BHAUMIK Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Action Timeline

Testing of Fabricated Chips

Energy June 2012 scavenger, MB power amp. HS Serial Link, October 2012 13 Gbps First December 2012 Second March 2013.

2. IEP IEP to be conducted, giving topic,duration and schedule dates 3. International Guest Faculty Workshop IGF workshop to be conducted, giving topic, Expert name and schedule dates 4. Upload Instruction Enhancement Programe/International Guest Faculty workshop proceeding/ppt on RCs website 5. Estimated Manpower Generation in current academic year at various levels (Type-I,II,III,IV)

Topics/duration Dates
None Due / None requested

Name of Expert

When visiting

Details
PPT on the last two IEPs hels at IIT Delhi

Dates
April 15, 2012

Type-I = 3 By August Type-II = 40 2013 Type-III = 120 Type-IV = 120 Number of visits: at least 1
each

6. PI Visits for review and monitoring

Dates: June July 2012

7. Preparation of closure report and draft submission

Draft report

Feb. 2013

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute :Indian Institute of Technology Guwahati B. Coordinator : Prof. S. Dandapat C. Co-coordinator : Dr. Roy Paily Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action No new design The second board design for the chip India Chip Analog 3 is ongoing and IITG will update the test result Timeline 31st Mar. 2012 New PCB fabrication by May- June 2012

Test results by October 2012 By August 2013

2. Estimated Manpower Generation in current Type-I = 1 Type-II = 9 academic year at various levels (TypeType-III = 25 I,II,III,IV) (Both RCs & PIs) Type-IV = 90 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others
Important Note

Draft report

Feb. 2013

Presently we are running on negative balance about 2 Lakhs total on heads like Equipment, EDA training, travel and consumables. We have not exceeded on the initially sanctioned targets but as the actual allocation to IIT Guwahati for the subsequent years were reduced, this has happened. We have some balance on contingency about 0.5 lakhs. I request you to consider, an amount of Rs. 1.5 lakhs also in the next allocation additional to the head salaries. I will be submitting the detailed report and UC for the same soon as possible.

ANNUAL ACTION PLAN for FY 2012-13 RESOURCE CENTERS A. Name of the Institute : I.I.T. Kanpur B. Coordinator : Prof. S. Qureshi C. Co-coordinator : Dr. Bahniman Ghosh Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action Details PCB for the India Chip to be tested has been fabricated Timeline 31st Mar. 2012 Date 3oth June 2012

2. IEP IEP to be conducted, giving topic,duration and schedule dates

Topics/duration Dates Low Power April 30, Digital design/ 2012 4 days

3. International Guest Faculty Workshop IGF workshop to be conducted, giving topic, Expert name and schedule dates 4. Upload Instruction Enhancement Programe/International Guest Faculty workshop proceeding/ppt on RCs website 5. Estimated Manpower Generation in current academic year at various levels (Type-I,II,III,IV)

Name of Expert

When visiting

Details Low Power Digital Design Type-I =2 Type-II =40 Type-III =150 Type-IV =240 Number of visits One (joint)

Dates May 31st, 2012 By August 2013

6. PI Visits for review and monitoring

Dates To be scheduled

7. Preparation of closure report and draft submission

Draft 31st December, 2012

Feb. 2013

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : Dept. of Electronics Engg., IT-BHU, Varanasi B. Coordinator :Prof. S. K. Balasubramanian C. Co-coordinator :Prof. Anand Mohan Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Action One chip is already fabricated and no new tape out is in the present plan. N/A Timeline 31st Mar. 2012

Testing of Fabricated Chips

Date By August 2013

2. Estimated Manpower Generation in current Type-I = 02* Type-II = 12* academic year at various levels (TypeType-III = 20* I,II,III,IV) (Both RCs & PIs) Type-IV = 85* 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others Draft report to be submitted at the time line. In the extended one year of the project, the course curriculum (Lab/Project) based on the SMDP facilities would continue. Further, we plan to develop a Piezoresistive pressure sensor.

Feb. 2013

* These figures are based on the data available for the current year. The exact figures will be provided in August 2013.

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : Jadavpur University B. Coordinator : Prof. Chandan Kumar Sarkar C. Co-coordinator :Mr. Sayan Chatterjee Activities 1. India ChipProgramme Design Tape out / Integrated Action
1. Chopper Stabilized Amplifier 2. Neuron & 7-3 Compressor 3. Sense Amplifier

Timeline
1. August , 2008

2. November , 2009 3. July , 2010 1. August , 2011

Testing of Fabricated Chips

1. Chopper Stabilized Amplifier 2. Neuron & 7-3 Compressor 3. Sense Amplifier

2. August , 2011

3. August , 2011 31st Mar. 2013

Design to be undertaken

Design of Low Power Data Converters

2. Estimated Manpower Generation in current Type-I = 0 By August Type-II = 18 2013 academic year at various levels (TypeType-III = 9 I,II,III,IV) (Both RCs & PIs) Type-IV = 120 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others Draft report Feb. 2013

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute :DR.B.R Ambedkar, National Institute of Technology, Jalandhar B. Coordinator :Dr.R.K.Sarin C. Co-coordinator :ER.Mamta Khosla Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action Annexure-1* Annexure-1* Timeline 31st Mar. 2012 31st Oct. By August 2013

2. Estimated Manpower Generation in current Type-I =01 Type-II =06 academic year at various levels (TypeType-III =20 I,II,III,IV) (Both RCs & PIs) Type-IV =97 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others Draft report Annexure-2*

Feb. 2013

*see Annexure-1 and Annexure-2 attached with this mail in word format.

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute :National Institute of Technology Silchar, Assam B. Coordinator : Santosh Kumar Gupta C. Co-coordinator : Brinda Bhowmick (Shome) Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action 4-bit Hamming code generator for communication systems Details Timeline 31st Mar. 2012 30th September, 2012 By August 2013

2. Estimated Manpower Generation in current academic year at various levels (TypeI,II,III,IV) (Both RCs & PIs) 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others

Type-I =02 Type-II =12 Type-III = Type-IV =210 Draft report

Feb. 2013 31st March, 2013

Summer/Winter Training Program for nearby colleges

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : National Institute of Technology, Rourkela B. Coordinator : Prof. K.K. mahapatra C. Co-coordinator : Prof B.D.Sahoo Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Action Controller Area network Chip along with BESU and IIT KGP NA* Timeline 31st Mar. 2012

Testing of Fabricated Chips

Date

2. Estimated Manpower Generation in current Type-I =2 By August Type-II =22 2013 academic year at various levels (TypeType-III =66 I,II,III,IV) (Both RCs & PIs) Type-IV =150 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others Draft report will be prepared Feb. 2013

* We would like to take up fabrication of another chip (A 8 bit adder using feedthrough logic if permitted by DIT. We have just completed design)

A. B. C.

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES Name of the Institute : Bengal Engineering and Science University, Shibpur Coordinator :Dr.Hafizur Rahaman Co-coordinator :Dr. Biplab K Sikdar Activities India Chip Programme Design Tape out / Design to be undertaken/Integrated Action Details Tape out Date :15th April 2012, (Integration of Combined Chip of IIT-KGP,BESUS, NIT-R) Details Testing of Individual circuit will be done by Corresponding PI/RC.
Timeline 31st Mar. 2012

1.

Testing of Fabricated Chips

Date After getting chip, testing will be done within 3 months

2.

Estimated Manpower Generation in current academic year at various levels (Type-I,II,III,IV) (Both RCs & PIs)

Type-I = 4 Type-II = 18 Type-III = 72 Type-IV = 160 Draft report Will be submitted in the specified time

By August 2013

3.

Preparation of closure report and draft submission (Both RCs & PIs) Others

Feb. 2013

4.

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : Maulana Azad National Institute of Technology Bhopal B. Coordinator : Dr. R. P. Singh C. Co-coordinator : Dr. Arvind Rajawat Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Action Circuit for Genetic Algorithm Implementation, RoundRobinarbiter and NeuronCircuit are among some circuits being worked upon To be undertaken after designs are complete Type-I = 03 Type-II = 20 Type-III = 02 Type-IV = 10 Draft report to be submitter later Permission has been sought to utilize unspent balance from SMDP II in the financial year 2012-2013 Timeline 31st Mar. 2012

Testing of Fabricated Chips

2. Estimated Manpower Generation in current academic year at various levels (TypeI,II,III,IV) (Both RCs & PIs)

By August 2013

3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others

Feb. 2013

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute :S.V .National Institute of Technology (SVNIT),Surat-7 B. Coordinator :A.D.Darji C. Co-coordinator :Z.M.Patel Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action NIL Timeline

31st Mar. 2012 Under Testing 30th APR 2012

2. Estimated Manpower Generation in current Type-I =NIL By August Type-II =25 2013 academic year at various levels (TypeType-III = 25 I,II,III,IV) (Both RCs & PIs) Type-IV =211 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others Draft report 4 Int. Conf. Publications 2 Int. Journal Publications New M.Tech course (VLSI & Embedded System) is started from July 2012 with 25 students One workshop will be organized Feb. 2013 By August 2013

July 2012

By August 2013

Note: We will try for one more tape out after submission of test report of our first chip by March 31,2013

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : Thapar University, Patiala B. Coordinator : Dr. Alpana Agarwal C. Co-coordinator : Dr. Seema Bawa Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action Timeline

Components of ADC July 2012 comparators / reference circuits Testing of Low December Power opamp and 2012 synthesized Differential Amplifiers Type-I = 0 Type-II = ~30 Type-III = ~30 Type-IV = ~120 Draft report By August 2013

2. Estimated Manpower Generation in current academic year at various levels (Type-I,II,III,IV) (Both RCs & PIs)

3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others

Feb. 2013 -

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : Malaviya National Institute of Technology Jaipur B. Coordinator :Dr. Vineet Sahula C. Co-coordinator : Dr. D. Boolchandani Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Action Low power DCT, Hamming codec June 2012 Timeline 31st Mar. 2012 (GDS-II submitted to DIT, Feb 2012) June 2012

Testing of Fabricated Chips

2. Estimated Manpower Generation in current Type-I =02 By August 2013 Type-II =31 academic year at various levels (TypeType-III =62 I,II,III,IV) (Both RCs & PIs) Type-IV =144 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others Draft report Feb. 2013

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute :National Institute of Technology Warangal B. Coordinator :Prof KSR Krishnaprasad C. Co-coordinator : Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action Details enclosed Under pipe line Timeline 31st Mar. 2012 September 2012

2. Estimated Manpower Generation in current Type-I =2 By August Type-II =20 2013 academic year at various levels (TypeType-III =43 I,II,III,IV) (Both RCs & PIs) Type-IV =267 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others Draft report Feb. 2013

India chip program--- Chip Design (Details of the chip fabricated using SMDP Fund) 1. 2. Name of Chip Design Number of students involved in project Technical Specification including I/O PIN detail/packages/complexities/ power consumption etc.) Technology used Name of the Design Integrating Institution Brief Description of functionality Power management IC 01

3.

Details enclosed

4. 5.

180nm NITW/NITT

6.

Gives power to mixed signal systems

7.

Name of the foundry where chip has been fabricated

UMC

8.

Cost in fabrication Cost in testing the design Total Cost in Chip design

Met by DIT under common pool 50000

9. 10. 11 12.

Silicon area Scanned picture of Chip/Die Date of Tapeout: 2011 Test Report:

500umx500um for PMIC included

will be given in due course

Layout of the chip

Pinoutdetailso

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute :PSG College of Technology B. Coordinator :Dr.P.Kalpana C. Co-coordinator :Mrs.K.Rajalakshmi Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action Participated Test results Timeline Dec 2012 JUNE

2. Estimated Manpower Generation in current Type-I =4 By 2013 academic year at various levels (Type- Type-II =18 Type-III =54 I,II,III,IV) (Both RCs & PIs) Type-IV =260

3. Preparation of closure report and draft Draft report Feb. 2013 submission (Both RCs & PIs) 4. Others Extention of March 2014 licenses for EDA tools

ANNUAL ACTION PLAN for FY 2012-13 RESOURCE CENTERS A. Name of the Institute : Indian Institute of Technology Bombay, Mumbai B. Coordinator : A.N.Chandorkar C. Co-coordinator : Supratik Chakraborti Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated ***** Total cost for three chips will be around is Rs. 24 Lakhs Action (1)Novel current-mode signaling on-chip interconnect schemes and BIST Technology: 90nm CMOS technology (2)FractionalNPLL (0.18u) (3)WimaxMixer(0.18u) Testing of Fabricated Chips (1)Third current-mode signaling test chip (2)Low-power analog and mixed-signal test chip Timeline (1)October 2012 as per run schedule available from Europractice

(2&3)Design ready but layout etc is still underway. Submissionby October2012 (1) Already started. (2)Start date: May 2012.

(3)NovelSample&Hold (3)StartBy31st Circuit(0.18um) August2012

2. IEP IEP on VLSI Testing Coordinated by Prof. Virendra Singh, IITB

3-4days

Available dates: 8th to 13th July, 2012 When visiting will be in consultation

3. International Guest Faculty Workshop

Will host and conduct

IGF workshop to be conducted, giving topic, Expert name and schedule dates 4. Upload Instruction Enhancement Programe/International Guest Faculty workshop proceeding/ppt on RCs website

Workshop with Visitors called by other RCs NOT Planned

with other RCs

Details: Our Earlier IEPs video and PPTs are already are available on SMDP site (A) Type-I = 10 Type-II = 22(Micro)+10 others Type-III = 20(Micro)+ 20 others Type-IV = 20 (B) Type I: 17 Type II : 43 Type III : 100 Type IV: 120

Not needed

5. Estimated Manpower Generation in current academic year at various levels (Type-I: Ph.D. ; Type-II:Dual Degree; Type-III: M.Tech. ; Type IV: B.Tech.) (A) These students are doing Projects related to VLSI

By August 2013

(B) Students getting exposed to VLSI Courses:

6. PI Visits for review and monitoring

Number of visits will be 3: one each to NIT Surat, VNIT Nagpur and One at SGSITS in next 5 Months

Dates will be Finalized as per PIs request

7. Preparation of closure report and draft submission

Draft report

Feb. 2013

*****ForFabricationandTestofProposedTHREEChips,we mayrequireRs24lakhs(totalmoneyasperquotations availablewithus).Thisincludespackagingcostandother consumablesforBoarddesignandfab.

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : Visvesvaraya National Institute of Technology B. Coordinator : R. B. Deshmukh C. Co-coordinator : Prof. R.M. Patrikar Activities 1. India Chip Programme Design Tape out / Design to be undertaken/Integrated Action Proposal for Zigbee Transreceiver already submitted In house testing of the transreveiver Timeline 30the Sept. 2012

Testing of Fabricated Chips

Feb. 2013

2. Estimated Manpower Generation in current Type-I = 01 Type-II = 21 academic year at various levels (TypeType-III = I,II,III,IV) (Both RCs & PIs) Type-IV=105 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others Draft report

By May 2013

Feb. 2013

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES

A. B. C.

Name of the Institute : National Institute Of Technology, Jamshedpur Jharkhand Coordinator : Dr S.N.Singh Co-coordinator : Dr A.Choubey

Activities 1. India ChipProgramme

Design Tape out / Design to be undertaken/Integrated

Action

Time line

st The initiative will be taken to 31 Mar. design an optimal Low power 2012 CMOS devices for combinational digital circuits in collaboration with RC and other Institutes under SMDP-II M.Tech Students/Faculty/ Research scholars will be involved in the above programme

Testing of Fabricated Chips 2. Estimated Manpower Generation in current academic year at various levels (Type-I,II,III,IV) (Both RCs & PIs) Preparation of closure report and draft submission (Both RCs & PIs) Others

Testing of fabricated chips within 6 Date months time Dec 2012 By August Type- I =1 2013 Type- II = 12 Type- III = 16 Type - IV = 300 (approx) Draft report Feb. 2013 M.Tech Thesis / Research Project will be submitted . Papers in International and Jan 2013 National Journals will be published by Faculty/Research scholars of the Institute utilizing resources of VLSI lab. Interactive programmes with Industry and Technical Institutes will be organized. M.Tech course in Communication System will be started in which VLSI subjects have been included July 2013 (Type III)

3.

4.

Date Place : Jamshedpur

Coordinator / Co-coordinator SMDP Project-II National Institute of Technology, Jamshedpur

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute :National Institute of Technology Hazratbal Srinagar 190 006 B. Coordinator :Prof G. M. Rather C. Co-coordinator :Dr. Najeeb-ud-din Activities 1. India Chip Programme Design Tape out / Design to be undertaken/Integrated Action Details: We may not be able to submit the design by 31st March 2012. However if we are given some more time we will be able to submit the design. Details: dates may get modified accordingly Timeline 31st Mar. 2012

Testing of Fabricated Chips

Date

2. Estimated Manpower Generation in current Type-I = X Type-II = None academic year at various levels (TypeI,II,III,IV) (Both RCs & PIs) Type-III = 19 Type-IV = 110 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others

By August 2013

Draft report will Feb. 2013 be submitted We will conduct May-June a workshop on 2012 Microelectronics

(G.M. Rather) Coordinator SMDP II

(Najeeb-ud-din) Co-Coordinator SMDP II

A . B . C .

ANNUAL ACTION PLAN for FY 2012-13 RESOURCE CENTERS Name of the Institute : Indian Institute of Technology Kharagpur Coordinator : Prof. Swapna Banerjee, E&ECE Dept, IIT Kharagpur Co-coordinator :Prof. Chitta ranjan Mandal, CSE Dept. IIT Kharagpur Action Digital ADC Low Kickback Noise Latched Comparator Secure arithmetic hardware Timeline Will be fabricated soon

Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated

To be fabricated

Testing of Fabricated Chips 2. IEP IEP to be conducted, giving topic,duration and schedule dates 3. International Guest Faculty Workshop IGF workshop to be conducted, giving topic, Expert name and schedule dates

10-Bit, 500M Already Sample/S fabricated Track and Hold Amplifier Designed at IIT Kharagpur Done Already sent to DIT Topics/duratio n Name of Expert N/A Dates When visiting N/A

4. Upload Instruction Enhancement Programe/International Guest Faculty workshop proceeding/ppt on RCs website

Lecture Dates Materials and Video lecture February of IEP on 2012 VLSI Application on Biomedical Engineering have been uploaded in the IIT Kharagpurs SMDP website. Type-I = 25 Type-II = 38 Type-III = 58 Type-IV = 120 IIT Kharagpur has regular interaction with PIs at Silchar, Rourkela and Jadavpur. Closure Report: is under preparation Proposed draft submission: has already been done and submitted to DIT. By August 2013

5. Estimated Manpower Generation in current academic year at various levels (Type-I,II,III,IV) 6. PI Visits for review and monitoring

Silchar and jadavpur visited IIT KGP during the IEP-2011

7. Preparation of closure report and draft submission

Will be submitted by Feb. 2013 Has been submitted in February 2012

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : Shri G. S. Institute of Technology and Science, Indore B. Coordinator :Dr. D. K. Mishra , Dean(R&D) , Professor and Head(E&I Dept) C. Co-coordinator :Prof. P. K. Jain Activities 1. India Chip Programme Design Tape out : Action Timeline

A two Stage CMOS Op-Amp 31st Mar. was taped-out in 2010-11. 2012

Design to be undertaken/Integrated: A 3.1-10.6GHz Inductive degenerated Common-Source Low noise Amplifier is ready for tape out(DRC,LVS, RCX completed) Testing of Fabricated Chips A two stage CMOS Op-Amp Completed was fabricated and its testing report is already submitted 2. Estimated Manpower Generation in current academic year at various levels (TypeI,II,III,IV) (Both RCs & PIs) Type-I =02+(08 registered) Type-II =24+(25 expected) Type-III =25+(25 expected) Type-IV =150+(150 expected) By August 2013

3. Preparation of closure report Preparation of closure report Feb. 2013 and draft submission (Both RCs & and draft submission is under progress and will be PIs) completed before time line. 4. Others A) We will be shortly submitting two designs proposals for approval to SAC, ISRO: 1. Design and testing of A/D converter 2. Trans-receiver for Ultra wideband application B) We have applied for

Accreditation of M. Tech. (Microelectronics& VLSI Design) course to NBA.

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : National Institute of Technology Karnataka, Surathkal. B. Coordinator : Ramesh Kini. M. C. Co-coordinator : Dr. M S Bhat. Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action -NIL-NILTimeline 31st Mar. 2012 Date By August 2013

2. Estimated Manpower Generation in current Type-I = 2 (expected) academic year at various levels (TypeType-II = I,II,III,IV) (Both RCs & PIs) 28+2(MTech by Reasearch) Type-III = 0 Type-IV = 107 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others Draft report (Possible) Proposing Chip tape out during FY 2012-13. Please refer to the attached sheet

Feb. 2013 Uploading of GDSII by Sep. 2012. Europractice mini@sic run October 15, 2012. Test report by March 2013.

Department of E & C, NITK, Surathkal proposes to tape out a chip of size 2 slices of 1.5mm X 1.5mm with UMC 180nm technology. The proposed chip designs are from two Research scholars and will help in validating their designs. Schematic designs are ready and the students are about to start layout. Implementation would be possible with the extension of EDA tool licenses, and allocation and release of grant for fabrication. Details are given in the attached sheets. We request you to kindly permit us to go ahead with proposal and grant us the necessary resources. Thanking you, Yours sincerely, (Ramesh Kini.M.)

PROPOSAL FOR CHIP DESIGN FROM NITK

NITK proposes one chip of size 1.5 mm x 3 mm from UMC 180 nm CMOS process. The chip will help two Ph.D. Scholars, currently pursuing their research at NITK, to validate their research ideas. A brief details of the two designs is as follows.

1. Design 1 : 0.5 V, 5th order Chebyshev low-pass Active-RC filter Specifications 3-dB bandwidth Technology : 500 kHz : 0.18m n-well standard CMOS Technology

Total Power dissipation : 236 W Area required : 1mm x 1mm

2. Design 2: 0.5 V 4th order Butterworth low-pass Gm-C filter Specifications 3-dB bandwidth Technology : 1 MHz : 0.18 m n-well standard CMOS Technology

Total Power dissipation : 32 Watts Area required : 0.6 mm x 1 mm

Current Status: Both the above designs are in the final stage of schematic design, performing final testing of the design in schematic level.

Expected time-line for design completion:

The chip will be ready for tape-out in September 2012.

The floor plan for the chip design: A proposed floor plan of the chip is show below. This plan will have an efficient area utilization and there by value for the money.

Package type: The active area in used by the design: Total area of the chip:

64 pin Dual-in-Line 1 mm x 3 mm = 3 mm2 4.5 mm2

The remaining area can be used for the other designs. We, at NITK, have 2 more schematic designs in pipeline which can be added to the same chip. These are designs from the M.Tech. (by Research) program viz.

1. Design 3: 3.3 V to 1.8 V step down DC/DC converter in 0.18m CMOS Technology with 94 % peak efficiency. 2. Design 4 : A 0.5 V, 300 W, 50 MS/s, 6 bit flash ADC using inverter based comparators in 0.18 m CMOS Technology Expected expenditure: The fabrication and packaging costs are expected to be in the range of Rs. 4.5 Lakhs for 20 samples of the chip. The estimation is based on the details given in the Europractice web site and the prevailing currency exchange rates of Euro and US Dollar.

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute :Motilal Nehru National Institute of Technology-Allahabad B. Coordinator : Professor Rajeev Tripathi C. Co-coordinator :Mr. Sanjeev Rai Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action Details Details Timeline 31st Mar. 2012 Date By August 2013

2. Estimated Manpower Generation in current Type-I = 6 Type-II = 45 academic year at various levels (TypeType-III = 42 I,II,III,IV) (Both RCs & PIs) Type-IV = 238 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others Report to be submitted shortly.

Feb. 2013

ANNUAL ACTION PLAN for FY 2012-13 RESOURCE CENTERS A. Name of the Institute :Indian Institute of Technology Madras B. Coordinator :Vinita Vasudevan C. Co-coordinator :Nagendra Krishnapura
1. Activities India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action N/A N/A Timeline 31st Mar. 2012 N/A

2.

IEP IEP to be conducted, giving topic,duration and schedule Topics/duration dates International Guest Faculty Workshop IGF workshop to be conducted, giving topic, Expert name and schedule dates (This is tentative-approaches are being made to these experts for possible visit in late 2012. These have not yet been confirmed.) Name of Expert Prof. Staszewski (TU Delft) Dr. Sotiriadis (Sotecko Inc) Prof. Makinwa (TU Delft) Details Prof. Klumperinks lecture material Type-I =1 Type-II =35 Type-III =70 Type-IV =90 Number of visits N/A Draft report

Dates

3.

When visiting Tentatively planned for Nov.-Dec. 2012

4.

Upload Instruction Enhancement Programe/International Guest Faculty workshop proceeding/ppt on RCs website

Dates 31st March 2012

5.

Estimated Manpower Generation in current academic year at various levels (Type-I,II,III,IV)

By August 2013

6.

PI Visits for review and monitoring

Dates N/A Feb. 2013

7.

Preparation of closure report and draft submission

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute : Indian Institute of Technology, Roorkee B. Coordinator : Dr. S. N. Sinha C. Co-coordinator : Dr. S. Dasgupta Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action Details(see attachment) Details Timeline 31st Mar. 2012 Date By August 2013

2. Estimated Manpower Generation in current Type-I =03 Type-II =15 academic year at various levels (TypeType-III =15 I,II,III,IV) (Both RCs & PIs) Type-IV =85 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others UC & audited Statement submitted.

Feb. 2013

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute :National Institute Of Technology Durgapur B. Coordinator :Dr. Gautam Kumar Mahanti C. Co-coordinator : Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action Mentioned Below Mentioned Below * Timeline 31st Mar. 2012 31st Mar. 2012 / Earlier

2. Estimated Manpower Generation in current Type-I = 01 By August Type-II = 21 2012 academic year (2011-12) at various levels Type-III = 00 (Type-I,II,III,IV) (Both RCs & PIs) Type-IV =221 3. Preparation of closure report and draft submission (Both RCs & PIs) 4. Others: a) Wish to conduct Short-termCourse in June-July 2012 b) Fourth Tape-out in 4th Qtr(Oct.-Dec. 2012) Draft report
Short-Term Course on Analog VLSI Design

Feb. 2013 June-July 2012

Tape-out by Dec. 2012

Design ready by Mrach 30, 2012 for tape out from NIT DURGAPUR
A programmable switched capacitor filters with below mentioned features: A programmable switched capacitor forth order filter with digital control to select low pass or band pass response from the same biquad. A control bit selects whether the filter behaves as a low pass filter or a band pass filter. The cutoff frequency/centre frequency is tunable by changing the clock input.

Power and area efficient ring oscillator and NOC generator. Low power high speed class AB buffer with single path push pull operation for the output stage.

Pins required: 10 pins including supply.

Testing Plan
Test plan circuit attached Chips fabricated earlier under IndiaChip are tested successfully. PCB images attached. 6 to 8 weeks from the date of receiving the chip. The test circuit planned for this chip is shown below. The PCB will be made once the pin diagram is made available.

First two chips have already been tested and their reports have already been submitted to DIT. Testing photographs of the first two chips designed jointly with IIT KGP, BESU and Jadavpur University.

Testing chips fabricated under Indiachip program in 2011.

A. B. C. 1.

ANNUAL ACTION PLAN for FY 2012-2013 CSIR-CEERI, PILANI Name of the Institute : CSIR-CEERI, Pilani Coordinator : Sh. Raj Singh, Chief Scientist Co-coordinator : Dr. S. C. Bose, Senior Principal Scientist Activities Action India Chip Programme Design Tape out / Design to be Completing the integration for multiundertaken / Integration project chip and tape-out of the designs of 10-bit ADC (CEERIPilani); Modified electronic lock (DEIT/MCIT); DCT/IDCT, 7-bit Hamming Codec, 8-FFT, and CORDIC hardware (MNIT-Jaipur); Differential Amplifier (BRANITJalandhar); 1-bit Adder (MNNITAllahabad); 16-bit and 32-bit Adder (NIT-Hamirpur); Full Adder (NITKurukshetra); 16-bit ADC (IITRoorkee) Testing of Fabricated Chips Each of the above institute will do the testing of their fabricated designs.

Timeline April 16, 2012

October 16, 2012

2.

IEP IEP to be conducted, giving topic, duration and schedule dates

Topics/duration ---

Dates ---

3.

International Guest Faculty Workshop Name of Expert IGF workshop to be conducted, giving topic, Expert name and schedule dates ---

When visiting ---

4.

--Upload Instruction Enhancement Programe/International Guest Faculty workshop proceeding/ppt on RCs website Estimated Manpower Generation in current academic year at various levels (Type-I, II, III, IV) Type-I = 2 Type-II = 3 + 2 Type-III = 5 + 4

---

5.

August, 2013

Type-IV = NIL 6. PI Visits for review and monitoring One visit per PI. As there are 3 PIs with CEERI, therefore, total of 3 visits during 20122013. March, 2012

7.

Preparation of closure report and draft submission

Project completion February, 2013 report preparation. Draft report submission to DEIT/MCIT.

8.

9.

Centralized procurement of Hardware and EDA Tools EDA Tools licenses renewal EDA tools licenses to be April-October, renewed for Synopsys, 2012 Cadence, Mentor and Xilinx. Hardware maintenance No centralized task is envisaged for this. Website for SMDP-II March, 2013 Others : Website at RC project at CEERI will be updated and maintained.

ANNUAL ACTION PLAN for FY 2012-13 PARTICIPATING INSTITUTES A. Name of the Institute :NIT, Trichy B. Coordinator :B.Venkataramani C. Co-coordinator :G.Lakshminarayanan Activities 1. India ChipProgramme Design Tape out / Design to be undertaken/Integrated Testing of Fabricated Chips Action A number of Designs need to be fabricated* Fabricating the PCBs Timeline Dec 2012 2012 March 2013

2. Estimated Manpower Generation in current Type-I =2 By August Type-II =25 2013 academic year at various levels (TypeType-III =25 I,II,III,IV) (Both RCs & PIs) Type-IV =170 3. Preparation of closure report and draft submission (Both RCs & PIs) Others: 4.
1. Design and fabrication of RF front end for Cognitive Radio 2. Design and fabrication of digital backend for Cognitive Radio 3. Testing of ICs * - Designs need to be fabricated 10-bit 100MSPS Pipelined ADC with a modified Telescopic Cascode OTA Continuous-time Second Order Sigma Delta Modulator ADC with a modified OTA Modified Recyclic Folded Cascode OTA with high gain and bandwidth Design of RF front end modules for Zigbee Receiver Design & testing on-chip Serial Interconnect drivers using wavepipelined surfing Transceivers with Quasi-resonant serial interconnects with active inductor A Carry Look Ahead Adder using Pseudo 4-Phase Dual-Rail Asynchronous Protocol Asynchronous Wave-Pipelined 8-tap DA FIR filter using Online Clock Skew Scheme Total

Draft report

Feb. 2013
Dec. 2012 Dec. 2012 Mar. 2013 Area in mm2 0.64 0.48 0.40 0.73 1.02 0.54 0.054

0.054 3.928