International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN 0976 6480(Print),

, ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME ENGINEERING AND TECHNOLOGY (IJARET)

ISSN 0976 - 6480 (Print) ISSN 0976 - 6499 (Online) Volume 4, Issue 3, April 2013, pp. 308-315 IAEME: www.iaeme.com/ijaret.asp Journal Impact Factor (2013): 5.8376 (Calculated by GISI) www.jifactor.com

IJARET
IAEME

DESIGN & IMPLEMENTATION OF 3-BIT FLASH ADC IN 0.18M CMOS

Md Noorullah Khan Assistant professor, ECED Muffakham Jah college of engineering and technology Hyderabad, A.P. Dr Kaleem Fatima Professor and Head ECED Muffakham Jah College of engineering and technology Hyderabad, A.P. Khaja Mujeebuddin Quadry Professor & Head Dept. of ECE Royal Institute of Technology and Science Chevella, R.R.Dist, A.P.

ABSTRACT This paper describes the design and implementation of a 3-bit flash Analog to Digital converter (ADC). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18um CMOS Technology. The simulation result of ADC is done in Cadence environment. Index Terms: CMOS, Comparator, Thermometer code, Flash ADC, cadence
I. INTRODUCTION

Applications such as wireless communications and digital audio and video have created need for cost-effective data converters that will achieve higher speed and resolution. The needs required by digital signal processors continually challenge analog designers to improve and develop new ADC and DAC architectures. There are many different types of arc-hitectures, each with unique characteristics and different limitations. Figure.1 shows the general block diagram of ADC.

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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME

Fig. 1.Block diagram for 3-bit Flash ADC Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert an analog signal to a digital signal. Flash ADCs are ideal for applications requiring very large bandwidth; however, they typically consume more power than other ADC architectures and are generally limited to 8-bits resolution.
II ADC ARCHITECTURE

III The 3-bit Flash ADC architecture is shown in Fig. 2. The entire ADC consists of three components: the resistive ladder, the comparators, and the binary encoder. Each comparator compares the voltage difference between its positive input from VIN and its negative input from the Resistive ladder and then generates a digital output. The binary encoder generates corresponding 3-bit binary codes based on the comparator outputs. As shown in figure 2.

Fig. 2.Simple 3-bit Flash ADC The encoder converts the thermometer code produced by the comparators to a binary code as shown in the truth table in table II. As seen from the figure, the comparators all operate in parallel. Thus, the conversion speed is limited only by the speed of the comparator or the sampler. For this reason, the flash ADC is capable of high speed.

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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME A) COMPARATOR CIRCUIT & DESIGN SPECIFICATIONS

Comparator A comparator is used to detect whether a signal is greater or smaller than zero, or to compare size of one signal to another. It is in fact the second most widely used electronic components after amplifiers. A simple op-amp amp can be used as a comparator but this approach is too slow for practical applications. The circuit that has been used as a comparator is a CMOS circuit, which consists of two stages. The first stage is a differential amplifier circuit and the second stage consists of a buffer formed by using two inverter circuits. The output of f the differential stage will neither rise exactly to vdd nor fall exactly to zero, hence this output is given to second stage consisting of two inverters which gives final output which will be either vdd or zero depending on whether the input voltage is greater greater or less than the reference voltage respectively.

Fig.3. Circuit Diagram of the Comparator

Fig 3 shows the comparator circuit where two matched input transistors whose sources are joined together and biased by a transistor which should always be maintained in saturation region. The MOS differential pair formed by the input transistors is loaded by a current mirror formed by two MOS transistors at the top. The input voltage is applied to the gate of the input transistor in the left leg of the circuit and reference voltage is applied at the gate of the input transistor in the right leg. If the input t voltage exceeds the reference voltage then the input transistor in the right leg goes into cutoff and the entire current from the source flows only into the left leg and thus the voltage at the output node will be nearly equal to vdd, which is then given to the stage consisting of two inverters which finally makes output equal to vdd. Table 1: transistor sizes of the proposed comparator
Transistor PM0 PM1 PM2 PM3 NM0 NM1 NM2 NM3 NM4 W (um) 10 10 2 2 6 6 1 1 10 L (nm) 180 180 180 180 180 180 180 180 180

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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME On the other hand when the input voltage is less than the reference voltage the input transistor in the left leg of the circuit goes into cutoff and the entire current from the source flows only into the right leg and thus the voltage at the output node will be nearly equal to zero and the next stage will make it exactly zero. W/Ls of the transistors used in the comparator are shown in Table 1, The above proposed comparator circuit consists of total 9 (4 pmos and 5 nmos) transistors. The widths and lengths of each of these transistors are shown in table I. Fig 4 shows the transient responses of the comparator. In the transient response it can be seen that whenever the input sinusoidal signal voltage is above the reference voltage (which is 1volt in this case) the comparator output is logic-1 and whenever it is below the reference voltage the comparator output is logic-0.

Fig.4. Comparator Output The ac response in fig 5 shows that the comparator can work efficiently up to 4G-HZ since this comparator circuit can provide sufficient gain up to this frequency after which the response degrades and circuit cannot be used as a comparator beyond this frequency.

Fig.5. AC response of the comparator B) THERMOMETER TO BINARY ENCODER DESIGN

The outputs of comparators form a thermometer code (TC) which is a combination of a series of zeros and a series of ones, e.g., 000011111 and are given to Thermometer to binary encoder circuit.

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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME

Fig .6. Block Diagram of Sub-ADC Because binary code is usually needed for digital signal processing, a thermometer code is then transformed to a binary code through a (2k-1)-to-k (2k TC-to-BC BC encoder, where k is the resolution (bits) of ADCs. Truth table for thermometer to binary encoder is as shown in table2 tab Table.2. Thermometer to binary code

The logic that has been used in implementing the thermometer to binary encoder is that the output binary code is numerically equal to the number of 1s present in the input thermometer code.

Fig.7. Thermometer to Binary Encoder 312

International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME Hence the output binary code can be obtained by simply adding all the bits of the input thermometer code. This has been implemented by using the full adder circuits as shown in the fig 7

FIG.8. OUTPUT OF THERMOMETER TO BINARY CODE CONVERTER Figure 8 shows the output of the comparators which are called as thermometer code, the bottom 3 wave forms are the converted 3 bit binary code. It can be seen from this result that as the number of input signals having the value equal to logic-1 1 increases by one the binary output of the circuit also increases by one in value. C) FINAL 3BIT FLASH ADC BLOCK After having designed the comparator and the thermometer to binary converter circuits, the next step is to arrange the seven comparators in parallel, where the one input to each of the comparator is the input signal and the other input is the reference voltages, voltages, which is shown in the figure 9.

Fig.9. Final Flash ADC Here the comparator used is that of the figure 3 and the reference voltages required are derived from a series of voltage sources each having a voltage of 250mV. Hence the voltage obtained as reference for the bottom most comparator is 250mV and that of the top most seventh comparator is 1.75V. Hence the reference voltages for the 3-bit 3 flash ADC is according to the table 2.

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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME

Fig.10. Layout of Flash ADC III.ADC OUTPUT WAVEFORMS For the Flash ADC complete layout is prepared as shown in figure 10 where the most sensitive parts are the comparators for which common centroid layout is carried out in order to overcome the errors in the fabrication process.

Fig.11. Final output of 3bit Flash ADC Figure 11 shows the output of final 3-bit flash ADC designed. It can be observed from this figure that the input signal applied to the flash ADC is a sinusoidal signal whose input voltage varies from 0V to 2V which generates a 3-bit binary output which varies from 000 to 111 as the input sinusoidal voltage increases from 0V to 2V.

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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME III. CONCLUSION A 3-bit Flash ADC has been designed using the proposed comparator circuit. The implementation of this circuit has Been done in cadence environment and output waveforms have been obtained. IV. REFERENCES [1] Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw-Hill Edition, 2002. [2] R.Jacob Baker, Harry W. Li & David E. Boyce, CMOS circuit design, layout and simulation, IEEE Press Series on Microelectronic Systems, Prentice-Hall of India Private Limited, 2004. [3] Klass Bult and Govert J. G. M. Geelen, A Fast Settling CMOS OpAmp for SC Circuits with 90dB DC Gain , IEEE J. Solid-State Circuits, Vol.25, No.6, December 1990. [4] Thomas Byunghak Cho, Student Member, IEEE, and Paul R. Gray, Fellow, IEEE, A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter, IEEE J. Solid-State Circuits, Vol.30, No.3, March 1995. [5]. Mark Ferriss, Joshua Kang, A 10-Bit 100-MHz Pipeline ADC, University of Michigan, 598 design project, 2004. [6]. Andrew M. Abo and Paul R. Gray, Fellow, IEEE, A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, IEEE J. Solid-State Circuits, Vol.34, No.5, March 1999. [7].Stephen H. Lewis, H.Scott Fetterman, George F. Gross, R. Ramachandran and T. R. Viswanathan, A 10-b 20-Msample/s Analog-to-Digital Converter, IEEE J. Solid-State Circuits, Vol.27, No.3, March 1992. [8]. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits: A Design Perspective, Prentice Hall, 2nd edition [9] Suhas. S. Khot, Prakash. W. Wani , Mukul. S. Sutaone and Saurabh.K.Bhise, A 581/781 Msps 3Bit Cmos Flash Adc Using Tiq Comparator International Journal Of Electronics And Communication Engineering &Technology (IJECET) Volume 3, Issue 2, 2012, PP: 352 359 ISSN PRINT: 0976- 6464, ISSN ONLINE: 0976 6472 [10]Rajinder Tiwari, R K Singh, An Optimized High Speed Dual Mode Cmos Differential Amplifier for Analog Vlsiapplications International Journal of Electrical Engineering & Technology (IJEET) Volume 3, Issue 1, 2012, PP: 180 187, ISSN PRINT: 0976-6545, ISSN ONLINE: 0976-6553 [11] S. S. Khot, P. W. Wani,M. S. Sutaone and S.K.Bhise, A 555/690 Msps 4-Bit Cmos Flash Adc Using Tiq Comparator International Journal of Electrical Engineering & Technology (IJEET) Volume 3, Issue 2, 2012, PP: 373 382, ISSN PRINT: 0976-6545, ISSN ONLINE: 0976-6553

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