External Super Multi DVD Rewriter

MODEL: GSA-5168D /GSA-5169D

SERVICE MANUAL

P/NO : 3828HS1050D Feb, 2006 Printed in Korea

MODEL : GSA-5168D/GSA-5169D

TABLE OF CONTENTS
SECTION 1 : GENERAL
INTRODUCTION .......................................................................................................................................................................3 GENERAL FEATURES .........................................................................................................................................................3~5 SPECIFICATIONS.................................................................................................................................................................6~9 OPERATING MANUAL .....................................................................................................................................................10~20 DISASSEMBLY .......................................................................................................................................................................21 1. TOP COVER AND BOTTOM COVER.............................................................................................................................21 2. BOTTOM SHIELD ...........................................................................................................................................................21 3. TOP SHIELD AND USB BRIDGE BOARD......................................................................................................................21 EXPLODED VIEW .............................................................................................................................................................23~24 REPLACEMENT PARTS LIST..........................................................................................................................................25~26 MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION.............................................................................27~50 USB AV CAPTURE & BRIDGE BOARD TROUBLESHOOTING GUIDE ..............................................................................51 POWER CORD SECTION .......................................................................................................................................................53 BLOCK DIAGRAM[USB AV CAPTURE & BRIDGE BOARD] .................................................................................................54 CIRCUIT DIAGRAM[USB AV CAPTURE & BRIDGE BOARD] .........................................................................................55~57 PRINTED CIRCUIT BOARD DIAGRAM ...........................................................................................................................58~61

SECTION 2 : DVD MULTI DRIVE ASSY

DISASSEMBLY .................................................................................................................................................................62~63 1. CABINET AND CIRCUIT BOARD ...................................................................................................................................62 2. MECHANISM ASSY ........................................................................................................................................................62 EXPLODED VIEW .............................................................................................................................................................64~65 REPLACEMENT PARTS LIST..........................................................................................................................................66~67 DVD & CD DATA PROCESSING......................................................................................................................................68~71 INTERNA STRUCTURE OF THE PICK-UP......................................................................................................................72~74 DESCRIPTION OF CIRCUIT.............................................................................................................................................75~79 MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION.............................................................................80~97 TROUBLESHOOTING GUIDE ........................................................................................................................................98~114 BLOCK DIAGRAM ........................................................................................................................................................115~116 PRINTED CIRCUIT BOARD DIAGRAM .......................................................................................................................117~120 ELECTRICAL REPLACEMENT PARTS LIST ......................................................................................................................121

CAUTION - INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM.

SECTION I GENERAL
INTRODUCTION
This service manual provides a variety of service information. It contains the mechanical structure of the External Super Multi DVD Rewriter and the electronic circuits in schematic form. This External Super Multi DVD Rewriter was manufactured and assembled under our strict quality control standards and meets or exceeds industry specifications and standards.

GENERAL FEATURES
1 General
1) Universa Serial Bus (USB) 2.0 interface for high-speed data transfer. (Internal Drive : GSA-4164B or GSA-4166B, ATAPI interface.) 2) External Half-height drive 3) Buffer Under Run error protection technology 4) Emergency eject support 5) Bear media loading with power eject. 6) CD-R/RW, DVD-R/-R DL(Dual Layer)/-RW/-RAM/+R/+R DL(Double Layer)/+RW read and write compatible, CD Family and DVD-ROM read compatible. 7) Supports region playback control Phase II. 8) Supports LightScribe-Direct Disc Labeling (GSA-5168D only).

2. Supported disc formats

1) Reads data in each DVD-ROM, DVD-R(Ver. 1.0, Ver. 2.0 for Authoring) and DVD-RAM(Ver.1.0) 2) Reads and writes in each DVD-R(Ver. 2.0 for General),DVD-R DL(Dual Layer) DVD-RW, DVDRAM(Ver.2.2), DVD+R, DVD+R DL(Double Layer) and +RW 3) Reads data in each CD-ROM, CD-ROM XA, CD-I, Video CD, CD-Extra and CD-Text 4) Reads data in Photo CD (Single and Multi session) 5) Reads standard CD-DA 6) Reads and writes CD-R discs conforming to Orange Book Part 2 7) Reads and writes CD-RW discs conforming to Orange Book Part 3 8) Reads DVD-RAM with CPRM and DVD-RW with CPRM 9) LightScribe DVD+R confirming to LightScribe Media Specification 10) LightScribe CD-R conforming to LightScribe Media Specification

3. Supported write method

1) DVD-R: ..................Disc at Once and Incremental Recording 2) DVD-R DL : ..........Sequential Recording 3) DVD-RW:...............Disc at Once, Incremental Recording and Restricted Overwrite 4) DVD-RAM:.............Random Write 5) DVD+R: .................Sequential Recording 6) DVD+R DL: ...........Sequential Recording 7) DVD+RW:..............Random Write 8) CD-R/RW: .............Disc at Once, Session at Once, Track at Once and Packet Write 9) LightScribe Label Printing Functions complying with LightScribe System Specification.

4. Performance
1) Average access time: (1/3 stroke) 2) Write speed: DVD-ROM CD-ROM DVD+R DVD+RW DVD-R DVD-RW DVD+R DL DVD-R DL DVD-RAM CD-R CD-RW 3) Read speed: DVD-ROM 16x max. DVD-Video(CSS Compliant Disc) 8x max. (Single/Dual layer) DVD-R/-RW/DL 16x/ 8x / 8x max. DVD+R/+RW/DL 16x/ 8x / 8x max. DVD-RAM (Ver.1.0/2.2) 2x, 3x, 5x CLV CD-R/RW/ROM 48x / 32x 48x max. CD-DA (DAE) 40x max. 4) Sustained Transfer rate: DVD-ROM 22.16 Mbytes/s (16x) max. CD-ROM 7,200 kB/s (48x) max. 5) Burst Transfer rate: USB 2.0 480Mbps (High-Speed) USB1.1 Compliant 6) Multimedia MPC-3 compliant 7) LightScribe label Printing (GSA-5168D only) Pixel Resolution 600 [DPI] Track Resolution 500~1600 [TPI] Linear Velocity 0.25~1.00 [m/sec] Laser Power 30~60 [mW] as Objective emission light of 780nm wavelength Color Monochrome * You can use a variety of Drive. 140 ms 120 ms 2.4x, 4x (CLV), 8x (ZCLV), 12x (PCAV), 16x (CAV) 2.4x, 4x (CLV), 8x (ZCLV) 2.4x, 4x (CLV), 8x (ZCLV), 12x (PCAV), 16x (CAV) 1x, 2x, 4x (CLV), 6x (ZCLV) 2.4x, 4x (CLV), 6x, 8x (ZCLV) 4x (CLV) 2x, 3x, 5x CLV (Ver.2.2) 16x (CLV), 24x (ZCLV), 32x, 40x, 48x (CAV) 4x, 10x, 16x (CLV), 24x, 32x (ZCLV) (High Speed: 8x, 10x, Ultra Speed> 16x)

GSA-5168D
LightScribe I/F Internal Drive Yes USB2.0 only GSA-4166B

GSA-5169D
No USB2.0 only GSA-4164B

5. AV Capture
1) Receive Video Video(S-Video) and Audio analog signal 2) Video Encoding Standard : MPEG-2, MPEG-1 3) Data Multiplexing : MPEG-2 (ISO/IEC 1318-1) 4) Audio compression : Read : MPEG-1, MPED-2, AC3 5) Write : MPEG-1, Layer-2 6) Video Type : NTSC/PAL 7) Video Format : VCD/SVCD/DVD/AVI 8) Supported capture Recording disc : CDR, CDRW (VCD/SVCD/AVI) 9) DVD+R, DVD_RW, DVD+R DL (DVD/AVI) * Definition Transfer Rate : Capacity :

1x (DVD) = 1.385 mbytes/s, Mbytes/s = 106 bytes/s, MB = 220 bytes, kB = 210 bytes

1x (CD) = 150 kB/s kB/s = 210 bytes/s

SPECIFICATIONS
I. MODEL : GSA-5169D
1. SYSTEM REQUIREMENTS
-CPU: IBM Compatible Pentium 4 2.4GHz (or faster) -512MB Memory or greater -USB 2.0 support

2. SUPPORTING OPERATING SYSTEM

* Operating System Window 2000 Professional Window XP Home Edition, Professional * AV Capture tool One touch DVD(Honestech) 2.1 Applicable disc formats DVD ............................DVD-ROM: DVD-R DL: DVD-R: DVD-RW: DVD-RAM: DVD+R: DVD+R DL: DVD+RW: 4.7GB (Single Layer) 8.5GB (Dual Layer) 8.5GB 4.7GB (Ver.2.0 for Authoring : read only) 4.7GB (Ver.2.0 for General: read & write) 4.7GB (Ver.1.2) 2.6GB/side (Ver.1.0) 1.46GB/side, 4.7GB/side (Ver.2.2) 4.7GB 8.5GB 4.7GB * Recording tool (1) Nero(Ahead) (2) In CD(Ahead) (3) Power Producer Gold (Cyber Link)

CD...............................CD-ROM Mode-1 data disc CD-ROM Mode-2 data disc CD-ROM XA, CD-I, Photo-CD Multi-Session, Video CD CD-Audio Disc Mixed mode CD-ROM disc (data and audio) CD-Extra CD-Text CD-R (Conforming to Orange Book Part2: read & write) CD-RW (Conforming to Orange Book Part3: read & write) 2.2 Writing method (1) DVD-R/RW ...........................Disc at Once Incremental Recording Restricted Overwrite (DVD-RW only) (2) DVD-R DL ............................Sequential Recording (3) DVD-RAM/+RW ...................Random Write (4) DVD+R .................................Sequential Recording (5) DVD+R DL ...........................Sequential Recording (6) CD-R/RW .............................Disc at Once (DAO) Session at Once (SAO) Track at Once (TAO) Packet Write

2.3 Disc diameter ..............................................120mm 80mm (Horizontal only) 2.4 Data capacity User Data/Block DVD-ROM/R/RW/RAM/+R/+RW ......2,048 bytes/block CD (Yellow Book) ..........................................2,048 bytes/block(Mode 1 & Mode 2 Form 1) 2,336 bytes/block (Mode 2) 2,328 bytes/block (Mode 2 Form 2) 2,352 bytes/block (CD-DA) 2.5 RPC (Regional Playback Control) Phase2, No Region

3. DRIVE PERFORMANCE
3.1 Host interface ..................................................................USB 2.0 (480Mbits/s) 3.2 Read/Write & Rotational speed <Write> DVD-R ...............................................................2x, 4x (CLV), 8x (ZCLV), 12x (PCAV), 16x DVD-RW............................................................1x, 2x, 4x (CLV), 6x (ZCLV) DVD+R ..............................................................2.4x, 4x (CLV), 8x (ZCLV), 12x (PCAV), 16x (CAV) DVD+RW...........................................................2.4x, 4x (CLV), 8x (ZCLV) DVD+R DL.........................................................2.4x, 4x (CLV), 8x (ZCLV) ... DVD-R DL..........................................................4x (CLV) DVD-RAM ...............................Ver. 2.2 .............2x, 3x (CLV), 5x (PCAV) CD-R..................................................................16x (CLV), 24x (ZCLV), 40x, 48x (CAV) CD-RW ..............................................................4x, 10x,16x (CLV), 24x, 32x (ZCLV) ...........................................................................(High Speed: 8x, 10x, Ultra Speed: >16x) <Read> DVD-ROM ...............................Single layer .......6.7x - 16x (CAV), .................Approx. 9,200 r/min Dual layer..........3.3x - 8x (CAV), .................Approx. 5,200 r/min DVD-Video (CSS)..............................................3.3x - 8x (CAV) DVD-R.....................................3.95GB..............6.7x - 16x (CAV), .................Approx. 9,200 r/min 4.7GB................6.7x - 16x (CAV), .................Approx. 9,200 r/min DVD-RW .................................4.7GB................3.3x - 8x (CAV), .................Approx. 4,500 r/min DVD+R ....................................4.7GB................6.7x - 16x (CAV), .................Approx. 9,200 r/min DVD+RW.................................4.7GB................3.3x - 8x (CAV), .................Approx. 4,500 r/min DVD+R DL ..............................8.5GB................3.3x - 8x (CAV), .................Approx. 4,500 r/min DVD-R-DL ...............................8.5GB................3.3x - 8x(CAV), .................Approx. 4,500r/min DVD-RAM ...............................Ver. 1.0/ 2.2 ......2x/ 3x (CLV), 5x (PCAV) 1x : Approx. 2,390 (Inside) - 1,010 r/min (Outside)/ Ver.2.2 2 x: Approx. 3,250 (Inside )- 1,380 r/min (Outside) CD-R/ROM, data CD-1......................................20x - 48x (CAV), .................Approx. 9,800 r/min CD-RW ..............................................................15x - 32x (CAV), ..................Approx. 6,400 r/min CD-DA (DAE) ....................................................17x - 40x (CAV), .................Approx. 8,000 r/min CD-DA (Audio out)/Video CD ............................6x - 15x (CAV), ....................Approx. 3,130 r/min

3.3 Data transfer rate 3.3.1 Sustained transfer rate <Write> DVD-R.........................2.77, 5.54, 5.54-11.08, 8.91-22.16 Mbytes/s ; 2x, 4x (CLV), 8x (ZCLV), 12x (PCAV), 16x (CAV) DVD-RW ...............1.385, 2.77, 5.54, 8.31 Mbytes/s , 2x, 4x (CLV), 6x (ZCLV) DVD+R ........................3.32, 5.54, 5.54-11.08, 8.91-22.16 Mbytes/s ; 2x, 4x (CLV), 8x (ZCLV), 12x (PCAV), 16x (CAV) DVD+RW.....................3.32, 5.54, 11.08 Mbytes/s, 2.4x, 4x (CLV), 8x (ZCLV) DVD+R DL ..................3.32, 5.54, 8.31-11.08 Mbytes/s, 2.4x, 4x CLV, 8x ZCLV DVD-R DL 5.54 Mbytes/s, 4x CLV DVD-RAM(Ver. 2.2): ...2.77, 4.15, 4.15-6.925 Mbytes/s, 2x, 3x (CLV), 5x (PCAV()w/o Verify) CD-R 2,400, 2,400-3,600, 2,400-7,200, kB/s (Mode-1) ; 16x (CLV), 24x (ZCLV), 40x, 48x (CAV) CD-RW........................600, 1500, 2,400, 2,400- 3,600 kB/s (Mode-1) ; 4x, 10x, 16x (CLV), 24x, 32x (ZCLV) <Read> DVD-ROM ...................Single layer.......................6.88 - 22.16 Mbytes/s .........................16x max. DL..........................................................................4.58 - 11.08 Mbytes/s............................8x max. DVD+/-R................................................................6.88 - 22.16 Mbytes/s..........................16x max. DVD+/-RW/DL.......................................................4.58 - 11.08 Mbytes/s ...........................8x max. DVD-RAM ...................Ver. 1.0 .............................2.77 Mbytes/s ......................................2x ZCLV Ver. 2.2 .............................2.77, 4.155,4.155-6.93 Mbytes/s ..2x, 3x ZCLV, ; 5x PCAV CD-R/ROM ............................................................2,700 - 7,200 kB/s ...............................48x max. CD-RW........................ .........................................2,250 - 3,600 kB/s ...............................32x max. CD-DA (DAE) ........................................................2,550 - 6,000 kB/s ...............................40x max. 3.4 Access time (1/3 stroke) DVD-ROM..............................................................140 ms Typ. (Note 1) DVD-RAM (Ver.2.1) ...............................................250 ms Typ. CD-ROM ................................................................120ms Typ. (Note 1) Note : 1) Average access time is the typcal value of more than 50 times including latency and error correction time. Test Disc : DVD : ALMEDIO TDV-520 / TDR-820 CD : ALMEDIO TCDR-701 / HITACH HCD-1 *) Typical value defines a measured value in normal temperature (20 deg.C.) and horizontal position. 3.5 Data error rate (Measured with 5 retries maximum) DVD-R/RW/ROM/RAM ..................................<10-12 DVD-+R/+RW.................................................<10-12 CD-R/RW/ROM..............................................<10-12 (Mode-1) <10-9 (Mode-2) Condition : It is assumed that the worst case raw error rate of the disc is 10-3 3.6 Data buffer capacity .......................................................2 Mbytes

4. Quality and Reliability

4.1 MTBF ..................................................125,000 Power On Hours(Consecutive/Cumulative POH) Assumption : ..........................Used in a normall office environment at room temperature. -POH per year.........................3,000 -ON/OFF cycles per year........600 -Operating duty cycle..............20% of power on time (Seek: 5% of operating time) 4.2 Tray cycle test ...................................30,000 times No degeneration in the mechanical part after test 4.3 Actuator mechanism ........................1,000,000 full stroke seek 4.4 MTTR (Mean Time To Repair) ...........0.5 h 4.5 Component life .................................5 years or 2,000 h of Laser radiating time Assumption : ..........................Used in a normall office environment.

5. POWER REQUIREMENTS
5.1 Power Requirements AC Adaptor INPUT : 100-240V AC, 0.6A 47-63Hz OUTPUT : 12V DC 2A (max2.5A) * Please Contact the friendly staff of LG Service Care at: Website http: //www.LGEservice.com

6. Dimensions
External dimensions (Wx H x D) .............................................160 x 50 x 230 mm

7. Mass

1370g +/-30g (net)

OPERATING MANUAL

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DISASSEMBLY
1. TOP COVER AND BOTTOM COVER
A. Remove 4 side rubbers and release 2 screws (A). B. Release 2 screws (B) on the bottom cover and remove Bottom cover in the direction of arrow (1). C. And then, remove Top cover in the direction of arrow (2). (See Fig.1) Side Rubbers

2. BOTTOM SHIELD
A. Release 9(or 5) screws (C) and Remove Bottom Shield (3). (See Fig.2)

Internal DVD Multi Drive

(C)

(A)

(3)

Top Cover
(2)

(A)

Bottom Shield
265

(C)
Fig. 1-2
(1)

3. TOP SHILD AND USB BRIDGE BOARD

A. Remove Top Shield (4). B. Release 2 screws (D) and remove the USB bridge board in the direction of arrow (4). (See Fig.1-3)

Bottom Cover

(B)

Fig. 1-1

Top Shield
265

(4)

USB Bridge Board

(D)

(D)

Fig. 1-3

21

EXPLODED VIEW
5

261 484
4

265 487 A40 487

265

250 487
3

261 484 003 494

PBF01

487
PBS00 (USB C.B.A)

002 266 489 260 484

A B C
23

487

D
24

MECHANICAL REPLACEMENT PARTS LIST

MODEL: GSA-5168D
LOCA.NO PART NO(GS) DESCRIPTION SPECIFICATION NSP: Not Service Part REMARKS

ASSEMBLE PARTS SECTION

A40 6779H-1048A DVD MULTI DRIVER ASSY JX1 GSA-5168D EVNT

PARTS SECTION
250 260 261 265 266 002 003 PBS00 PBF01 3551H-1034A 3550H-1124A 5040H-1108A 3300H-1265A 3300H-1266A 3580H-1109A 3061H-1175A 6871H-410BA 6871H-411AA COVER ASSEMBLY COVER RUBBER PLATE PLATE DOOR BEZEL ASSEMBLY PWB (PCB) ASSEMBLY PWB (PCB) ASSEMBLY TOP(JX1) GSA-5169D BOTTOM JX1 (BLACK) SIDE HOOT(JX1) TOP SHIELD (JX1) BOTTOM SHELD (JX1) TRAY (JX1) JRP5 (JX1) JX1 MP2 PWB (PCB) ASSEMBLY BEZEL PWB (PCB) ASSEMBLY JX1

SCREW
484 487 489 494 ISZZH-1214A ISZZH-1217A ISZZH-1219A ISZZH-1224A SCREW, DRAWING SCREW, DRAWING SCREW, DRAWING SCREW, DRAWING ROUND D3.0 8MM SWCH18A/CZN5 ROUND D5.5 4MM PA 5.5MM 2MM MA FLAT D3.0 6MM SWRCH 18A/BZN 5.5MM ROUND D3.0 6MM SWCH 18A/BZN 5.5MM

Note: Refer to DVD MULTI DRIVER ASSY REPLACEMENT PARTS LIST in order to look for the part number of A40.

MISCELLANEOUS PARTS
801 802 805 806 807 810 811 811 812 812 812 814 815 3828HM1056T 3840HW1017A 3890H-2103A 3890H-2104A 3920H-1121A 6851HC3005A 6851HC3006A 6956H-D030B 6851HU7002A 6851HU7004A 6956H-D030C 6410HE1201K 6634A00006A MANUAL, OWNERS CARD, WARRANTY BOX BOX PACKING CABLE ASSEMBLY CABLE ASSEMBLY COMPACT DISC TITLE, DVD CABLE ASSEMBLY CABLE ASSEMBLY COMPACT DISC TITLE, DVD POWER CORD ADAPTER, AC EXTERNAL DRIVE (GSA-5168D) WITH OPTICAL STORAGE(DOMESTIC) GIFT GSA-5168D CD-TOWN-KR SHIPPING GSA-5168D CD-TOWN-K INDIVIDUAL GSA-5160B (EXTER) 5602-E04N-01B, UL1007 20AWG STR 5341-N40N-12B 40PIN IDC CABLE GSA-5169D WITH L/S (ONE TOUCH) U00088 DOTOP USB USB SA5320-0100-BK REV 1.0 SUREFIR GSA-5168D NERO TOOL WITH L/S KJTS04-132 KUKJETONGSHIN KS/ 18 DA24B12 12V 2.5A

NSP

25

MECHANICAL REPLACEMENT PARTS LIST

MODEL: GSA-5169D
LOCA.NO PART NO(GS) DESCRIPTION SPECIFICATION NSP: Not Service Part REMARKS

ASSEMBLE PARTS SECTION

A40 6779H-1048A DVD MULTI DRIVER ASSY JX1 GSA-5168D EVNT

PARTS SECTION
250 260 261 265 266 002 003 PBS00 PBF01 3551H-1034A 3550H-1124A 5040H-1108A 3300H-1265A 3300H-1266A 3580H-1109A 3061H-1175A 6871H-410BA 6871H-411AA COVER ASSEMBLY COVER RUBBER PLATE PLATE DOOR BEZEL ASSEMBLY PWB (PCB) ASSEMBLY PWB (PCB) ASSEMBLY TOP(JX1) GSA-5169D BOTTOM JX1 (BLACK) SIDE HOOT(JX1) TOP SHIELD (JX1) BOTTOM SHELD (JX1) TRAY (JX1) JRP5 (JX1) JX1 MP2 PWB (PCB) ASSEMBLY BEZEL PWB (PCB) ASSEMBLY JX1

SCREW
484 487 489 494 ISZZH-1214A ISZZH-1217A ISZZH-1219A ISZZH-1224A SCREW, DRAWING SCREW, DRAWING SCREW, DRAWING SCREW, DRAWING ROUND D3.0 8MM SWCH18A/CZN5 ROUND D5.5 4MM PA 5.5MM 2MM MA FLAT D3.0 6MM SWRCH 18A/BZN 5.5MM ROUND D3.0 6MM SWCH 18A/BZN 5.5MM

Note: Refer to DVD MULTI DRIVER ASSY REPLACEMENT PARTS LIST in order to look for the part number of A40.

MISCELLANEOUS PARTS
801 802 803 804 805 806 807 812 814 815 3828HN1012D 3840HF1035H 3840HR1010A 3840HW1023B 3890H-2075A 3890H-2050A 3920H-1121A 6956H31040Z 6410HE1201M 6634A00006A MANUAL, INSTALLATION CARD, INFORMATION CARD, REGISTRATION CARD, WARRANTY BOX BOX PACKING COMPACT DISC TITLE, CD-R POWER CORD ADAPTER, AC EXTERNAL DRIVE GSA-5169D AV D.O.C SHEET GSA-5169D[LG OR HL] OPTICAL STORAGE [LGEUS] NORTH OR SOUTH AMERICA, OPTICA GIFT GSA-5169D US-WITH HANDL SHIPPING GSA-5169D LG(W/W)-P INDIVIDUAL GSA-5160B (EXTER) GSA-5169D KJTS04-134 KUKJETONGSHIN UL/CS DA24B12 12V 2.5A

NSP

26

MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION (USB AV Capture & Bridge Board)
IC101(PL2507C) : Hi-Speed USB 2.0 to IDE Bridge Controller
1-1. General description
The PL-2507C is a single chip Hi-Speed USB-to-IDE bridge controller that is designed to perform seamless protocol transfer between the USB and ATA interface. The operating speed is determined by the capability of the host/hub it is connected to. PIO mode 0 to mode 4, Multi Word DMA mode 0 to mode 2, and Ultra DMA mode 0 to mode 4 are implemented to support broad range of standard ATA and ATAPI devices. The PL-2507C supports two devices at the same time using Master/Slave mode and upgradeable firmware using large EEPROM or SPI Flash.

1-2. Block Diagram

27

2.0. PIN Assigment & Description

2-1. Pin Assigment for LQFP64 Package

28

2-2. USB2.0 PHY Related Pins

29

30

IC301(MC74HC4052A) : Analog Multiplexers / Demultiplexers High-Performance Silicon-gate CMOS

1-1. General description
The MC74HC4052A utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The HC4052A is identical in pinout to the metal-gate MC14052AB. The Channel-select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel-select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal-gate CMOS analog switches. Analog Power Supply Range (VCC - VEE) = 2.0 to 12.0 V Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V

1-2. LOGIC DIAGRAM

31

IC401(EMP202) : Single-Chip Dual-Channel AC97 Audio Codec for PC Audio Systems

1. General description
The EMP202 is a 2 channel, 20-bit DAC and 20-bit ADC, full duplex AC 97 2.2 compatible stereo audio CODEC designed for PC multimedia systems, including soft/host audio and riser card based designs. The EMP202 incorporates proprietary converter technology.

2. Block Diagram

32

3. Pin Assigment

33

4. PinDescription

34

35

IC501(X6417CE01) : High speed LDO Regulator+VD

1. Block Diagram

2. Pin Configuration and Pin Assignment

VR

Power

3. Function
OPERATION

36

IC505(APW1172) :2.5A SWITCH STEP DOWN SWITCHING REGULATOR

1. General Description
The APW1172 is a step down monolithic power switching regulator with a switching current limit of 3.8A so it is able to deliver more than 2.5A DC current to the load depending on the application conditions. The output voltage can be set from 1.235V to 22V.The high current level is also achieved utilize an SO8 package with exposed pad frame. The type of package allows to re-duce the Rth (j-amb) down to approximately 45 C/W. An internal oscillator fixes the switching frequency at 250KHz. Having a minimum input voltage of 4.8V only, it is particularly suitable for 5V bus, available in all computer related applications.

2. Pin Description

= Thermal Pad (connected to GND plane for better heat dissipation)

37

3. Block Diagram

4. Pin Function Description

No. 1 2 3 4 5 PIN OUT SYNC INH COMP FB Description Regulator Output. Master/Slave synchonization. A logical signal (active high) disables the device. If INH not used the pin must be connected to GND. When it is open an internal pull-up disable the device. E/A output for frequency compensation. Feedback input. Connecting directly to this pin results in an output voltage of 1.235V(APW1172). An external resistive divider is required for higher output voltages. 3.3V reference voltage output, no Capacitor Is requested for stability. Ground. Unregulated DC input voltage.

6 7 8

VREF GND VCC

38

IC601(TVP150AM1) : Ultralow Power NTSC/PAL/SECAM Video Decoder WIth Robust Sync Detector
1. Introduction
The TVP5150A device is an ultralow power NTSC/PAL/SECAM video decoder. Available in a space saving 32-pin TQFP package, the TVP5150A decoder converts NTSC, PAL, and SECAM video signals to 8-bit ITUR BT.656 format. Discrete syncs are also available. The optimized architecture of the TVP5150A decoder allows for ultralow-power consumption. The decoder consumes 115 mW of power in typical operation and consumes less than 1 mW in power-down mode, considerably increasing battery life in portable applications. The decoder uses just one crystal for all supported standards. The TVP5150A decoder can be programmed using an I2C serial interface. The decoder uses a 1.8-V supply for its analog and digital supplies, and a 3.3V supply for its I/O.

1.1. Functional Block Diagram

39

1.2. Terminal Assignments

1.3. Terminal Function

40

41

IC701(EM2860) : USB Video Capture Device EM2860 Supports Video Decoder, Audio Decoder, and VBI
1. General Description
EM2860 USB Video Capture Device (UVCD) is a highly integrated VLSI that provides a cost-effective solution for video capture applications on USB 2.0. Typical applications of this device are: CMOS PC-Camera NTSC/PAL Video Capture

2. Functional Block Diagram

USB

EM2860
USB 2.0 PHY

Video Source

Serial Interface

SIE

Video Interface

Video Pipe line Stream Buffer

Audio Source

Audio Interface

3. Pin Assignment
RW_DOWN LED SNAP RM RD RCE VCC2 RC6 GND RO6 GND RO4 SDO SYMC BCLK IR 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

GND WSEL TESTMODE EXTPHY VCC3 CLKINT VCLKI VCC2 GND XSCI XSCO VCC3 AGND RREF DM DP

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

EM2860

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

VCC3 SDI RO8 RO2 RO1 GND SDA SDA SCL VREF HREF SCLK VCLK VID7 VCC3 VID6

42

(NC) (NC) (NC) (NC) AVCC3 AGND (NC) GND VID0 VCC2 VID1 VID1 VID3 GND VID4 VID5

01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16

4. Pin Descriptions
4.1. Video Interface Symbol XCLK VCLK VREF HREF FID VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Pin No. 21 20 23 22 44 19 17 16 15 13 12 11 9 Type O I B B I I I I I I I I I Description Video sycchronous clock output Video reference clock from video source Vertical reference (sync) signal from video source in input mode. Video timing generator vertical reference output in output mode. Horizontal reference (sync) signal from video source in input mode. Video timing generator Horizontal reference output in output mode. Field ID from video source Video input data, bit 7 Video input data, bit 6 Video input data, bit 5 Video input data, bit 4 Video input data, bit 3 Video input data, bit 2 Video input data, bit 1 Video input data, bit 0

4.2. Audio Interface Symbol BCLK SDI SYNC SDO WSEL Pin No. 34 31 35 36 50 Type I I O O I Description AC97/I2S bit clock AC97/I2S serial data input AC97 48KHz fized rate sample sync AC97 serial data output I2S word select at audio sample rate

4.3. USB Interface Symbol DP DM RREF XSCI XSCO Pin No. 64 63 62 58 59 Type B B Analo Analo Analo Description USB differential data positive USB differential data negative Connect reference resistor (12.1 KOhm, 0.1%) to Analog Ground Crystal oscillator input 12MHz Crystal oscillator output 12MHz

43

4.4. Serial Bus and Programmable I/O Symbol SCL SDA PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 PIO0 Pin No. 24 25 43 41 39 37 30 29 28 27 Type B B B B B B B B B B Description Serial bus clock, require external pull-up resistor. Serial data, require external pull-up resistor. General I/O Port 7, require external pull-up resistor in output mode. General I/O Port 6, require external pull-up resistor in output mode. General I/O Port 5, require external pull-up resistor in output mode. General I/O Port 4, require external pull-up resistor in output mode. General I/O Port 3, require external pull-up resistor in output mode. General I/O Port 2, require external pull-up resistor in output mode. General I/O Port 1, require external pull-up resistor in output mode. General I/O Port 0, require external pull-up resistor in output mode.

4.5.Remote Control Infrared Sensor Interface Symbol IR Pin No. 33 Type I Description Infrared sensor signal

4.6. Miscellaneous Symbol RN SNAP LED PW_DOW TESTMO EXTPHY CLKINT UCLKI Pin No. 45 46 47 48 51 52 54 55 Type I I O O I I I I Description Chip reset input. Active low. Connect to power-up RC circuit. Connect to snapshot button Connect to LED Power down external devices. Put the chip in test mode. Normally tie to GND. Select and use external PHY. Normally tie to GND Select and use internal PLL. normally tie to 3.3V VCC Chip clock input when CLKINT=0. Normally tie to GND.

4.7.Power and Ground Symbol AVCC3 AGND VCC3 VCC2 GND (NC) Pin No. 5, 60 6, 61 18, 32, 53 10, 42, 56 8, 14, 26, 38, 40, 49, 57 1, 2, 3, 4, 7 Type Power Ground Power Power Ground Description 3.3V Analog Power Analog Ground 3.3V Digital Power 2.5V Digital Power Digital Ground No connect to internal die

44

IC901(USB2502) : 2-Port Usb2.0 Hub Controller

1. Pin Configuration

SCL/SMBCLK/CFG_SEL0

27

VDD33CR VSS XTAL2 XTAL1/CLKIN VDDA18PLL VDDA33PLL ATEST/REG_EN RBIAS VSS

28

19 18

SDA/SMBDATA

VBUS_DET

CFG_SEL1

CLKIN_EN

RESET_N

VDD18

TEST

VSS

VDD18 VSS SELF_PWR

USB2502 36-QFN

OCS_N PRTPWR PRTPWR_POL CR2/NON_REM1 GR1/NON_REM0

38 1 9

10

VSS

USBDP1

USBDN1

USBDP2

VDDA33

USBDN0

USBDN2

USBDP0

VDDA33

VSS

45

2. Block Diagram

3. Pin Descriptions
3-1. Port Hub Pin Descriptions

NAME

SYMBOL

TYPE

FUNCTION

UPSTREAM USB2.0 INTERFACE USB Bus Data USBDN0 USBDP0 VBUS_DET IO-U These pins connect to the upstream USB bus data signals.

Detect Upstream VBUS Power

I/O8

Detects state of Upstream VBUS power. The SMSC Hub monitors VBUS_DET to determine when to assert the internal D+ pull-up resistor (signaling a connect event). When designing a detachable hub, this pin must be connected to the VBUS power pin of the USB port that is upstream of the hub. (Use of a weak pull-down resistor is recommended.) For self-powered applications with a permanently attached host, this pin must be pulled-up to either 3.3V or 5.0v (typically VDD33).

2-PORT USB2.0 HUB INTERFACE High-Speed USB Data USBDN[2:1] USBDP[2:1] IO-U These pins connect to the downstream USB peripheral devices attached to the Hubs ports.

46

NAME USB Power Enable

SYMBOL PRTPWR

TYPE O8

FUNCTION Enables power to USB peripheral devices (downstream). The active signal level of the PRTPWR pin is determined by the Power Polarity Strapping function of the PRTPWR_POL pin. Green indicator LED for ports 2 and 1. Will be active low when LED support is enabled via EEPROM or SMBus. If the hub is configured by the internal default configuration, these pins will be sampled at the rising edge of RESET_N to determine if ports [2:1] contain permanently attached (non-removable) devices. Also, the active state of the LEDs will be determined as follows: NON_REM[1:0] = 00, All ports are removable, GR2 is active high, GR1 is active high. NON_REM[1:0] = 01, Port 1 is non-removable, GR2 is active high, GR1 is active low. NON_REM[1:0] = 10, Port 1 & 2 are non-removable, GR2 is active low, GR1 is active high. NON_REM[1:0] = 11, Port 1 & 2 are non-removable, GR2 is active low, GR1 is active low.

Port[2:1] Green LED & Port Non-Removable strapping option.

GR[2:1]/ NON_REM [1:0]

I/O8

Port Power Polarity strapping.

PRTPWR_POL

I/O8

Port Power Polarity strapping determination for the active signal polarity of the PRTPWR pin. While RESET_N is asserted, the logic state of this pin will (though the use of internal combinatorial logic) determine the active state of the PRTPWR pin in order to ensure that downstream port power is not inadvertently enabled to inactive ports during a hardware reset. On the rising edge of RESET_N, the logic value will be latched internally, and will retain the active signal polarity for the PRTPWR pin. 1 = PRTPWR pin has an active high polarity 0 = PRTPWR pin has an active low polarity

Over Current Sense

OCS_N

IPU

Input from external current monitor indicating an over-current condition. (Note: Contains internal pull-up to 3.3V supply) A 12.0K (+/-1%) resistor is attached from ground to this pin to set the transceivers internal bias settings.

USB Transceiver Bias

RBIAS

I-R

47

NAME

SYMBOL

TYPE

FUNCTION

SERIAL PORT INTERFACE Serial Data/SMB Data Serial Clock/SMB Clock & Config Select 0 Configuratiion Programming Select SDA/SMBDATA IOSD12 SCL/SMBCLK/ CFG_SEL0 IOSD12 (Serial Data)/(SMB Data) signal. (Serial Clock)/(SMB Clock) signal. This multifunction pin is read on the rising edge of RESET_N (see the applicable RESET_N timing table in Section 5.6.1) and will determine the hub configuration method as described in Table 3.2. This pin is read on the rising edge of RESET_N (see the applicable RESET_N timing table in Section 5.6.1) and will determine the hub configuration method as described in Table 3.2.

CFG_SEL1

3-2. SMBus or EEPROM Interface Behavior

CFG_SEL1 0 1 1 CFG_SEL0 X 0 1 SMBus or EEPROM interface behavior. Configured as an SMBus slave for external download of userdefined descriptors. SMBus slave address is 0101100. Internal Default Configuration via strapping options. 2-wire (12C) EEPROMS are supported.

3-3. Miscellaneous Pins

NAME Crystal Input/ SYMBOL XTAL1/CLKIN TYPE ICLKx FUNCTION 24MHz crystal or external clock input. This pin connects to either one terminal of the crystal or to an external 24MHz clock when a crystal is not used. 24MHz Crystal This is the other terminal of the crystal, or left unconnected when an external clock source is used to drive XTAL1/ CLKIN. It must not be used to drive any external circuitry other than the crystal circuit. Clock In Enalble; low = XTAL1 and XTAL2 pins configured for use with external crystal high = XTAL1 pin configured as CLKIN, and must be driven by an external CMOS clock. This active low signal is used by the system to reset the chip. The minimum active low pulse is 1us. Detects availability of local self-power source. Low = Self/local power source is NOT available (i.e., Hub gets all power from upstream USB Vbus). High = Self/local power source is available. Used for testing the chip. User must treat as a no-connect or connect to ground. This signal is used for testing the analog section of the chip, and to enable or disable the internal 1.8V regulator. This pin must be connected to VDDA33 to enable the internal 1.8V regulator, or to VSS to disable the internal regulator. When the internal regualtor is enable, the 1.8V power pins must be left unconnected, except for the required bypass capacitors. When the PHY is in test mode, the internal regulator is disable and the ATEST pin functions as a test pin.

External Clock Input

Crytal Output XTAL2 OCLKx

Clock Input Enable

CLKIN_EN

RESET Input Self-power / Bus-power Detector TEST Pin Analog Test & Internal 1.8V voltage regulator enable

RESET_N SELF_PWR

IS I

TEST ATEST/ REG_EN

IPD AIO

48

3-4. Power, Ground and No Connect

NAME VDDCORE3P3 SYMBOL VDD33CR TYPE FUNCTION +3.3V I/O Power. if the internal core 1.8V regulator is enabled, then this pin acts as the regulator input. VDD1P8 VDD18 +1.8V core power. If the internal regulator is enabled, then VDD18 pin 27 must have a 4.7F (or greater) + 20% (ESR <0.1) capacitor to VSS. VDDAPLL3P3 VDDA33PLL +3.3V Filtered analog power for the internal PLL. If the internal PLL 1.8V regulator is enabled, then this pin acts as the regulator input. VDDAPLL1P8 VDDA18PLL +1.8V Filtered analog power for internal PLL. If the internal regulator is enabled, then this pin must have a 4.7F (or greater) + 20% (ESR <0.1) capacitor to VSS. VDDA3P3 VSS VDDA33 VSS +3.3V Filtered analog power. Ground.

3-5. Buffer Type Descriptions

BUFFER I IPD IPU IS I/O8 O8 IOSD12 ICLKx OCLKx I-R IO-U DESCRIPTION Input. Input, 40k - 100k Internal pull-down. Input, 40k - 100k Internal pull-up. Input with Schmitt trigger. Input/Output 8mA. Output 8mA. Open drain....12mA sink with Schmitt trigger, and must 12C-Bus Specification Version 2.1 requirements. XTAL Clock Input. XTAL Clock Output. RBIAS Defined in USB Specification. Note: Meets USB1.1 requirements when operating as a 1.1-compliant device and meets USB2.0 requirements when operating as a 2.0-compliant device. AIO Analog Input/Output. Per PHY test requirements.

49

IC902(APL5533) : Dual-Channel, 2.5V/300mA and 1.8V/300mA Linear Regulator

General Description
The APL5533 is a dual low dropout regulator with output1 with 3.5V/0.3A and output2 with 1.8V/0.3A output capability. In order to obtain lower dropout voltage and faster transient response, which is critical for low voltage applications, the APL5533 has been optimized. The dropout voltages are guaranteed at 0.4V at 0.3A for output1 and 0.9V at 0.3A for output 2. Current limit is trimmed to ensure specified output current and controlled short-circuit current. On-chip thermal limiting provides protection against any combination of overload that would create excessive junction temperatures. The APL5533 regulator comes in a SOP-8 and SOP-8-P package.

Pin Configuration

Pin Description

Block Diagram

50

USB AV Capture & Bridge Board Trouble Shooting Guide

Drive Operation?

NO Check the Adaptor Power.(12V)

YES

Check the Power Cable connection. CN601 pin 1, 4 (5V,12V) Check the DC-DC Converter Circuit.(5V) IC505(APW1172), L501, D501

about 11V

Switching Frequency (IC505 pin1)

250 + 25 KHz

USB Operation?

NO Check the USB Cable connection.

YES

Check the 3.3V Power Supply. IC501(XC6417CE) pin 2

Check the IC901 Reset and Oscillating. IC901(USB2502) pin 24(RESET) IC901 pin 30(XTAL2)

Check the USB Power and Data Line. IC901 pin 25 and CN901 pin 1(VBUS) IC901 pin 2, 3 and CN901 pin 3, 2 (D+,D-)

Internal Drive Recognition?

NO Check the CN801(ATAPI Cable) connection. Check the IC101 Reset and Oscillating. IC101(PL2507) pin 38(RESET) IC101 pin 43(XSCO) Check the USB Power and Data Line. IC901 pin 14 and IC101 pin 62(USB-PWR) IC901 pin 5, 6 and IC101 pin 47, 48 (DM,DP)

YES

51

NO Video Capture Device Drive Recognition? Check the Power Supply. IC902(APL5533) pin 1, 4 (2.5V,1.8V)

YES

Check the IC601 Reset and Oscillating. IC601(TVP5150AM1) pin 8(RESET B) IC601 pin 6(XTAL2) Check the IC701 Reset and Oscillating. IC701(EM2860) pin 45(RN) IC701 pin 59(XSCO)

Check the System Clock and Serial Bus. IC701 pin 20(VCLK / 27MHz) IC701 pin 24, 25 (SCL,SDA)

Check the USB Data Line. IC901 pin 8, 9 and IC701 pin 64, 63(DP, DM)

NO Audio Capture Device Drive Recognition? Check the IC401 Reset and Oscillating. IC401(EMP202) pin 11(RESET#) IC401 pin 2(XTL-IN/27MHz) Check the Clock and Data Line. IC701 pin 34(BCLK) IC401 pin 10(SYNC) IC401 pin 5, 8(SDO,SDATA)

YES

NO Movie(Video) Capture Operation?

YES

Check the Analog Video Signal. Composite ( IC301 pin 13 : H ) - IC301 pin 5(Y1) and IC601 pin 2(B) S-Video ( IC301 pin 13 : L ) - IC301 pin 1(Y0) and IC601 pin 2(B) - IC301 pin 12(X0) and IC601 pin 1(A)

Check the Video Data Line. IC601 pin 11~18 (YOUT7~0)

NO Movie(Audio) Capture Operation?

Check the Analog Audio and Data Signal. IC401 pin 23, 24(Audio L,R) IC701 pin 31(SDATA)

52

POWER CODE SECTION

UK (6410HE1201J) America (6410HE1201M)

Australia (6410HE1201N)

Corea (6410HE1201K)

Euro (6410HE1201L)

53

BLOCK DIAGRAM (USB AV CAPTURE & BRIDGE BOARD)

54

CIRCUIT DIAGRAM(USB AV CAPTURE & BRIDGE BOARD)

5

C
55

D
56

E
57

SECTION II DVD MULTI DRIVE ASSY

DISASSEMBLY
1. CABINET and CIRCUIT BOARD DISASSEMBLY
1-1. Bottom Chassis
A. Release 4 screws (A) and remove the Bottom Chassis in the direction of arrow (1). (See Fig.1-1)

1-3. Cabinet and Main Circuit Board

A. Remove the Cabinet in the direction of arrow (4). (See Fig. 1-3) B. When the CD tray has been opened completely, lift 2 points (a) and remove the CD tray while drawing out simultaneously. C. Remove the Soldering of the LD- and LD+ (b) for the Loading Motor, and then remove the Main Circuit Board. D. At this time, be careful not to damage the 5 connectors of the Main Circuit Board.

Cabinet
(1) (a) (4)

(A) Bottom Chassis (A) (A) (A) Fig. 1-1 Main Circuit Board (b) Fig. 1-3 (5)

1-2. Front Bezel Assy

A. Insert and press a rod in the Emergency Eject Hole and then the CD Tray will open in the direction of arrow (2). B. Remove the Tray Door in the direction of arrow (3) by pushing the stoppers forward. C. Release 3 stoppers and remove the Front Bezel Assy.
Tray Door (3)

2. MECHANISM ASSY DISASSEMBLY

2-1. Pick-up Unit
A. Release screws (B). B. Separate the Pick-up Unit in the direction of arrow (6).
(B) (B)

Stoppers

Pick-up Unit (6) (2) CD Tray

Front Bezel Assy

Emergency Eject Hole

Fig. 1-2 Fig. 2-1

Mechanism Assy

62

2-2. Pick-up
A. Release 1 screw (C) and remove the Pick-up.

Pick-up Unit

(C)

Pick-up
Fig. 2-2

63

005

035

004

EXPLODED VIEW

012 008 006

009 010 011

015

4
016

PBM00 (MAIN C.B.A)

A01
3

A03
013

PBF00 (FRONT C.B.A)

453

034 033 031 001 007 025 419 026 027 024

A02
003 002

430 020 430 028 482 452

028

481
030

020

021

032 050 014 453 036 021 452 452

482

482

482

GSA-5168D only

C
64

D
65

1. Data Processing Flow

IC261 DRAM

IC121 RF AMP (AN22113A) CD

SERVO DSP Encoder & Decoder & CSS

IC201 (MN103SA6G)
Command

P-up Unit (LPC-812R)

RF EQ & AGC

TE/CSO GEN

DVD

FE GEN

RF data slice Data PLL Servo ADC Focus/tracking control output Sled control output CAV Spindle control

EFM demodulator CiRC error correction Audio DAC Buffer/Memory controller CSS controller Atapi interface control

Data Status

DVD & CD DATA PROCESSING

SRAM Flash ROM

IC262

68

2. Copy Protection and Regional Code Management Block

Block Diagram

Change the "KEY"

MN103SA6G
Scrambled MPEG Data

HOST DVD PLAYER (EMPEG2 B/D)

KEY Management Control

Brief Process
1. Regional Code for DVD Disc DVD-ROM drive transfers the regional code of the control data to host by the command of host, the DVD player of host reads the regional code, and plays title in the case of allowed regional code only. 2. Management of DVD Disc for the scrambled of data (1) DVD-ROM and DVD player of host generate the KEY 1 respectively, transfer to opposite part, the KEY 2 is received, recognizes the data transfer or not with this value, and generates the bus key encoded the data. (2) Encoded Disc Key and Title Key host is transfer with the bus Key. (3) DVD player of host reads the key value, and uses the value to restore the scrambled data. * Refer to the next page for the details.

69

3. About Prevention the DVD-ROM from to be copy

A data is able to encode and record in the disc, if a copyright holder wants to prevent the disc from copying. In case of a disc enhanced movie of 3 titles...... DISC KEY (2048 Bytes) is used to encode the whole contents in the disc and TITLE KEY (5 Bytes) is used to encode the title respectively. So, the data is encoded and stored in a disc through the unknown algorithms with a disc key and title key. (At this time, the disc key and title key are stored in a disc.) As above, the disc is able to copy when the disc key and title key are opened. Then, ROM-DRIVE encodes the disc key and title key and transfers to MPEG2 board. If you want to play the disc prevented from the copy...... First of all, ROM-DRIVE and MPEG-2 board identify with each other through the procedure as described below.

AGID

HOST

ROM-DRIVE

Challenge key

MPEG-2 BOARD

encoded disc key, title key

1. Drive and host gives and takes the ID of 2bit. This ID is AGID (Authentication Grant ID). The various decoder boards are attached to the host, in these, AGID sets the MPEG-2 board and drive. 2. After the AGID is set, MPEG-2 board generates the challenge key (10 Byte) and transfers to drive. The board and drive generate key 1 (5Byte) with the challenge key respectively. (Of course, the Algorithm generating the key 1 is not known.) 3. Compare with the generated key 1, if it corresponds each other, the first step of authentication is completed. This is a course to identify the MPEG-2 board with a drive. 4. The second step of authentication is a course to identify a drive with the MPEG-2 board. The dirve generates a challenge key and transfers it to the MPEG-2 board. The dirve and MPEG-2 board generate the key 2 (5Byte) with the challenge key, compare with each other, and if it corresponds and the secondary step of authentication is completed. 5. As above, the identification is completed. 6. The dirve and MPEG-2 board generate the Bus key with the key 1 and key 2 and own it. 7. Dirve encodes the disc key and title key with this Bus key and transfers to the MPEG-2 board. 8. The MPEG-2 board reads the encoded disc key and title key with the Bus key only. 9. MPEG-2 board lets data read from the drive to decode with the read disc key and title key and makes into the video signal by decoding.

70

4. About the DVD-ROM Regional Code

Regional code

1
GRL FIN CAN RUS FST LTU BIR POI UKR MNG U.S.A BMG JRN MIX BHS CUB TUR TKM AFG PAK MMR CHN

6 3

KOR

JPN

1
PRI. VIR

FGY

2
HKG TWN MAC PHL PLW PNG MNP GUM

1
MDI

5 4 2
ZAF ISO SWZ

1
AUS

NZL

DISC

ROM - DRIVE

MPEG-2 BOARD

VGA CARD

MONITOR

The disc has the regional code of 8 bit.

Transfer to MPEG-2 board reading the regional code.

If the board is setting to the regional code 1 for the U.S.A. ... Check the received regional code to number 1, all or not, transfer the data to VGA card in accordance with only a case among the three case.

Example) The disc manufactured in the U.S.A, has the number one.

Receiving data from the MPEG-2 board and output through the monitor

71

INTERNAL STRUCTURE OF THE PICK-UP

1. Block Diagram of the PICK-UP(LPC-812R)

7 6 5 4 3 2 1

RFSW EF3 RF+ C EF2 B CXA2694N VC A PD4CI EF1 EF4

8 9 10 11 12 VCC 13 D 14 GND

CW CW

10 9 8 7 6

VREF NC CDO DVDO IN

VCC GND STB SW OUT

1 2 3 4 5 Themester

CP0076AH

13 14 15 16 17 18

ENA OUTB RSA GND RSB OUTA

E3 NE2 E2 ER RFA RFB

6 5 4 3 2 1

Focus

TILT TRACK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

VC(PDIC) VCC(PDIC) GND(PDIC) EF4 EF1 A B EF2 EF3 C D SW(PDIC) RF+ RFSW(FM) VCC(FM) GND(FM) VREF(FM) FM_OUT TEMP GND W1DISN W1DIS W2DISN W2DIS W3DISN W3DIS OSCEN GND GND VCC W3SET W2SET W1SET RSET OUTSET ENABLE VCC GND F+ FTILT+ TILTT+ T-

11 VCC 12
SEL

8 NE4 9 OSC 10
IR I2

VCC

E4

NE3

VCC

I3

I4

24

23 22 21

19
DVD_LD CD_LD

20

Actuator

72

2. Pick up Pin Assignment

No. 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Pin Name TT+ TiltTilt+ FF+ GND(LDD) VCC(LDD) ENABLE OUTSEL RSET W1SET W2SET W3SET VCC(LDD) GND(LDD) GND(LDD) OSCEN W3DIS W3DISN W2DIS W2DISN W1DIS W1DISN GND(FPD) TEMP FPD-OUT VREF(FPD) GND(TEMP) VCC(FPD) SW2(FPD) RFRF+ SW1(PDIC) D C EF3 EF2 B A EF1 EF4 GND(PDIC) VCC(PDIC) VC(PDIC) Signal Description Tracking Actuator drive signalTracking Actuator drive signal+ Tilting Actuator drive signalTilting Actuator drive signal+ Focusing Actuator drive signalFocusing Actuator drive signal+ Ground connection for LDD Power supply for LDD Disables output current regardless of OUTEN(ENABLE Low:No lout) High:selects DVD LD, Low:CD LD Input voltage for current amplifier Input voltage for current amplifier Input voltage for current amplifier Input voltage for current amplifier Power supply for LDD Ground connection for LDD Ground connection for LDD TTL control for Oscillator Enable (High Enable) LVDS control for output current (High Enable) LVDS control for output current (Low Enable) LVDS control for output current (High Enable) LVDS control for output current (Low Enable) LVDS control for output current (High Enable) LVDS control for output current (Low Enable) Ground connection for PDIC, FPD, TEMP Output voltage for controlling temperature APC amplifier output APC amplifier reference voltage output Ground connection for PDIC, FPD, TEMP Power supply for FPD FPD output gain Select (High : CD, Low:DVD) Signal PDIC RF negative differential output Signal PDIC RF positive differential output PDIC output gain Select (L/M/H) Signal PDIC output D Signal PDIC output C Signal PDIC output EF3 Signal PDIC output EF2 Signal PDIC output B Signal PDIC output A Signal PDIC output EF1 Signal PDIC output EF4 Ground connection for PDIC, FPD, TEMP, LDD Power supply for PDIC(+5V) Reference voltage input for PDIC)

73

3. Signal detection of the P/U

Infrared Iaser Pick-Up module Tracking Focusing

Photo Diode

1) Focus Error Signal ==> (A+C)-(B+D) This signal is generated in RF IC (IC121 : AN22113A) and controls the pick-ups up and down to focus on Disc. 2) Tracking Error Signal (DPP Method) ==> {(A+D)-(B+C)}- k x {(EF1+EF4)-(EF2+EF3)} This signal is generated in RF IC (IC121 : AN22113A) and controls the pick-ups left and right shift to find to track on Disc. 3) RF Signal ==> (A+B+C+D) This signal is converted to DATA signal in DSP IC (IC201 : MN103SA6G).

Track Center

Tp/2

Sub1 F,E

Main

D,C A,B

Sub2

H,G

Tp k[(F+H) - (E+G)] Offset (A+D) - (B+C)

TE

(A+D) - (B+C) - k[(F+H) - (E+G)]

74

DESCRIPTION OF CIRCUIT
1. ALPC (Automatic Laser Power Control) Circuit
1-1. Block Diagram

CN 101
Optical Pick-up LPC-812R
VREFPD 124

IC 121
APC
127 FPDM FM 19 123 VPD

AN22113A
Ave S/H2 LPF
VGA

IC 201 MN103SA6G
M P X

S/H3 S/H1
40 41 SH2

Erase Space

A/D

VGA

LD

PD
42 SH1

Write Strategy S/H Signal

LDD D/A D/A D/A D/A D/A D/A Serial I/F

SH3

ADSC

1-2. ALPC (Automatic Laser Power Control) Circuit Operation

The ALPC block detects the laser output power of the front monitor. The power signal detected with the PD for front monitor detection is input the voltage from the VPD pin(123Pin) or the FPDM pin(127Pin), the reference signal of the input signal is input from the VREFPD pin(124Pin). The ALPC block generates the singals from the input laser power signals in the following detection systems. This block has four detection paths:All average value path, multi pulse average/peak value detection path, erase/bottom value detection path, space/playback power value detection path.

75

2. Focus/Tracking/Sled Servo Circuit

2-1. Focus, Tracking & Sled Servo Process
Focus, Tracking, Sled Servo

Pick-up E F B C G H A D
A,B,C,D E,F,G,H A,B,C,D E,F,G,H A,B,C,D

Focus Error Detector

FE

Focus Error Detector

TE

IC121 A N22113A

Tracking Focusing Actuator 53

T-

54
T+

51
F-

52
F+

IC201 Servo Control MN103SA6G

A/D
TE FE

LEVEL SHIFT LEVEL SHIFT

5 4

FDRV

60
TDRV

IC301 BD7956FS
29 30

64

D A C

PARALLEL DIGITAL COMPENSATOR

STEP2

SLED COMPENSATOR A/D

SDRV

Logic

66 67

37 38 40 39 A+ A- B- B+

STEP1

M
Stepping Motor

76

77

MN103SA6G MECHANISM

Need to change to 16bit R On/Off R On/Off Track BD7956 Drive IC Focus OPU

S-DPWM 10bit 100/50 MHz

S-DPWM 10bit 100/50 MHz RFOUT ADC INT 16 bit Timer Circuit AN22113 FEP

PDIC

Internal u-P(F/W)

RXD

2-2. Focus & Tracking Servo Process(using the LightScribe)

HC_CTL

RFOUT

LPF RXD MUX Comparator RFS_iNT RXD/RFS_INT

V ref

3. Spindle Servo Circuit

3-1. Spindle Servo Process

Pick-up E F B C G H Spindle Motor A D RF SRF

IC121 AN22113A
Wobble Signal Generator WBLIN

EFM

IC201 MN103SA6G
SERVO DSP

M
Frequency Controller Level Shift

SPDRV

68 Phase Controller

IC301 BD7956FS

3-2. Spindle Servo

Spindle servo is as following ; 1) Wobble CLV 4x, 10x, 16x, 24x, 32x, 40x : Blank area in CD-R, CD-RW 2) Wobble CLV 1x, 2x, 2.4x, 4x, 8x : Blank area in DVD+/-R/RW 3) CD 15x CAV : Video CD, CD-DA(Audio out) 4) CD 32x CAV : CD-RW, CD-DA(DAE) 5) CD 40x CAV : CD-ROM/R 6) DVD 8x CAV : Single Layer DVD-ROM(Movie), Dual Layer DVD-ROM, DVD+RW, DVD-RW, DVD+R Double Layer 7) DVD 10x CAV : DVD+R, DVD-R 6) DVD 16x CAV : Single layer DVD-ROM(Data) -Spindle Servo is controlled by IC201(MN103SA6G) and servo signal is output via SP-DRV(Pin70).

78

3-3. Spindle Servo Process(using the LightScribe)

MN103SA6G

MECHANISM

BSDA 12bit 100MHz

2 or 3 state

R On/Off

BD7956 Drive IC

Motor

Internal u-P (F/W)

Optical FG INT

69

Optical Encoder

16bit Timer

Pre-scale

X-TAL 16.9344MHz

5V

Enc
FEP

Vcc

TR

Optical Encoder IC

79

MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION

IC121 (AN22113A) : FEP(RF) Analog Signal Processor
Pin Assignment

96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 65 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 NC 46 45 44 43 42 41 40 39 38 37 36 35 34 33

RFN RFP CWBLHPF1 CWBLHPF2 CWAGC1 CWAGC2 CWBLVGA1 CWBLVGA2 CRWCMP CRWAGC AIDENV/WBLDIF CWBLCMP CBPFAGC CLPPHPF CLPPPH RFOUT VCC2 CWBLBUF HDVREF RFIN1 RFIN2 FLTAMP EQOUTP EQOUTN PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0

CDRFP CDRFN CDHPF DLY1 DLY2 GND2 FO1 FO2 TR1 TR2 TR3 TR4 NC NC VCC1 GND6 VREF SVREF VCC3 AIN BIN NC NC EIN FIN NC NC DACOUT VREF08 VPD NC VREFPD

97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

AN22113A
(Top View) 128Pin TQFP TQFP-128-P-1414A

CLUMPGT WBL LPPS ASENV/LPPM GND4 VCC52 RSDAT RSEN SDAT SCK SEN VCC4 SH5 SH1 SH2 SH3 WIDGT/SH4 FEPIDGT/SH6 WTGT GND5 VCC51 BDO OFTR TC STMOUT PIO4 PIO3 PIO2 PIO1 PIO0 PO6

GND3 ROPCIN APCAAF1 APCAAF2 APCAAF3 CPCAPH CPCABH

CBDOF CBDOS CHPOFT COFTR VCC6 VHALF CTC CXDPH1 CXDPH2 SEO1 SEO2 MOUT0 MOUT1 MOUT2 GND1 PO0 PO1 PO2 PO3 PO4 PO5

STMD STMDN

1 2 3 4 5 6 7 NC 8 9 10 NC 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

80

STMD STMDN STMOUT SE01 SE02

TC

SDAAOUT + _ SDABOUT

TEC Block
_ VGA COMP. +

MPX

SLPOS1

Input Block
SMFEP

COMP.

SPLAOUT SDACOUT + SDADOUT _ SPLBOUT VGA

SLP23

PK ENV

SLPOS2

FIN
SMFEPN Operation Circuit SSFEP SSFEPN SMTEP SMTEN SSTEP SSTEN SDAAOUT SDABOUT SDACOUT SDADOUT

EIN TR3 TR4 AIN/TR1 BIN/TR2 HIN/Fo1 GIN/Fo2

CD/DVD Switch S/H & VGA

SLP14

PK ENV

LPF

LPOS Block

MPX
M P X VGA/ Bypass VGA/ Bypass M P X

MPX
SRFMA + SRFMD SRFMB + VGA S/H VGA S/H

TECENV

WBLDIF
VGA AGC/ Bypass AGC/ Bypass VGA

BAL

VGA

WBL Detection

FOCUS PPTE Block

WBL

BAL

MPX Block
SDPDTEP

SRFMC SLP14 SLP23

LPP Detection

WBL/LPP Block
SDPDTEN SPLAOUT SPLBOUT SPOF SSTEP

ASENV/ LPPM

LPPS

DPD TE Dtetction
SRFMA SRFMD SRFMB SRFMC GATE

MPX

SMTEP SMTEN

+ - CHP0FT + COFTR

Amp

COMP.

OFTR

DPD Block
TCOP

SSTEN

VGA

OFTR Block

TC/TI Dtetction TCTI Block

TCON TIOP TION SBDOAS VGA

TCO

MPX
TIO

VREF HDVREF VHALF VREF08

VREF

OPC&ASENV Block
PK ENV MPX VGA LPF Bypass S/H VGA

MPX

MPX

APC Block

To Each Block

VREF Block
SW

GATE Block

COMP.

BDO Block
All Sum

LPF

Lve1 Shift

LPF VGA PK ENV BT ENV Group delay compensation VG A CLMP. Amp EQ 0FST + -

VGA

S/H

LPF/ Bypass

VGA ATT COMP.

S/H

ATT

SEL

VPD

FPDN

VGA

S/H

Block Diagram

RFP CDRFP RFN CDRFN

To Each Block

To Each Block

SDAT

JLINE

To MPX

LOGIC

SCK SEN

RSDAT

RF Gene Block
RF OUT

RFEQ Block
BDO RFIN1 RFIN2

JLINE Block
EQOUTP EQOUTN

LOGIC Block

RSEN

81

 Pin Assignment
Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name GND3 ROPCIN APCAAF1 APCAAF2 APCAAF3 CPCAPH CPCABH NC STMD STMDN N.C CBDOF CBDOS CHPOFT COFTR VCC6 VHALF CTC CXDPH1 CXDPH2 SEO1 SEO2 MOUT0 MOUT1 MOUT2 GND1 PO0 PO1 PO2 PO3 PO4 PO5 PO6 PIO0 PIO1 PIO2 PIO3 PIO4 STMOUT TC Type PS I I I I O O I I I I O I PS O I I I O O I I/O I/O PS O O O O O O O I/O I/O I/O I/O I/O O O Function Ground pin for APC/OPC & ASENV Input pin after OPC addition Capacitor connection pin for APC mark system AAF Capacitor connection pin for APC average DC detection system AAF Capacitor connection pin for APC bottom detection system AAF. External capacitor connection pin for PCA peak hold. External capacitor connection pin for PCA bottom hold. PD input pin for STM PD input pin for STM Capactitor connection pin for BDO detection Fast Peak Env. Capacitor connection pin for BDO detection LPF External capacitor connection pin for OFTR HPF External capacitor connection pin for OFTR Power supply pin for DPD & internal current source power supply pin(3.3V) 1/2 VCC(3.3V) output pin Capacitor connection pin for TE binary floating PH capacitor connection pin 1 for LPOS PH capacitor connection pin 2 for LPOS Output pin 1 after selection of each error signal Output pin 2 after selection of each error signal Analog monitor 0 Analog monitor 1 Analog monitor 2 Ground pin for INPUT MATRIX/SERVO/VREF/DPD CMOS output pin 0 CMOS output pin 1 CMOS output pin 2 CMOS output pin 3 CMOS output pin 4 CMOS output pin 5 CMOS output pin 6 CMOS input pin or output pin 0 CMOS input pin or output pin 1 CMOS input pin or output pin 2 CMOS input pin or output pin 3 CMOS input pin or output pin 4 Encoder circuit comparator output Track cross signal output

82

Pin no. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

Pin Name OFTR BDO VCC51 GND5 WTGT FEPIDGT/SH6 NC WIDGT/SH4 SH3 SH2 SH1 SH5 VCC4 SEN SCK SDAT RSEN RSDAT VCC52 GND4 ASENV/LPPM LPPS WBL CLUMPGT PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 EQOUTN EQOUTP FLTAMP

Type O O PS PS I I I I I I I PS I I I/O I I PS PS O O O I I I I I I I I I O O I

Function OFTR signal output BDO output Power supply pin for CMOS I/F & internal current source power supply pin 1(3.3V) Ground pin for CMOS I/F Light gate signal input (pull-down) CAPA through signal input pin/ servo sampling signal input pin(pull-dowm) VFO through signal input pin ROPC mark detection sampling signal input pin (pull-down) PCA average detection, APC space detection/Playback power detection/ Erase detection sample timing signal input pin(pulldown) PCA peak/bottom detection, APC space detection/Playback power detection/ Erase detection sample timing signal input pin(pulldown) ROPC space detection, APC space detection/Playback power detection sample timing signal input pin(pulldown) Sample-and-hold timing signal input pin of wobble S/H at recording (pull-down) Power supply pin for internal LOGIC(5.0V) Serial enable input (pulldown) Serial clock input (pullup) Serial signal data input Serial enable input for RF (pulldown) Serial signal data input for RF Power supply pin for CMOS I/F & internal current source power supply pin2 (3.3V) Ground pin for internal LOGIC ASENV output/LPP mark output pin LPP space output pin WBL binary output RFAGC input bias circuit clamp setting input pin (pulldown) A/D input pin 0 A/D input pin 1 A/D input pin 2 A/D input pin 3 A/D input pin 4 A/D input pin 5 A/D input pin 6 A/D input pin 7 Equalizer filter ouptut N pin Equalizer filter output P pin FILTER final stage AMP reference voltage stabilization pin

83

Pin no. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115

Pin Name RFIN2 RFIN1 HDVREF CWBLBUF VCC2 RFOUT CLPPPH CLPPHPF CBPFAGC CWBLCMP AIDENV/WBLDIF CRWAGC CRWCMP CWBLVGA2 CWBLVGA1 CWAGC2 CWAGC1 CWBLHPF2 CWBLHPF1 RFP RFN CDRFP CDRFN CDHPF DLY1 DLY2 GND2 FO1/GIN FO2/HIN TR1 TR2 TR3 TR4 N.C N.C. VCC1 GND6 VREF SVREF VCC3

Type I I O I PS O I I I I O I I I I I I I I I I I I I I I PS I I I I I I PS PS O I -

Function RFAGC signal input pin 2 RFAGC signal input pin 1 2.2V reference voltage output pin Capacitor connection pin for WBLDIF Power supply pin for RFGene/RFEQ/WBL/LPP (5.0V) RFGene signal output pin Capacitor connection pin for LPP peak hold Capacitor connection pin for LPPHPF AGC adjustment capacitor connection pin after WBL BPF Floating Capacitor connection pin for VGA before WBL binary ASENV binary output/Differential signal output pin for ADIP detection AGC adjustment capacitor connection pin for +RW Floating Capacitor connection pin for VGA before WBLDIF AGC Floating Capacitor connection pin 2 for VGA before SLR Floating Capacitor connection pin 1 for VGA before SLR AGC adjustment capacitor connection pin 2 for WBL extraction AGC adjustment capacitor connection pin 1 for WBL extraction Capacitor connection pin for N side HPF before WBLAGC Capacitor connection pin for P side HPF before WBLAGC DVD RF differential input + pin DVD RF differential input - pin CD RF differential input + pin CD RF differential input - pin Internal RF additional floating capacitor connection pin Capacitor connection pin 1 for group delay correction Capacitor connection pin 2 for group delay correction Ground pin for RFGene/RFEQ/WBL/LPP DVD focus signal input pin 1/CD sub signal input pin 3 DVD focus signal input pin 2/CD sub signal input pin 4 DVD tracking signal input pin 1 DVD tracking signal input pin 2 DVD tracking signal input pin 3 DVD tracking signal input pin 4 Power supply pin for INPUT MATRIX/SERVO/VREF (5.0V) Ground pin for BG 1.65V reference voltage output pin OEIC signal reference level input pin Power supply pin for APC/OPC&ASENV(5.0V)

84

Pin no. 116 117 118 119 120 121 122 123 124 125 126 127 128

Pin Name AIN BIN N.C. N.C. EIN FIN N.C. N.C. DACOUT VREF08 VPD N.C. VREFPD

Type I I I I O O I I I

Function CD main signal input pin 1 CD main signla input pin 2 CD sub signal input pin 1 CD sub signll input pin 2 Wide Use DAC output pin 0.8V referece Voltage output (for APC) pin DVD front monitor signal input pin (for APC) Front light system reference level input pin

I : Input pin

O: Output pin

I/O : I/O pin

PS : Power supply/Ground pin

N.C: Non Connection

85

IC201 (MN103SA6G) : Encoder, Decoder & DSP Singal Processor

Pin Assigment

BSMD NBSMD PKMD NPKMD PK2MD MPK2MD PK3MD NPK3MD AVDD33D2 LOUT ROUT AVSSD2 RV1 VREFH AVDD33D1 CPOP5 CPOP4 CPOP3 CPOP2 CPOP1 AVSSD1 SE01 SE02 AVSSA AIDENV/WBLDIF AVDD33A REFMDLA REFTOP REFBTM REGDRC EQOUTN EQOUTP AVDD33DRC CDA1 AVSSDRC P02 FMSW/PO3 WTGT WBL FEPIDGT SH5 WIDGT SH3 SH2 SH1 TC CLUMPGT ASENV POLGT LPPS OFTR P04/GENE0/TRCDATA3/EXTRIG2 TGCHG/P05 LSEN

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109

NRST TRCST/P21 TRCCLK/P20 P17/TRCDATA2/EXTRIG1 VDD3 OSC0 OSC1 VSS MSTPOL/TRCDATA1 DASPST/TRCDATA0 SCLOCK SDATA TRYLOAD/P26 NEJECT TX/P16 NCE NOE FDT0 FDT8 FDT1 FDT9 FDT2 FDT10 FDT3 VDD12 FDT11 FDT4 FDT12 FDT5 FDT13 FDT6 FDT14 FDT7 FDT15 FADR16 FADR15 FADR14 FADR13 FADR12 FADR11 VDD3 VSS FADR10 FADR9 NWE FADR20/P25 FADR19/P24 FADR18 FADR17 FADR8 FADR7 FADR6 FADR5 FADR4

MN103SA6G TOP VIEW

FADR3 FADR2 FADR1 MA4 MA3 MA5 MA2 MA6 MA1 MA7 MA0 VDD3 VSS MA8 MA10 MA9 P15/TRCDATA3/EXTR1G2/MBA1 P14/TRCDATA2/EXTR1G1/MA11 MBA0 MCKB MNRAS MCLK MNCAS MDQMU MNWE MDQML VDD3 VDD12 VSS MDQ8 MDQ7 MDQ9 MDQ6 MDQ10 MDQ5 MDQ11 MDQ4 MDQ12 MDQ3 MDQ13 MDQ2 MDQ14 MDQ1 MDQ15 MDQ0 NDASP NCS3FX VDD3 VDD5 VSS NCS1FX DA2 DA0 NPDIAG

LSCK LSDAT LDDENA P06/HFON VSS VDD3 VHALF/PO7 PWM0A PWM0B/P10 PWM1A PWM1B/P11 PWM2A/P27 PWM28/P12/TX PWM3A PWM3B/P15 PWM4 FG SEN SCK

SDAT RSEN RSDAT BDO MASTER/P23 NRESET HDD7 HDD8 HDD6 VSS VDD12 VDD3 HDD9 HDD5 HDD10 HDD4 HDD11 HDD3 HDD12 HDD2 HDD13 VSS VDD3 HDD1 HDD14 HDD0 HDD15 DMARQ WIOWR NIORD IORDY NDMACK INTRQ N10/CS16/P22 DA1

55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108

86

 Block Diagram (SODC:MN103SA6G)

FEP

DRC CD

FMT

ECC

HOST I/F

HOST

LDD ANALOG FEP

SERVO ADSC

CPU

BCU

SDRAM 16 Mbit 64 Mbit

CD REC

16.9MHz PERIPHERAL

32 bit CPU

Falsh ROM 2 Mbyte

87

 Pin Table
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name BSMD NBSMD PKMD NPKMD PK2MD NPK2MD PK3MD NPK3MD AVDD33D2 LOUT ROUT AVSSD2 RV1 VREFH AVDD33D1 CPOP5 CPOP4 CPOP3 CPOP2 CPOP1 AVSSD1 SEO1 SEO2 AVSSA AIDENV WBLDIF AVDD33A REFMDLA REFTOP REFBTM REGDRC EQOUTN EQOUTP I/O O O O O O O O O Power supply O O GND I/O I Power supply I/O I/O I/O I/O I/O GND I I GND I Power supply O O O O I I Connection Target PU PU PU PU PU PU PU PU Power supply Audio AMP Audio AMP GND Res FEP Power supply Cap.Res Cap.Res Cap.Res Cap.Res Cap.Res GND FEP FEP GND FEP Power supply Cap Cap Cap Cap FEP FEP Power supply Cap GND Description BIAS modulation signal differential current output NBIAS modulation signal differential current output PEAK1 modulation signal differential current output NPEAK1 modulation signl differential current output PEAK2 modulation signal differential current ouptut NPEAK2 modulation signal differential current ouptut PEAK3 modulation signal differential current ouptut NPEAK3 modulation signal differential current ouptut Analog VDD(3.3V) for audio Analog audio output (Lch) Analog audio ouput (Rch) Analog Vss for audio Fixed current source for LVDS, WBL, and analog blocks 2.2V reference voltage input WOBBLE analog VDD(3.3V) Filter connection pin for wobble PLL Filter connection pin for wobble PLL Filter connection pin for wobble PLL Filter connection pin for wobble PLL Filter connection pin for wobble PLL WOBBLE analog Vpp Error signal output after selection analog input Error signla output after selection analog input Servo analog-to-digital converter analog Vss TE signal for DVD-RAM ADIP detector signal input Servo analog-to-digital converter analog VDD(3.3V) Analog-to-digital converter reference voltage for ADIP Analog-to-digital converter reference voltage for DRC(TOP) Analog-to-digital converter reference voltage for DRC(BOTTOM) DRC analog-to-digital converter analog VDD(1.2V) RF differential signal (NEG) RF differential signal (POS) DRC analog-to-digital converter analog VDD(3.3V) Smoothing capacitance for DRC-VCO DRC analog Vss CPU external interrupt, general-purpose I/O, laser fault detect signal

AVDD33DRC Power supply CDA1 AVSSDRC PO2 O GND I/O

88

Pin Number 37

Pin Name FMSW PO3

I/O I/O

Connection Target PU

Description Power monitor detector multiplier conversion signal General-purpose I/O

38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

WTGT WBL FEPIDGT SH5 WIDGT SH3 SH2 SH1 TC CLUMPGT ASENV POLGT LPPS OFTR PO4 GENE0 TRCDATA3 EXTRIG2

O I O O O O O O I O I O I I

FEP FEP FEP FEP FEP FEP FEP FEP FEP FEP FEP FEP FEP FEP

Write gate Wobble binary signal CAPA punch out signal, main beam sampling signal Write WOBBLE sample and hold sampling signal VFO punch out signal, ROPC mark detection sampling signal Sample timing signal for PCA mean value detection, APC space detection, read power detection, and erase detection Sample timing signal for PCA peak, bottom detection, APC peak detection, and mean value detection Sample timing signal for ROPC, space detection, APC space detection, and read power detection Track crossing signal input RF AGC bias circuit clamp signal ASENV/LPP mark input CAPA polarity switch signal, sub beam sampling signal LPP space input Off track input CPU external interrupt, general-purpose I/O

I/O

Inner limit switch input Trace data 3 Trigger 2

53

TGCHG P05

I/O

OEIC

Write power switch signal General-purpose I/O

54 55 56 57 58

LSEN LSCK LSDAT LDDENA P06 HFON

O O I/O O I/O

PU PU PU PU -

LDD serial interface enable LDD serial interface clock LDD serial interface data LDD enable signal CPU external interrupt(5V input) General-purpose I/O for external high frequency module(HFM) ON/OFF

59 60 61

VSS VDD3 VHALF P07

GND Power supply I/O

GND Power supply FEP

Digital Vss I/O pad VDD(3.3V) Drive pin central reference voltage input General-purpose I/O

62 63

PWM0A PWMOB P10

O I/O

DRIVER DRIVER

Focus drive differential PWM+ output, focus drive BSDA output Focus drive differential PWM- output General-purpose I/O

89

Pin Number 64 65

Pin Name PWM1A PWM1B P11

I/O O I/O

Connection Target DRIVER DRIVER

Description Focus 2(tilt) drive differential PWM+ output, focus 2 drive BSDA output. Focus 2(tilt) drive differential PWM-output General-purpose I/O

66

PWM2A P27

I/O

DRIVER

Tracking drive differential PWM+ output, tracking drive BSDA output General-purpose I/O Tracking drive differential PWM-output

67

PWM2B P12 TX I/O DRIVER

General-purpose I/O, IEC958-compliant digital output Debugging serial TX

68 69

PWM3A PWM3B P13

O I/O

DRIVER DRIVER

Traverse drive differential PWM+ output, stepper 1 drive output Traverse drive differential PWM- output, stepper 2 drive output General-purpose I/O

70 71 72 73 74 75 76 77 78

PWM4 FG SEN SCK SDAT RSEN RSDAT BDO MASTER P23

O I O O I/O O O I I/O

DRIVER DRIVER FEP FEP FEP FEP FEP FEP HOST

Spindle drive output Spindle FG input(5V input) FEP serial interface enable FEP serial interface clock FEP serial interface data FEP serial interface enable2(RF) FEP serial interface data2(RF) Dropout signal ATAPI master/slave signal General-purpose I/O

79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

NRESET HDD7 HDD8 HDD6 VSS VDD12 VDD3 HDD9 HDD5 HDD10 HDD4 HDD11 HDD3 HDD12 HDD2 HDD13 VSS

I I/O I/O I/O GND Power supply Power supply I/O I/O I/O I/O I/O I/O I/O I/O I/O GND

HOST HOST HOST HOST GND Power supply Power supply HOST HOST HOST HOST HOST HOST HOST HOST HOST GND

ATAPI reset signal ATAPI data I/O ATAPI data I/O ATAPI data I/O Digital Vss Internal logic Vpp(1.2V) I/O pad VDD(3.3V) ATAPI data I/O ATAPI data I/O ATAPI data I/O ATAPI data I/O ATAPI data I/O ATAPI data I/O ATAPI data I/O ATAPI data I/O ATAPI data I/O Digital Vss

90

Pin Number 96 97 98 99 100 101 102 103 104 105 106 107

Pin Name VDD3 HDD1 HDD14 HDD0 HDD15 DMARQ NIOWR NIORD IORDY NDMACK INTRQ NIOCS16 P22

I/O Power supply I/O I/O I/O I/O O I/O I/O O I O I/O

Connection Target Power supply HOST HOST HOST HOST HOST HOST HOST HOST HOST HOST HOST

Description I/O pad VDD(3.3) ATAPI data I/O ATAPI data I/O ATAPI data I/O ATAPI data I/O DMA request to ATAPI host ATAPI host write signal ATAPI host read signal Ready signal to ATAPI host ATAPI host DMA acknowledge signal Interrupt request to ATAPI host ATAPI data bus width select signal General-purpose I/O

108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132

DA1 NPDIAG DA0 DA2 NCS1FX VSS VDD5 VDD3 NCS3FX NDASP MDQ0 MDQ15 MDQ1 MDQ14 MDQ2 MDQ13 MDQ3 MDQ12 MDQ4 MDQ11 MDQ5 MDQ10 MDQ6 MDQ9 MDQ7

I/O I/O I/O I/O I GND Power supply Power supply I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

HOST HOST HOST HOST HOST GND Power supply Power supply HOST HOST SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM

ATAPI host address signal input Diagnostic signal from ATAPI slave to master ATAPI host address signal ATAPI host address signal ATAPI host chip select signal Digital Vss 5V reference power supply I/O pad VDD(3.3V) ATAPI host chip select signal ATAPI drive active slave signal SDRAM data SDRAM data SDRAM data SDRAM data SDRAM data SDRAM data SDRAM data SDRAM data SDRAM data SDRAM data SDRAM data SDRAM data SDRAM data SDRAM data SDRAM data

91

Pin Number 133 134 135 136 137 138 139 140 141 142 143 144

Pin Name MDQ8 VSS VDD12 VDD3 MDQML MNWE MDQMU MNCAS MCLK MNRAS MCKE MBA0 P14

I/O I/O GND Power supply Power supply O O O O I/O O O O

Connection Target SDRAM GND Power supply Power supply SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM

Description SDRAM data Digital Vss Internal logic Vpp(1.2V) I/O pad VDD(3.3V) SDRAM DQML signal SDRAM write enable signal SDRAM DQMU signal SDRAM CAS signal SDRAM clock SDRAM RAS signal SDRAM clock enable signal SDRAM bank switch 0 General-purpose I/O

145

TRCDATA2 EXTRIG1 MA11 P15

I/O

SDRAM

Debugging trace data Trigger SDRAM address General-purpose I/O

146

TRCDATA3 EXTRIG2 MBA1

I/O

SDRAM

Debugging trace data Trigger SDRAM bank switch 1

147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164

MA9 MA10 MA8 VSS VDD3 MA0 MA7 MA1 MA6 MA2 MA5 MA3 MA4 FADR1 FADR2 FADR3 FADR4 FADR5

O O O GND Power supply O O O O O O O O I/O I/O I/O I/O I/O

SDRAM SDRAM SDRAm GND Power supply SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM FLASH FLASH FLASH FLASH FLASH

SDRAM address SDRAM address SDRAM address Digital Vss I/O pad VDD(3.3V) SDRAM address SDRAM address SDRAM address SDRAM address SDRAM address SDRAM address SDRAM address SDRAM address Flash ROM address Flash ROM address Flash ROM address Flash ROM address Flash ROM address

92

Pin Number 165 166 167 168 169 170

Pin Name FADR6 FADR7 FADR8 FADR17 FADR18 FADR19 P24

I/O I/O I/O I/O I/O I/O I/O

Connection Target FLASH FLASH FLASH FLASH FLASH FLASH

Description Flash ROM address Flash ROM address Flash ROM address Flash ROM address Flash ROM address Flash ROM address General-purpose I/O

171

FADR20 P25

I/O

FLASH

Flash ROM address General-purpose I/O

172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200

NWE FADR9 FADR10 VSS VDD3 FADR11 FADR12 FADR13 FADR14 FADR15 FADR16 FDT15 FDT7 FDT14 FDT6 FDT13 FDT5 FDT12 FDT4 FDT11 VDD12 FDT3 FDT10 FDT2 FDT9 FDT1 FDT8 FDT0 NOE

O I/O I/O GND Power supply I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power supply I/O I/O I/O I/O I/O I/O I/O O

FLASH FLASH FLASH GND Power supply FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH Power supply FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH

Flash ROM write enable signal Flash ROM address Flash ROM address Digital Vss I/O pad VDD(3.3V) Flash ROM address Flash ROM address Flash ROM address Flash ROM address Flash ROM address Flash ROM address Flash ROM data Flash ROM data Flash ROM data Flash ROM data Flash ROM data Flash ROM data Flash ROM data Flash ROM data Flash ROM data Internal logic VDD(1.2V) Flash ROM data Flash ROM data Flash ROM data Flash ROM data Flash ROM data Flash ROM data Flash ROM data Flash ROM output enable signal

93

Pin Number 201 202

Pin Name NCE TX P16

I/O O I/O

Connection Target FLASH -

Description Flash ROM chip enable signal IEC958-compliant digital output, debugging serial TX General-purpose I/O

203 204

NEJECT TRYLOAD P26

I/O I/O

Mecha Mecha

Tray eject signal (SODC external interrupt) Tray eject signal (SODC external interrupt) General-purpose I/O

205 206 207

SDATA SCLOCK DASPST TRCDATA0

I/O I/O I/O

Debugger data, DRC monitor 0 Debugger clock, DRC monitor 1 DASP setting Trace data 0

208

MSTPOL TRCDATA1

I/O

MASTER pin polarity switch Trace data 1

209 210 211 212

VSS OSCI OSCO VDD3 P17

GND I O Power supply

GND Xtal Xtal Power supply

Digital Vss Oscilator input (16.9344MHz) Oscilator output I/O pad VDD(3.3V) General-purpose I/O

213

TRCDATA2 EXTRIG1

I/O

Trace data 2 External interrupt

214

TRCCLK P20

I/O

Trace clock General-purpose I/O

215

TRCST P21

I/O

Trace status General-purpose I/O

216

NRST

Reset IC

Reset input (power on reset)

94

IC301 (BD7956FS) : CD-ROM/DVD-ROM 7CH POWER DRIVER

Block Diagram

LDOLDO+ Vcc ACTIN1 ACTIN2 TJMON BTHC SPVM_S PGND1 PGND2 U SPV M 1 V fin PGND3 W SPV M 2 SPRNF HB HU+ HUHV+ HVHW+ HWSPIN DGND

1 2 3

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
fin FG

ACO1+ ACO1ACO2+ ACO2ACO3+ ACO3AVM ACTIN3 LDIN AGND SPCNF FG VC fin SLO1+ SLO1SLO2+ SLO2SLGND CTL2 CTL1 SLRNF2 SLRNF1 SLV DD SLIN2 SLIN1 DVcc

LEVEL SHIFT

LEVEL SHIFT

50k

100k

LEVEL SHIFT

50k

4
100k

5
50k

LEVEL SHIFT

Tjmonitor

6 7 8 9 10 11 12

100k 50k

100k

TSD

13 14 15 16 17 18
HB fin BOTTOM HOLD

PWM

OSC FF FF

PRE LOGIC PRE LOGIC

19 20 21

STBY/ BRAKE CONTROL

35 34 33 32

FG LIMIT LIMIT

Hall matrix

22 23 24 25 26 27

33.6k

31 30 29

Current Limit

33.6k

47k

28

95

 Pin Function
No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Symbol LDOLDO+ Vcc ACTIN1 ACTIN2 TJMON BTHC SPVM-S PGND1 PGND2 U SPVM1 V fin PGND3 W SPVM2 SPRNF HB HU+ HUHV+ HVHW+ HWSPIN DGND Description Loading driver negative output Loading driver positive output BTL pre and Loading power supply Actuator driver 1 input Actuator driver 2 input monitor of chip temperature Capacitor connection terminal for spindle current bottom holding Spindle driver sense power supply Spindle driver power ground 1 Spindle driver power ground 2 Spindle driver output U Spindle driver power supply 1 Spindle driver output V fin Spindle driver power ground 3 Spindle driver output W Spindle driver power supply 2 Spindle driver current sense Hall bias Hall amp.U positive input Hall amp.U negative input Hall amp.V positive input Hall amp.V negative input Hall amp.W positive input Hall amp.W negative input Spindle driver input PWM block pre-ground 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 ACTIN3 LDIN AGND SPCNF FG Vc fin SLO1+ SLO1SLO2+ SLO2SLGND CTL2 CTL1 SLRNF2 SLRNF1 SLVDD SLIN2 SLIN1 DVcc Actuator driver input 3 Loading driver input BTL driver block power ground Spindle driver feedback filter Frequency generator output Reference voltage input fin Sled driver 1 positive output Sled driver 1 negative output Sled driver 2 positive output Sled driver 2 negative output Sled driver power ground Driver logic control 2 input Driver logic control 1 input Sled driver 2 current sense Sled driver 1 current sense Sled driver PowerMOS pre-supply Sled driver 2 input Sled driver 1 input PWM block control power supply No 54 53 52 51 50 49 48 Symbol ACO1+ ACO1ACO2+ ACO2ACO3+ ACO3AVM Description Actuator driver 1 positive output Actuator driver 1 negative output Actuator driver 2 positive output Actuator driver 2 negative output Actuator driver 3 positive output Actuator driver 3 negative output Actuator driver block power supply

96

Input/Output circuit diagram

Three-phase motor driver output
17 12

Spindle driver current detection input

8

Hall bias
28

2k
8

7pF
16 13 11 18

19

12.5k

9 10 15

Hall signal input

28 28 28 3

Splindle driver feedback filter pin

FG signal output
28

20 22 24

28

28

50k

2.5k 5pF

50k

21 23 25

5k

100

113
43

18k

40k

PWM driver output SLED1, 2

32 33

BTL driver output FO, TK

48 48

BTL driver output LD

3 3 3

48

37 39

38 40

49 51 53

50 52 54

45 27 36

45

BTL driver input ACT1,2,3,LD

3 3

PWM driver input SLED1, 2

28 28

PWM driver input Spindle

28

28

4 5 46 47 29

50k

10pP 5pF

5k

30

47k

26

3pF

47k

5k 5pF

Reference voltage input

3

Control signal input

28 28

1k

50k 50k

50k 50k

42

50k

10k

47k

50k

34 35

50k

4ch

2ch

BTHC terminal
1 1

TJ output
6

200k 200
1 20

100

97

TROUBLESHOOTING GUIDE
Reset or Power Check.

Check it after connecting the power cable only on interface cable for NO Reset or Power ON.

Are the pin 44 of CN271+5V, pin41 of CN271+12V respectively after the power cable connecting? YES Does the pin #1 (Reset) of IC271 change 0V to 3.3V at the power supply initial input mode? YES

NO

Check the power(5V/12V) short. Check the PC power cable. Repair the PC power supply.

NO

Check the IC401(3.3V regulator IC). Check the IC201, IC121.

NO Are the X201 oscillating?

Check the X201(16.9MHz). Check the IC201.

YES
<Power> Is the pin 5 of IC401 3.3V?

NO
Check the IC401.

YES
<Reference> 1.65V(VREF) : Check pin113 of IC121? 2.2V(HDVREF): Check pin78 of IC121

NO
Check the IC121.

YES

OK

98

System Check.

Load tray without inserting disc. YES Does Tray operate normally? YES Does Pick-up move to inside? YES Does Pickup lens move up/down? YES Does Laser turn on? YES After eject tray, Insert CD-ROM Disc and check rotation. YES Does Disc rotate continuously and the drive recognize the disc? YES After eject tray, Insert Blank CD-R or RW Disc and check rotation. YES Does Disc rotate continuously and the drive recognize the disc? YES After eject the tray, Insert DVD Disc and check rotation. YES Does Disc rotate continuously and the drive recognize the disc? YES After eject the tray, Insert DVD+R/RW Disc and check rotation. YES Does Disc rotate continuously and the drive recognize the disc? NO Go to :Recognition fail Case4 (Blank DVD+R/RW) NO Go to :Recognition fail Case3 (DVD Disc) NO Go to Recognition fail Case2 (Blank CD-R/RW) NO Go to Recognition fail Case1 (CD-ROM Disc) NO Go to Laser operating is abnormal NO Go to Focus Actuator operating is abnormal NO Go to Sled operating is abnormal NO Go to Tray operating is abnormal

OK

99

Tray operating is abnormal.

Tray open doesnt work.

Is the input voltage 0V at IC201 pin203 when push the EJECT SW? YES

NO

Check the connction of IC201 pin 203. Replace the EJECT SW.

Is there Tray control signal input? (IC301 pin 4) YES Is there Tray drive voltage output? (IC301 pin 1,2) YES

NO

Check the connction of IC201 pin

66.
Replace theIC201. Check the communication line

NO

When CN303 is open, Is there Tray drive signal output?

Replace the IC301.

YES
Check the connctor (CN303).

Drive doesnt work after tray close

YES Is the input voltage 0V at IC201 pin204(/OPENSW) when push the SW1? YES NO

Check the pull-up line(3.2V). Replace SW1.

Is the input voltage 0V at IC201 pin63(/LOADSW) when push the SW1?

NO
Check the pull-up line(3.3V). Replace SW1.

100

Sled operating is abnormal.

Is there Sled control signal output? (IC201 pin 68,69) YES

NO Replace the IC201.

Is there Sled drive voltage input? (IC301 pin 29,30) YES

NO
Check the R316, R317.

Is there Sled drive voltage output? (IC301 pin37,38,39,40) YES

NO

NO Is DRVMUTE2 signal H? (IC301 pin 35) YES

Check the connection of IC121 pin 32.

Replace the IC301.

Replace the IC121.

Is there Sled drive voltage output ? (CN302 pin 1,2,3,4) NO

YES Replace the Sled Motor.

Check the Connection CN302.

101

Spindle operating is abnormal

Is there Spindle control DSP output? (IC201 pin70) YES

NO
Replace the IC201.

Is there Spindle drive voltage output? (IC301 pin 11, 13, 16) YES

NO

Is there FG signal input? (IC201 pin 71)

NO

Check the output of IC301 pin 43. Check the connector CN301. Replace the IC301.

YES OK

Is there Spindle drive voltage output? (IC301 pin 1, 2, 3)

YES
Replace the Spindle Motor.

NO

Check the Connection CN301.

102

Focus Servo is unstable

Is FE signal output normal in Focusing Up/Down? (IC121 pin25*) YES

NO Check Pickup Read Power is 1.3~1.7mW?

NO Replace the Pick up.

Replace the IC121. Is FDRV signal output normal in Focusing Up/Down? (IC201 pin 62) YES Go to Focus Actuator operating is abnormal

NO
Replace the IC201.

* IC121 pin25 is MOUT2(FEP Monitor2). After disc recognition action, Monitor port is off. So, please check FE signal during disc recognition.

Focus Actuator operating is abnormal

Is there Focus Search control signal input? (IC301 pin5) YES

NO

Check the connection of IC201 pin 62. Check the communication line between

IC121 and IC201.

Replace the IC201.

Is there Focus Search drive voltage output? (IC301 pin 51,52) YES

NO

Is DRVMUTE2 signal H? (IC301 pin 35) YES

NO

Check the connection of IC121 pin 32. Replace the IC121.

Check the connection CN101 pin40,41.

Replace the IC301.

Replace the Pick-Up.

103

Track Servo is unstable

Is TE signal output normal in Focusing ON and Tracking OFF? (IC121 pin 24*)

NO

Is PICK UP (E, F, G, H) output normal? (CN101 pin 8, 5, 9, 4)

NO

Check the PICK UP FFC. Replace the PICK UP.

YES YES Replace the IC121.

Is there TDRV signal output in Tracking ON? (IC201 pin66)

NO Replace the IC201.

YES Check the Drive IC(IC301) and P/U referring to Focus Actuator operating is abnormal. * IC121 pin24 is MOUT1(FEP Monitor1). After disc recognition action, Monitor port is off. So, please check TE signal during disc recognition.

104

Recognition Fail Case 1: CD-ROM Fail

Check Pickup Read Power was 1.3 ~1.7mW? YES

NO Go to LD CHECK.

Does Focus Servo operate normally? YES

NO Go to Focus Servo is unstable.

Check Pickup RF signal IC121(Pin81) RFOUT was 2~2.5V?

NO

Check the Pick-up FFC and CN101. Replace the Pick-up.

YES

Check EQOUTP waveform (IC121 Pin 74) was 1.75~2.3V? YES

NO

Replace IC121.

NO Check after replacing IC201. It is OK? YES

Go to Tracking Servo is unstable.

OK

Recognition Fail Case2 : Blank CD-R/RW

YES Is there WBL (IC121 pin63) signal? NO Is there WBL (IC201 pin39) signal? NO Check the connection between IC201 and IC121.

YES Replace the IC201.

Replace IC121.

105

Recognition Fail Case 3 : DVD Disc

NO Check Pick-up Read Power was 1.1~1.3mW. YES Go to LD CHECK.

NO Is there RF signal at IC121 Pin81? YES Is there RF signal at IC121 Pin95(RFP) and Pin96 (RFN)? YES NO Check again after the replace IC121 It is OK? YES OK Replace the IC201. NO Replace the IC121. Replace the Pickup.

Recognition Fail Case 4 : Blank DVD+R/RW

Is there WBL (IC121 pin63) Signal?

YES

Is there WBL (IC201 pin39) Signal? NO

YES Replace IC201.

NO Replace IC121.

Check the connection between IC121 and IC201.

106

In case of writing fail.

Normal Case

Check the Media CD-R or CD-RW or DVD+R or DVD+RW? YES

NO Check disc Label.

Does the disc have any Dust, Scratch, Fingerprint...?

NO

Remove the Dust, Fingerprint and if the disc has long width Scratch, change it.

YES Is the write Tool(version) supported by LG DVD+RW Drive? NO

Use LG bundle Software (Write Tool & Version)

YES Check disc information on Writng Tool. [If you get some data information with Non Recordable Disc Message, the disc is finalized -Finalized Disc : unrecordable Disc any more]

NO Finalized Disc? YES If CD-R disc, use new CD-R disc. If CD-RW disc, erase the disc. If DVD+R disc, use new DVD+R disc. If DVD+RW disc, erase the disc. Go to Writing Part Check Eject Disc.

107

No audio output

Insert the audio Disc.

AUDMUTE : L? (IC121 Pin 33) YES

NO

Check and replace the IC121.

Audio Play : AUDMUTE H.

DSP ROUT,LOUT signals output? (IC201 Pin 10, 11)

NO

Check and replace the IC201.

YES Do audio Line signals output? (CN271 pin 51, 54) NO

Check the connection of L/R OUT.

Normal

108

LS Media Recognition Fail: LS CD, DVD

NO Check the Cleanness of Media. Change the Media.

YES NO Check Encoder IC Power.

Check 3pin FFC and Q501.

YES NO Check the OFG Signal. Check Enc Assys Alignment and Grease on it.

YES Check P/U Read Power 4.5~5.5mW. NO Go to LD CHECK.

YES

Check the RXD/RFS_INT Signal On Recognizing LS Media..

NO Replace IC501, 502.

OK

109

 How to use Test Tool (Dragon)

A. Start
1. Install GWA-4164B > PC Power ON > Execute Windows. 2. Execute Dragon_JW3.exe on Windows (Dragon_JW3.exe & Dragon.cfg should be on same Directory). 3. If you use GWA-4164B, Dragon(2005/04/08, 14:00) will be displayed on the window Frame. 4. Select I/F Setup on the menu bar. 5. Select ATAPI I/F and then Click OK. 6. Select Target Device on the menu bar. 7. Select DVDRRW GWA-4164B on Target Device, and then Click OK.

[Target Device window]

[I/F Setup Menu]

110

B. Check ALPC Parameters

1. Select About on the menu bar. 2. Click Addition Func. on About window -> New frame will be displayed. 3. Click ALPC Para tab and verify the specification. [ALPC Parameters] 1) CD VRDC 2) CD VWDC_NMP 3) CD VWDC_MP 4) CD VWDC_ERASE 5) DVD VRDC 6) DVD VWDC_NMP 7) DVD VWDC_MP 8) DVD VWDC_ERASE 9) H.C. VWDC 10) Default ALPC Para. used 4. Close window.

: 117~153 : 100~135 : 100~137 : 105~135 : 115~157 : 100~135 : 100~135 : 105~140 : 100~150 : 0xFF

[Additional Function Menu]

[ALPC Parameters Menu]

111

C. Laser Power Setup

1. Remove disc on the tray. 2. Select ALPC/OPC on the menu bar, and then select Setup Laser Power(Manual) menu. 3. First, select CD and setup wave length of LD Power meter (780nm) (Wave Length : CD(780nm), DVD(660nm), Measure Range : 0.01mW unit). 4. Click VRDC button on the Laser Power Setup window. Laser beam will be emitted from LD. 5. Measure LD Power with LD Power meter. Type the result in the blank(Read Power box). ex) 1.44mW -> 144, 0.99mW -> 99) 6. Click NMP button and measure LD Power with Power meter. Type the result in the blank(R NMP Power box). ex) 16.45mW -> 1645, 12.08mW -> 1208 7. Click MP button and measure LD Power with Power meter. Type the result in the blank(RW Erase Power box). 8. Click ERASE button and measure LD Power with Power meter. Type the result in the blank(RW Erase Power box). 9. Click LD Off button and then click Setup button, and result witll be displayed with OK or NG. 10. Select HC_CD and then click HC button. 11. Measure LD Power with Power meter. Type the result in the blank (HC Power). 12. Click LD Off button and then click Setup button, and result will be displayed with OK or NG. 13. Select DVD and change wave length of LD Power meter (660nm). 14. Follow above step 5, 6, 7, 8, 9. 15. Close Laser Power Setup window.

[Laser Power Setup window]

[Laser Power Setup Frame]

112

[CD Laser Power Setup Result]

[HC_CD Laser Power Setup Result]

[DVD Laser Power Setup Result]

113

Power Supply System Diagram

12V_source

Drive IC (spindle, sled, load) power

BD7956FS

5V_source

Drive IC (Actuator)
BD7956

Reset IC (IC271)
BD5233

RF IC (IC121)
AN22113A

DSP IC (IC201)
MN103SA6G

Pick-up
LPC-812R

IC401 3.3/1.2V-Reg
BA3259

3.3V

RF IC (IC121)
AN22113A

DSP IC (IC201)
MN103SA6G

SDRAM (IC261)
M12L16161A

IC101
AT22138A

Flash Memory (IC262)

MX29LV160BBTC

1.3V Pick-up
LPC-812R

EEPROM (IC201)
MN103SA6G

114

SODC(DSP) (MN103SA6G)
Disc

Spindle motor LDD ALPC I/V AMP Spindle Driver Disc Sled motor RF EQ & GCC Wobble Gain/S/H Matrix OPC/ROPC

FEP(RF) (AN22113A)

Write Strategy LVDS Serial I/F Servo ADSC MPX Serial I/F ADC

Host I/F

Host PC & Authoring Tool

32bit CPU FMT ECC Servo DRC

BCU

JLINE FCS/TRK/TILT Sled Driver PWM BSDA

1M bit DRAM

Buffer RAM

BLOCK DIAGRAM

-Controller

115

SDRAM 16/64Mb

EEPROM 4KByte
ADIP ADIP AD CD DRC AD SRAM CIRC DA VCO

RV7 FEP AN22113A

STM Block TEC Block LPOS Block MPX Block WBL/LPP Block

FORMATTER

ECG

HOST I/F

ENC

ATAPI I/F

Spindle motor (LG-inotec) P-up (LPC-812R) DAC Sled motor (Mabuchi) WS

GATE Block To each Block TCTI Block OPC & ASENV Block BDO Block RFEQ Block RF Gene Block VREF Block DPD Block

Input FOCUS Block PPTE Block

DEC

MPEG I/F

CD PRE

ANALOG A/D

SERVO DSP ADSC

32bit

BCU

DMA

AM

OFTR Block

host
CD REC

APC Block

PERIPHERAL AUTH INTC TMR

KCGEN

SYSIF

WDT

MODEC

Built-in System Controller JLINE LOGIC Block Block

serial

32Bit CPU 16.9344MH

1chip(7ch) Motor drive (TBD) serial

RV7 MN103SA6G
serial

Flash ROM

Regulator 3.3v/1.3V

Regulator 12V

Power block

116