Microprocessor Systems (LAB): SESSION 98/99 jmps to user defined interrupt service rountines.

8028H EX2 TF2 LJMP EX2TF2? Revectored Interrupt Addresses 8100H 8020H ES 8018H TF1 8010H EX1 8000H EX0 LJMP URT_ISR LJMP TF1_ISR LJMP EX1ISR LJMP EX0ISR Keil C Int Nos 5 4 3 2 1 0

8052 Interrupt Vector Structure CODE FFFFH XDATA

code & xdata overlaid by oring/PSEN and /RD

8000H 7FFFH

002BH EX2TF2 LJMP 8028H 0030H 0000H Interrupt Vector Addresses with ISR stimulus. 0023H ES 001BH TF1 0013H EX1 000BH TF0 0003H EX0 0000H RESET LJMP 8020H LJMP 8018H LJMP 8010H Reserved LJMP 8000H

Interrupts , Keil C and the Flight 32 (The Story)! The 8052 has 7 sources of interrupts including the reset vector. The manner in which the Keil C compiler handles both interrupts and the placement of the ISR routines is described in the following text. The method presented here is slightly different and more complicated to that used when developing code for a normal development board, i.e. with no mirrored memory spaces, which is unlike that in the Flight 32 development system. Full details of the 8051s interrupt structure can be found in the 80C51 family hardware description handout pages 63 through 68. The diagram above shows the standard external code and xdata memory spaces. The Interrupt vector addresses reside in the low memory addresses of the code space. Keil C implements the use of the ISR by the use of the keyword interrupt <nos> after the ISR function declaration; void serial_uart(void)/*interrupt 4;optional in prototype*/. KEIL C AND INTERRUPTS 1 AW98/99Ver1

Microprocessor Systems (LAB): SESSION 98/99 The interrupt keyword tells the compiler that this is a ISR routine, so that it automatically generates code to push and pop various registers at the start and finish of the ISR function. Additionally the function end brace } ,produces a RETI instruction rather than a RET instruction. The number after the interrupt keyword specifies which interrupt vector this ISR function is written for, the compiler therefore knows at which standard address to locate the ISR function code. The ISR vectors are in eprom and cannot be modified by the user programs. To allow access to several of the ISRs the eprom contain Long jumps to addresses in the upper half of memory which is RAM, we can therefore use these re-vectored ISRs within our own programs. Our programs must therefore locate the appropriate ISR code at the new ISR vector address. The Keil C compiler authors are aware that the ISR addresses may be revectored and have provided a switch to inform the compiler that the ISRs start at a non standard addresses.This is done by using the following line :#pragma INTVECTOR(0x8000h) This informs the compiler the start address of the ISRs is at 8000H rather than 0h, the compiler will therefore generate the normal interrupt spacings from this address using the following formula (Interval * n) + 3 where the Interval is normal 8 n refers to the interrupt number. This is fine and dandy ,but the revectored ISRs are not to the standard addresses i.e. 03H is revectored to 8000H rather than 8003H. Therefore the result is that in order to use these ISR vectors as is , the have #pragma INTVECTOR value must be changed to a new start address i.e. 3 minus 8000H = 7FFDH #pragma INTVECTOR(0x7FFD) by including this line in our program we can know utilise all the revectored interrupts. For further explanation of the memory system is below.

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Microprocessor Systems (LAB): SESSION 98/99 //C Serial Interrupt Example Program #pragma SRC #pragma LARGE #pragma INTVECTOR(0x7FFD) #include <reg52.h> void Serial_ISR(void); data unsigned char out_data; void main(void) { SP=0x5f; TMOD=0x20; //timer 1 8 bit auto reload mode 2 TH1 = 0xE8; //reload value for baud rate 1200 TR1=1; //timer1 start SCON=0x42; //uart 8 bit variable baud TI is set out_data=0x20; //initialise data to space character EA=1; //enable global interrupt ES=1; //enable serial interrupt executes ISR //since TI=1 set previously. for(;;); //continuous loop } void Serial_ISR(void) interrupt 4 { if(0x7f == out_data) //test if 128 ascii reached out_data = 0x20; //reset to space SBUF = out_data; //send data to serial port out_data++; //next ascii character to send TI=0; //reset TI flag } Compile the program in the normal way and then download hex file to Flight 32 system. We can now exploit the full power of the 8051s integrated peripherals counter /timer , external interrupts and uart. The design of the software is eased with the use of the Keil C compiler.

Further explaination Since this system is for development of user programs, it would be rather tedious and long winded to have to program a EPROM for every new program that was written. To provide the user with a readily available environment for software development and program execution, the designers have overlaid the top half of the code and KEIL C AND INTERRUPTS 3 AW98/99Ver1

Microprocessor Systems (LAB): SESSION 98/99 xdata space. This is done by decoding a RAM in the top half of the memory space and allowing either a processor code read cycle, via the /PSEN control line or a data read cycle via the /RD control line to select the RAM. The data write control line is also connected to the RAM , and can write data to the RAM. The advantage of this systems is that programs can be loaded into RAM using the monitor load function i.e. data writes, and then can executed out of RAM by accessing using the /PSEN. All programs normally execute out of the code space. The microcontroller thinks it is executing out of code space because it is executing a read code cycle using the /PSEN control line. The /PSEN line is actually Ored with the /RD line,the output of which output enables the RAM,therefore the /PSEN control line accesses the RAM data space and uses its contents as code instructions!.Neat!

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