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Interrupts There are two kinds of interrupts software and hardware.

. The hardware interrupt is known as interrupt request or IRQ while the software interrupt is a trap or exception. Hardware interrupts were introduced to reduce time spent in polling loops by the processor. Polling refers to the situation where the CPU continuously polls the process to check readiness without moving onto other programs. Busy-waiting is a form of polling where the process continuously keeps checking whether a certain condition is true keeping the CPU busy in an antipattern (useless activity). However, polling can be a valid strategy to implement spinlocks within operating system designed to run on SMP architecture. Spinlocks are implementations where a thread repeatedly spins around a lock with the intent of acquiring it while repeatedly checking if it is available. Usually, once acquired spinlocks are designed to be held until explicitly released. It has much less overhead than re-scheduling and context switching but is used only when a thread is expected to hold the lock for a very small period of time. This is because the longer a thread holds a lock the more likely it becomes for the thread to be de-scheduled by the CPU. In a situation where a few equal priority threads are looking to acquire the lock de-scheduling the lock holding thread would mean that every subsequent process will waste its quantum spinning around the lock till the original thread is scheduled once again and the lock is released. This is because the lock has to be explicitly released by the thread. Spinlock implementations are generally possible only through the use of special assembly language instructions like atomic-test-and-set operations. For high level implementations, non-atomic locking like Petersons algorithm can be used. Hardware interrupts can either be implemented using hardware control lines or they may be integrated with the memory system. If implemented in hardware there is a hardware interrupt controller, like IBMs Programmable Interrupt Controller (PIC), that multiplexes the interrupts into the available CPU lines, which are typically 1 or 2. As part of the memory system they can be mapped to the systems memory address space by the memory controller. Interrupts

Maskable Interrupts or IRQ

Non-Maskable Interrupt (NMI)

Inter-Processor Interrupt

Software Interrupt

Spurious Interrupt

Maskable interrupt can be ignored by setting a bit in the Interrupt Mask Register (IMR). As the name suggests, NMIs can never be ignored since they dont have an associated IMR. Inter-processor interrupts (IPI) is a special case where one processor interrupts another in a multiprocessor system. IPIs are typically used to implement cache coherency synchronization. IPI signaling is often performed through the use of the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which therefore issues a corresponding interrupt to its own CPU. IPIs are commonly used to maintain Cache coherence. The software interrupt is generated by the CPU itself in response to some illegal instruction. It is commonly used in generating system calls since software interrupts result in a subroutine call that changes into the CPU ring level. Spurious interrupts are unwanted as they are generated by electrical interference or faulty design. In general processors have an internal interrupt mask which is generally faster than setting the IMR in a PIC or disabling interrupt in the devices. In x86, enabling and disabling masks acts as a memory barrier and may be much slower. Memory barrier or member or memory fence or fence instruction is a type of barrier instruction that causes the CPU or the compiler to enforce a constraint on memory operations before and after the instruction. This means that some instructions must be carried out before the barrier and others after the barrier. Memory barriers are necessary because most modern CPUs employ performance optimizations that can result in out-of-order execution. A precise interrupt is one that leaves the machine in a known state. The criteria are: 1. The Program Counter (PC) is saved to a known place. 2. All instructions in the PC before the one being pointed at are completely executed. 3. The ones after the one being pointed at are not been executed (if there were changes made before the interrupt due to any of those instructions then they would be undone). 4. The execution state of the process currently being at is completely known. If any of these conditions are not satisfied then it is an imprecise interrupt.