An Efficient Non-Enumerative Method to Estimate Path Delay Fault Coverage

Irith Pomeranz and Sudhakar M. Reddy Electrical and Computer Engineering Department University of Iowa Iowa City, IA 52242
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Abstract
A method t o estimate the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results are presented to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage. Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths.

1. Introduction
Two common fault models were proposed for defects that change the timing behavior of a circuit, the gate delay fault model and the path delay fault model [l-61. Both models have received wide attention in terms of test generation, fault simulation and synthesis-for-testabilityprocedures. While the number of gate delay faults in a circuit is linear in the number of lines in the circuit, the number of path delay faults is, in the worst case, exponential in the number of lines. In most practical cases, the number of paths in a circuit is very large, making it impossible to enumerate all paths for the purposes of test generation and fault simulation. To overcome this problem, some methods consider only subsets of paths, e.g., only the longest paths are considered in [3,6]. However, even the number of longest paths can be very large, e.g., for optimized circuits, paths tend to have the same propagation delays [7]. In this work, we propose a method to estimate the number of path delay faults detected by a given test set, without enumerating the paths (neither the complete set of paths nor the detected paths are enumerated), in time which is polynomial in the size of the circuit. The problem of handling large numbers of paths (e.g., using the complete set of paths as in [2] or storing the detected paths as in [SI)is thus alleviated. The computed estimate is pessimistic, i.e., the true fault coverage is not smaller than the estimated one. As the order of the complexity polynomial is increased, better estimates are obtained. In the limit, if the degree of the polynomial is allowed to be of the
+ Research suppoltcd i n p t t by NSF G r a n t No. Mip-9109568 (re) and the SDIO/IST Contract No. NOOO14-90-J-1793 managed by US Office of Naval Research (SMR).

order of number of lines in the circuit instead of being a constant, thus resulting in exponential complexity, the exact number of path delay faults detected is obtained. We show experimentally that a very good estimate of the number of path delay faults detected is obtained even for the first-order approximation, in which the degree of the polynomial is two. It thus becomes practically possible to consider large numbers of path delay faults during fault simulation, without enumerating them. This also allows consideration of a large number of path delay faults during test generation, again, without enumerating paths. Combming this non-enumerative estimation method with a method to generate small test sets for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths. The paper is organized as follows. Section 2 provides an overview of the method proposed. In Section 3 we show how the number of paths can be computed in linear time, by making one backward pass over the circuit. In Section 4 we show how the number of path delay faults detected by a test pattern can be determined, without enumerating the paths, again, in linear time. In Section 5 we show how fault simulation with fault dropping can be performed, to estimate the total number of path delay faults detected by a given test set. Several orders of approximation are shown, having increasing polynomial complexity and increasing accuracy. Experimental results are presented in Section 6 to demonstrate the applicability of the method and its accuracy. Section 7 concludes the paper.

2. Overview
For path delay faults, determining the fault coverage achieved by a given test set requires two parameters to be computed The first parameter is the total number of faults in the set of target faults, NF.The second parameter that needs to be determined i s the number of target faults detected by the test set, ND.We give a method to determine NF accurately for path delay faults using a procedure that is linear in the size of the network. We also present procedures to estimate ND,with complexity that is polynomial in the size of the circuit. The number of path delay faults considered in this work, NF,is equal to twice the number of (physical) paths in the circuit-under-test, corresponding to slow

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(or defective) propagation of a falling or rising transition along circuit paths. NF. and consequently N,, may be exponential in the size of the circuit, nevertheless, they are computed or estimated in polynomial time. Three properties are used to allow the fault coverage of path delay faults to be estimated without enumeratingpaths. (1) The number of paths in the circuit can be computed in time which is linear in the number of lines in the circuit, by making one backward pass over the circuit (from outputs to inputs), as shown in Section 3 (2) Considering a single test pattern, one forwurd pass of fault free logic simulation (from inputs to outputs) is required to determine which lines in the circuit belong to paths whose delay faults are covered by the test (without determining, or enumerating, the paths), as noted in [2]. This property is used in [5] to trace, or enumerate, the paths detected by a given test pattern. In the method proposed here, using the algorithm developed for (1) above, the number of paths defined by this subset of lines can be determined in linear time without enumerating the paths. The number of paths computed equals the number of path delay faults covered by the test. Enumeration of paths is thus avoided. (3) Considering an arbitrary test pattern in the test set, some of the faults detected by the test are also detected by tests preceding it in the test set. Only new faults, detected for the first time by the test pattern considered, should be counted for the purposes of computing the fault coverage. For this purpose, circuit lines, which are not included in path delay faults detected by earlier tests, are determined. These circuit lines are called new lines.New lines are logical lines, i.e., with each physical line we associate a rising or falling transition, that has not been included in any previously detected path delay fault that assigns a signaltransition to the line. The number of new path delay faults detected by the test pattern considered can be pessimistically estimated by counting the number of path delay faults that are detected by the test, such that each path delay fault counted includes at least one new line. The procedure developed based on (1) above can be extended for this purpose. The estimated number of faults can then be added to the number of faults detected earlier, to obtain an estimate of the fault coverage. The estimate computed based on the above properties may be lower than the actual fault coverage, due to the use of Property 3. While a new path delay fault may be detected without using any new lines, i.e., lines and transitions that were not included in any previously detected path delay fault, we require the existence of such a line to allow polynomial time computations. To improve the bound, we implicitly partition the set of paths into subsets, using a cut through the circuit, such that every path passes through exactly one line of the cut. Such a cut can easily be found. Every line in the cut defines a subset of paths that pass through it, and new l i e s are defined with respect to each subset separately. As a result, a line that is not new with respect to one subset may be useful in increasing the fault coverage estimate due to another subset, if it is new in that subset. As

the number of cuts used is increased, a better estimate of the number of faults detected is obtained, at the same time increasing the complexity of the estimation procedure,as shown in Section 5. It is important to note, however, that the estimate is always pessimistic. i.e., the estimated fault coverage is always lower than the actual fault coverage. Throughout this paper, when we say polynomial complexity, we refer to time complexity which is polynomial in the number of lines in the circuit. Robust tests [ 1,4] are considered in this work, but extensions to non-robust tests can be easily incorporated.

3. Computing the number of paths

In this section, we give a procedure to determine the number of paths in a circuit in time linear in the size of the circuit. This procedure appears in [lo], and is included here for completeness. The basic idea is described next and illustrated by Figure 1. In Figure 1, line numbers are given in square brackets. Note that fanout stems and their branches are given different numbers, e.g., line 9 is a fanout stem with branches 10 and 11. Consider a gate G with inputs i,,i,, * * . ,ik and output i. Let N,(i) be the number of paths from line i to the primary outputs, e.g., in Figure 1, the number of paths from line 12 to the primary outputs is Np(12)=2, where the paths are 12-13-16 and 12-14-17. The ,ik, number of paths from each one of the inputs of G, i , . i z , to the primary outputs is also Np(i), as follows. For every path p from i to a primary output there is also a path ij-p from ij to the same primary output, where ij is followed by the path p. No other paths exist from ij to a primary output. For example, the number of paths from line 10 to the primary outputs, N,(lO), is the same as Np(12), or 2. For a fanout stem i with branches i, ,i2, . . .,ik, given the number of paths, Np(ij), from fanout stem ij to the primary outputs, the number of paths from i to the

---

primary outputs is

j=l

wp(ij), as follows. For every path p from a

fanout branch ij to a primary output, there is a path i-p from i to the same primary output, and no other paths exist from i. For a primary output i, Np(i)= 1. Starting from the primary outputs, we can thus compute the number of paths from every line to the primary outputs, without enumerating paths, as illustrated by the following example. ,%-ample: ISCAS-85 benchmark circuit c 17 is given in Figure 1. The circuit has 11 paths, listed in Table 1 as sequences of line numbers. To compute the number of paths, we assign every primary output the label 1. Lines 16 and 17 in Figure 1 are thus labeled by 1. We assign the inputs of every gate, whose output is labeled, the label of the output. We thus assign lines 8, 13, 1, 4, 14, 15,7, 11 the label 1. When a fanout stem is encountered, it is given a label which is the sum of the labels on its fanout branches. Line 12 is thus assigned the label 2. Continuing by these rules, we assign lines 2 and 10 the label 2, line 9 the label 3, lines 5 and 6 the label 3 and finally, line 3 is assigned the label 4. A l l labels are shown in Figure 1. We now sum the labels on all primary inputs. This number, 11 in this case, is equal to the number of paths in the circuit. 0 The general algorithm for computing the number of paths in the circuits is the following. We assume that topological sort

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6

6 7

Table 1: The paths of c 1 7 8 1 6 12 1 3 1 6 12 14 1 7 4 8 1 6 5 9 1 0 12 13 1 6 5 9 11 15 1 7 5 9 10 12 14 1 7 9 10 1 2 1 3 1 6 9 10 1 2 14 17 9 11 1 5 17 1 5 1 7

(or BFS [8]) has been used to number the lines in the circuit such that if there is a path from line li to line lj, then i < j . We denote the number of lines in the circuit by L.
Procedure 1: Computing the number of paths . Set i = L. (1) Assign all the primary outputs the label 1 (2) If line i is the output of a gate and the label of line i is Np(i),label all the inputs of gate i by Np(i). (3) If line i is a fanout stem with branches i l . i 2 , . - . , i k , label? Np(i,),Np(i2), .* ,Np(ik), respectively, label line

value "1x0 ("0x1") stands for a 1+0 (0+1) transition. "OOO" ("1 11")stands for a stable 0 (1) under the two patterns. The circuit line numbers are shown in square brackets (e.g., "[ 1 1 " ) . as in in Figure 2 Figure 1. The numbers in parenthesis (e.g., "(1)") indicate which input signal-transitions robustly propagate to the output of a gate, as follows. For signal-transitions on pimary inputs, the number in parenthesis is the primary input number. l signal-transition on line 6 is robustly propagated to The b line 9 when line 5 is held at stable 1. Therefore, line 9 has the number 6 in parenthesis. The signal-transition on line 9 robustly 1 .The latter therefore propagates to its fanout branches 10 and 1 have line 9 in parenthesis. Similarly, since the O+l signaltransitions on lines 7 and 11 robustly propagate to line 15, line 15 is marked by ( 7 . 11 ) .0 We denote the sets of lines to which transitions are . by R ( i ) . robustly propagated, given in parenthesis in Figure 2 The definition of R ( i ) is clarified by the following procedure for computing the sets R (i).

i by W p C i j ) .
j=1

Set i = i-1. If i > 0, go to Step ( 2 ) . The number of paths in the circuit is x ( N p ( i ) : iis U primory input). It can be shown by induction on the number of lines in the circuit that for every line I , the label computed by algorithm 1 is equal to the number of paths starting from I and ending at a primary output. In particular, the number of paths starting from the primary inputs can be computed as in Step ( 5 ) of the algorithm. The proof is omitted as it follows from the discussion above. We can thus compute the number of paths in the circuit using Procedure 1. The number of path delay faults is twice the number of physical paths. For every path, there are two path 1 transition on the input of delay faults, one associated with a b the path (called the slow-lo-rise fault) and one associated with a 1 4 transition on the input of the path (called the slow-lofull fault).

(4) (5)

4. Computing the number of path delay faults detected by a test pattern

In this section, we consider the problem of computing the number of path delay faults detected by a given two-pattern test, without enumerating the tested paths. Only robust tests are considered. Tests for path delay faults are comprised of two input patterns, applied consecutively.The first pattern is applied to set the required initial conditions in the circuit. All signal-transitionsin the circuit are allowed to settle under the first pattern. The second pattern is then applied to activate a path delay fault and brig its effect to a primary output. The following example illustrates a two-pattern test for path delay faults. ExMlple: The values in c 1 7 under the two-pattern test (1,2,3,6,7) = < (l,O,l,l,O), (O,O,l,O,l) > are given in Figure 2. A

Procedure 2: Computing the sets R ( i ) (1) Set R ( i )= I$for every line i. Set i = 1. (2) If line i is a primary input canying a signal-transition ( k l (0xl)or 14(lxO), s e t R ( i ) = ( i ) . (3) If line i is the output of a gate G, then for every input ij of G such that R ( i j ) # 4 and the signal-transition on ij robustly propagates to i, set R ( i ) = R ( i ) u ( i j l . (4) If line i is a fanout branch of fanout stem k and if R (k)# 4, set R ( i )= ( k ). (5) Set i = i + l . If i S L , go to Step (2)(L is the number of lines in the circuit). Only primary inputs carrying signal-transitions are initially assigned a non-empty set R ( i ) . Every other non-empty set R ( i ) results from a nonempty set R (j) on a line j directly driving line i (i can be the output of a gate of which j is an input, or j can be a fanout stem with a branch i). Therefore, R ( i ) # $ implies that there is a path from a primary input to line i, on which signal-transitionsare robustly propagated. The sets ( R ( i ) ] thus define a subcircuit such that every line in the subcircuit belongs to a path from the inputs on which a signal-transition robustly propagates. To find the fault coverage of the test, we need to find the number of paths in this subcircuit, that end at , there are three such primary outputs. For example, in Figure 2 6-9-11-15-17 and 7-15-17. For every such path, paths, 1-8-16, there is a path delay fault that is detected by the test. Procedure 1 can be modified to compute the number of paths in the subcircuit defined by the condition R ( i ) # 4. The following procedure can be used to obtain the required number of paths. Procedure 3: Computing the fault coverage of a given test Set N J i ) = 0 for every line i. (1) (2) Assign primary output i the label N J i ) = 1 if R ( i )# 4. Set i = L. (3) If line i is the output of a gate and the label of line i is N , ( i ) > O , label every input ij of gate i, such that R (ij) f $, by NJi). If line i is a fanout stem with branches i l , i z , * . ,ik, (4) labeled Np(i,),Np(i2), * * * ,Np(ik), respectively, and if

562

R ( i ) # 4. label line i by pp(ij).

j=l

Set i = i-1. If i > 0 ,go to Step (3). The number of path delay faults detected is x { N p ( i ) : iis U primary input). ErMlple: The labeling of c 17 by Procedure 3 for the test shown in Figure 2 is given in Figure 3. In Figure 3, the numbers in square brackets are line numbers and the number on each line is its label N,(i) assigned by Procedure 3. The sets R ( i ) are taken from Figure 2. Summing the labels on all primary inputs, we obtain the number of paths detected by the given test. In the case of this example, three path delay faults are tested, namely, the slow-to-fall fault on paths 1-8-16 and 6-9-11-15-17 and the slow-to-risefault on path 7-15-17.0 For the sake of lucidity, Procedure 2 was given separate from logic simulation. However, Procedure 2 can be combined with fault free logic simulation, to obtain the R sets as the fault free values are being computed. A single forward pass over the circuit can thus yield the fault free values and the R sets. (5) (6)

5. Estimating the fault coverage of a given test set

In the previous section, we showed how the fault coverage of a given two-pattern test can be computed. To estimate the fault coverage of a test set, we need to compute the number of new path delay faults detected by every test, i.e., the number of path delay faults not detected by any previous test in the test set. Fault coverage computationfor a test set is the subject of this section. To ensure that only new path delay faults are counted when a test pattern is applied, we require that a t least one line, that was not included in any previously tested path, would be included in every path counted. Since every line can be assigned one of two transitions, 0+1 or 1 4 , and since different path delay faults require the transition O+l and the transition 1 4 on a given line, we refine this requirement, and require that at least one line that was not included in any previously tested path with the transition assigned to it by the test under consideration, would be included in every path counted. Such lines are referred to as new lines. Consider the following example. Example: Consider the two-input test pattern (1,2,3,6,7) = e (O,O,l,l,O), (O,O,O,l,l) > applied to c 17 after the pattern shown in Figure 2 has already been applied (we assume that no fault has been detected by any other test applied after the test of Figure 2 was applied). The values robustly propagated through the circuit are given in Figure 4 together with the sets { R ( i ) ) (the other labels in Figure 4 will be explained subsequently). The slow-torise fault on path 7-15-17 is detected by both tests, the one of Figure 2 and the one of Figure 4. To avoid counting this fault twice, we require that the lines used for counting the number of path delay faults detected by the test of Figure 4 would drive or be driven by new lines. For the test of Figure 2, the following lines were included in the count of the number of paths (and hence cannot be used as new lines for the test of Figure 4): 0+1 transitions were used on lines (7,8,9,11,17); l-+O transitions were used on lines { 1,6,15,16]. Therefore, for the test in Figure 4, we have new (robust) 1 4 transitions on lines 3, 4 and 5 (only). For the purpose of counting the number of new faults, we require that every path counted would go through at least one

new line, contained in the set (3.45). 0 To achieve the goal of counting every fault detected only once, we modify Procedure 1, that computes the number of paths in a circuit, as follows. Instead of a single label, we associate with each line two labels. Both labels count the number of paths starting from the line and ending at the primary outputs, passing only through lines j with R 0) z 0. The 6rst label, denotedN,,(i), counts the number of paths fiom line i as above, with the additional requirement that every path would pass through at least one new line. The second label, denoted No(i), counts the number of paths with the additional requirement that they pass through no new lines. Each of the labels is manipulated separately, using the rules given in Procedure 1. However, when a new line is encountered, its two labels are fist computed separately and then, since every one of the paths counted from this line to the primary outputs passes through a new line (the one being labeled), its second label is zeroed and its first label is set to the sum of the two labels. A labeling of c 17 is given in Figure 4 and explained in the following example. We use the notation (N,,(i),No(i))for the labels computed. ExMlple : The labeling of c 17 for the test of Figure 4 is given in the figure. For the sake of clarity of the figure, we use L1 for label (0.1) and L p for label (1,O). The (0,O)labels are omitted. The labels are computed as follows. Primary output 17, that has a nonempty set R (i). is labeled L, (i.e. (0.1)). The other pri0 , O ) . The labels are propagated mary output, 16, is labeled ( through the preceding gates, until line 5 is reached. Line 5 carries the label (0.1) when it is reached. Since it is a new line, its label is changed into (1,O). Labeling continues until all lines are labeled. It can be seen that line 7 is assigned the label (0.1) at the end, implying that no new fault is detected, that starts on line 7. Only one new fault, the slow-to-fall fault on path 3-5-9-11-1517, which starts from the new line 3, is counted. 0 In general, new lines are used to compute the additional number of faults covered by a test, to eventually compute the fault coverage, as follows. The lines that can potentially be new lines are maintained as the set GPne,.Initially, G- contains all circuit leads with rising and falling transitions separately identified. For every new test, fault simulation and Procedure 2 are first applied to compute the R sets. The set of new lines that may contribute new path delay faults to the fault coverage estimate are the members of Gpmr that have signal-transitionsunder the test considered. Let this set of (new) lines be G,, = (g1,g2. . . , g k ) (in the previous example, G,, = { 3,4,5)). The number of paths is then computed, that go through lines with non-empty R ( i ) sets, using Procedure 4. Procedure 4 is similar to Procedure 1, except that two labels are associated with each line, instead of the single label N p ( i ) in Procedure 1. The labels are denoted (N,,(i),No(i)).
9

Procedure 4 Computing the number of new faults detected (1) Assign every primary output i such that R ( i ) # I$the label 4 0 ) . (0.1). Assign all other primary outputs the label ( Set i = L. (2) If line i is a new line labeled (Nn(i),No(i)),change its label into (Nn(i)+No(i),O).

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(3)

If line i is the output of a gate and the label of line i is

(Nm(i),No(i)), label all the inputs ij of gate i. such that R ( i j ) # 4, by (Nn(i),No(i)). Label all other inputs of the

(3)

gate by (0,O). If line i is a fanout stem with branches i l , i 2 , labeled

W n ( i )*No(i~ ~ ))*(Nn(i2)A'o(i2))9 . * * v(yn(ik)-No(ik))v

respectively, label line i by ( p , , ( i j ) , p o ( i j ) ) .

j=l

j=I

(4)

(5)

Set i = i-1. If i > 0, go to Step (2). The number of new path delay faults detected is
x ( N n ( i ) : iis aprimaty input).

To complete the procedure for computing the fault cover, , , is updated. Once age by a set of tests, we show next how G hocedure 4 is performed, we remove from G , , , , all the new , defined above) that were lines (these are members of G assigned non-zeroN, labels by Procedure 4. It is important to note that new path delay faults can be covered by a test even when no new lines exist that cany new transitions under the test considered. Therefore, the fault coverage estimate is a pessimistic one. We refer to the approximation described above as the 0-order upproximdon. To increase the quality of the fault coverage estimate based on new lines, we next propose to divide the circuit into subcircuits, such that each subcircuit has a unique set of paths contained in it. We then consider new lines with respect to each subcircuit separately, to increase the accuracy of the estimate, as follows. We find a cut through the circuit, such that every path from inputs to outputs passes through exactly one line in the cut. h t C = (cI.c2, -*-,ck besuchacut ] Asimple waytoselectc is to select all primary inputs or all primary outputs. In our experiments,the cut that includes primary inputs or all the fanout branches of a primary input when the primary input is a fanout stem and the cut that includes the inputs of all gates whose outputs are primary outputs were considered, and the larger of the two was used. Consider the following example. Exumple: For c 17, C, = (1,2,3,6,7] is a cut such that every path from inputs to outputs passes through exactly one line in C,, since Cl includes all primary inputs. C2 = (16,171 is another such cut, since it includes all primary outputs. We can increase the size of C , by replacing input 3 by its fanout branches, to obtain C3 = (1,2,4,5,6,7]. Similarly, we can increase the size of C2 by replacing each primary output by the inputs of the gate directly driving it, to obtain C, = (8,13,14,15). The advantages of selecting a larger cut will become clear later. The cut C 5 = (1,4,9] is not suitable, since there is a path from input 7 to output 17 that does not pass through this cut. 0 We use the cut C to divide the circuit into subciicuits, each one containing a disjoint set of paths, as follows. For every ci E C, we define a subcircuit that includes every line g such that there is a path in the circuit from g to ci or from ci to g. The following example illustrates this division. Exumple: Consider c 17 and the cut C = (1,2,4,5,6,7). The subcircuit for line 1 includes the lines [ 1,8,16]; the subcircuit for line 2 includes the lines (2,12,13,14,16,17]; the subcircuit for line 4 includes the lines (3,4,8,16); the subcircuit for line 5 includes the lines [ 3,5,9.10,11,12,13,14,15,16,17 1; the subcircuit

for line 6 includes the lines (6,9,10,11,12,13,14,15,16,17); the subcircuit for line 7 includes the lines (7.15.17). Each one of these subcircuits contains a unique set of paths from inputs to outputs, none of which is included in any other subcircuit. 0 Since every subcircuit contains a unique line ci of the cut C, every path in that subcircuit must pass through ci. The sets of paths contained in different subcircuits are therefore disjoint, and for computing the fault coverage of a test, we can count the number of new path delay faults detected in each subcircuit separately and then add the numbers. For every subcircuit separately, we record all the lines and transitions used in the fault coverage estimate for previous tests. A line that is not new in the subcircuit of a line c , E C may thus be new in the subciicuit of a line c2 E C,and may still be useful in improving the fault coverage estimate. This method is referred to as the Zsforder approximufion, since the division of the circuit into subcircuits is determined by a single cut. Comparing the lst-order approximation to the O-order approximation, where all previously used lines and signaltransitions are recorded together, the 1st-order estimate is higher and more accurate. Comparing the complexity of the two approaches, the number of computations required by the O-order approximation is approximately multiplied by the size of the cut in the case of the lst-order approximation (similar computations are performed for each subcircuit, however, they are performed for IC I subcircuits in the case of the 1st-order approximation, instead of a single one in the case of the O-order approximation). It is possible to further improve the accuracy of the estimate by considering two cuts instead of one, to obtain a 2ndorder upproximufion. For two cuts C I and C2. I C I I I C2 I subcircuits are considered each one with its own set of new lines. The kth-order approximation uses k cuts, and its complexity is 0 (Lk+') per test, where L is the number of lines in the circuit. This can be seen as follows. For every test and every subcircuit, the additional fault coverage is computed by performing a constant number of passes over the circuit (two passes: one for logic simulation and computing the sets R ( i ) and the other for assigning the N,, and No labels and computing the number of new path delay faults detected). The complexity of each pass is O(L). The size of every cut is also 0 (L). Therefore the number of subThe total complexity follows. circuits is 0 (Lk). Using the procedures above, it is also possible to restrict the computation to longest paths only. For that purpose, we label each line by its maximum distance (in lines or in gate delays) from the primary inputs. A single forward pass allows such a labeling, as follows. Denoting the maximum distance of line i from the primary inputs by d ( i ) , if line i is an output of a gate with inputs i , , * * ,ik, and assuming that the distances of i , , . * * ,it are known, the distance of line i is computed as m.ax(d(ij)]+l. Gate delays can also be accommodated by using
'I

m,ax(d(ij))+A(i), where A(i) is the delay of the gate. For a

I,

fanout stem i with branches i l , * * .ij, the branches are labeled by d(i)+A(i), where again, A(i) depends on the delay model (A(i) may be zero if the delay of a line is neglected). For the primary inputs, d ( i ) = 0. The d labels can thus be computed by a single forward pass, using the rules above. Once the d labels are

564

1 -

computed, a single backward pass can be used to mark all the lines contributing to longest paths, as follows. All primary outputs are marked. Input ij of a gate with output i is marked if d ( i ) = d(ij)+A(i), i.e., i j determined the maximum distance for line i. Similarly, fanout stems are marked. The procedures developed above for estimating the fault coverage are then applied only to the lines marked, belonging to longest paths. For a given test set, the fault coverage estimate obtained by the procedure proposed may depend on the order in which the tests are processed. Here, we do not refer to test ordering that changes the actual fault coverage of the test set. Rather, test ordering is used to improve only the fault coverage estimate. This is possible by regarding the test set as comprised of nonoverlapping two-pattern tests, i.e., for a test set T = ( f l , t 2 ,* . ,tt), where ti is a single input pattern, the two* * * . In pattern tests considered are cfl,f2>,cf2,f3>,cf3,f4>, order to take advantage of this observation, the following property of the proposed estimation procedure is used to obtain an easy-to-implementheuristic to determine the order of processing of tests. Using the procedure proposed here, the estimated fault coverage of a single two-pattern test, or of the first test that detects any fault in a test set, is accurate. Based on this observation, it is possible to increase the accuracy of the fault coverage estimate using the following scheme. First, the fault coverage of every test is obtained separately, using the 0-order approximation. The tests are then ordered by decreasing numbers of faults detected, and the fault coverage estimate for the test set is evaluated. More new lines are thus available when the tests that detect higher numbers of faults are evaluated, potentially increasing the fault coverage estimate. Preliminary results of the effect of test ordering are reported in the following section. Test ordering using higher order approximations is expected to further improve the accuracy of the estimates, and is currently under investigation. Note that the test ordering is used only for the purposes of improving the accuracy of the fault coverage estimate, and the test application order to the circuit-under-testis not changed.

Similar results were obtained when a deterministic test set, that detects all path delay faults, was used, as reported in [9]. Results for ISCAS-85 benchmark circuits are given in Table 3. Except for c880, we include results only for circuits that have very large numbers of paths. Results for fully scanned ISCAS-89 circuits are given in Table 4. To obtain the accurate results, we used a fault simulator that enumerates only the paths detected. Note that 1024 random patterns may be too few to detect any significant number of path delay faults (even stuck-at faults require larger numbers of random. patterns), however, this number is large enough to show the applicability of the estimate, that does not require path enumeration. For ISCAS-85 circuits we also give results for the case where the tests were reordered to improve the fault coverage estimate. Test ordering was performed using the O-order approximation to compute the fault coverage of every test separately, and the tests were then ordered by decreasing numbers of detected faults. The fault coverage estimate was then computed for the ordered test set using the 0order approximation. The complete set of results for the case of test reordering can be found in [9]. Table 2: Random patterns for Berkeley PLAs cut size, detected circuit Z9sym add6 adr4 alul
alu2

0 flts -

1st 77 47 27 28 19 233 162 76 160 169 0 122 83 0 253 141 66 140 164 130 115 153

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6. Experimental results
We applied the method proposed in this work to estimating the fault coverage in several sets of circuits. The results are reported in this section. We first applied the method to multi-level versions of Berkeley PLA benchmark circuits. The PLA benchmark circuits were synthesized using MIS-II to obtain multi-level implementations. 1024 random two-pattern tests were applied to each circuit and the fault coverage was estimated. Results are given in Table 2. Column "flts" of Table 2 gives the number of path delay faults in the circuit. The results of the 0-, 1st- and 2nd-order approximations are given next. For every approximation (except for the 0-order approximation), the size of the cut(s) used is given, followed by the number of path delay faults detected by 1024 random patterns. Also included in Table 2 is the number of paths detected using accurate fault simulation. It can be seen that while the O-order approximation sometimes gives results which are far from the accurate results, the first order approximation deviates from the accurate results by less than 1% on the average. The second order approximationgives accurate results.

al3 co 14 dk17 dk27 dk48 mish radd rckl rd53 vg2 xldn x9dn

24

498 210 76 260 282 144 340 128 572 280 170 476 154 492 440 612 190

19 157 108 76 141 142 0 108 62 0 228 89 58 115 94 87 84 102

4 4
49 46 40 23

50
114 26 123 29 65 68

58
28

2nd 77,4 47,15 27,ll 28,21 44,22 49,18 46,2 40.24 23.21 46,50 114,75 26,lO 123,15 29,8 65.12 68,9 58,ll 28.9

19 233 163 76 160 171 0 122 83 0 255 145 66 140 168 131 117 153

acc -

19 233 163 76 160 171 0 122 83 0 255 145 66 140 168 131 117 153

Table 3: Random patterns for ISCAS-85

reordered

Since in the ISCAS-85, ISCAS-89 and Berkeley PLA benchmark circuits, the number of path delay faults detected by random patterns is relatively low, we constructed a set of circuits that have large numbers of detectable path delay faults, to demonstrate the effectiveness of the procedure proposed in such a case. The circuits have the structure shown in Figure 5. The block in the dashed box is repeated different numbers of times, to obtain circuits of different sizes. In circuit C,, the block is

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Table 4: Random patterns for ISCAS-89 cut size, detected circuit s27 s208 s298 s344 s349 ,9386 inp 7 19 17 24 24 13 24 35 24 25 24 54 54 23 23 45 32 32 91 14 14 215 247 out 4 10 20 26 26 13 27 18 27 13 27 43 42 24 24 29 31 31 79 25 lines 26 208 298

7. Concluding remarks
A method to estimate the coverage of path delay faults of a given test set, without enumerating paths, was proposed. The method was based on properties, that allow the number of path delay faults detected by a test to be computed in linear time. An approximation was required to estimate the fault coverage of a test set comprised of more than one test. Several levels of approximation, with increasing accuracy and increasing complexity, were proposed In all cases, the method was polynomial in the number of lines in the circuit, and thus allows circuits with exorbitant numbers of paths to be considered under the path delay fault model. Experimental results were presented to show the effectiveness of the estimate in accurately evaluating the path delay fault coverage. We are currently investigating methods to improve the estimates, in particular, through the use of test ordering, as well as methods to employ the ideas presented here for test pattern generation. References S . M. Reddy, M. K. Reddy and V. D. Agrawal, "Robust Tests for Stuck-Open Faults in CMOS Combinational Logic Circuits", in Proc. Int. Symp. on Fault-Tolerant Computing, Florida, pp. 44-49, June 1984. G. L. Smith, "Model for delay faults based upon paths,'' in Proc. Int. Test Conf., pp. 342-349, Nov. 1985. C. J. Lin and S . M. Reddy, "On delay fault testing in logic circuits," IEEE Trans. CAD, pp. 694-703, Sept. 1987. E. S.Park and M. R. Mercer, "Robust and nonrobust tests for path delay faults in a combinational logic," in Proc. Int. Test Conf., pp. 1027-1034, Sept. 1987. M. H. Schultz, F. Fink and K. Fuchs, "Parallel Pattern Fault Simulation of Path Delay Faults", in Proc. Design Autom. Conf., pp. 357-363, June 1989. M. H. Schultz. K. Fuchs and F. Fink, "Advanced Automatic Test Pattern Generation Techniques for Path Delay Faults", in Roc. Int. Symp. on Fault-Tolerant Computing, pp. 44-51, June 1989. T. W. Williams, B. Underwood and M. R. Mercer, "The Interdependence between Delay-Optimization of Synthesized Networks and Testing", in Roc. 28th Design Automation Conf.. June 1991, pp. 87-92. S . Even, Graph Algorithms, Computer Science Press, 1979. I. Pomeranz and S. M. Reddy, "An Efficient NonEnumerative Method to Estimate the Path Delay Fault Coverage in Combinational Circuits", technical report No. 10-1-1991 Revised 7-11-1992, Electrical & Computer Eng. Dept., U. of Iowa I. Pomeranz, L. N. Reddy and S . M. Reddy, "SPADES: A Simulator for Path Delay Faults in Sequential Circuits", to appear in EURO-DAC '92, Sept. 1992.

344
349 386 400 420

s400
s420

s444
s5 10 626 s641 s713 s820 s832 s953 sl196 s1238 s1423 s1488 s1494 6378 s9234

444
510 526

640

713 820 832 953 1196 1238 1423 1488 25 1494 228 5295 250 9234

0 56 33 290 111 462 259 710 230 730 231 414 180 896 276 738 163 1070 274 738 337 820 366 3488 351 43624 261 984 341 1012 338 2266 398 6194 461 7116 478 89452 891 1924 600 1952 602 27084 2022 489708 1386

flts

1st acc 7 44 44 54 138 138 85 271 271 45 351 352 46 351 352 75 180 180 89 317 317 102 211 21 1 90 319 319 91 448 448 140 377 377 54 498 506 59 337 350 282 341 34 1 288 338 338 115 575 575 201 554 554 222 577 577 255 1186 1222 281 649 649 283 651 65 1 335 2319 2377 644 1582 1585

repeated n times (C,is given in Figure 5). Denoting the number of paths in Ci by N,(Ci), the number of paths in C, can be computed by the recursive equation N,(C,,) = N,(C,,-, ).2+2. The equation is obtained as follows. There are two ways to continue each path of Cn-, in C,,: through the "upper" branch or through the "lower" branch of the non-primary input of block n. In addition, there are two paths from the primary inputs in the n-th block to its output. Using N,(C,)=4, we obtain N,(C,,) = 3*2"-2. The procedure proposed was applied to a test set that detects all slow-to-fall path delay faults in the circuit. As many faults as possible were detected by every test, e.g., the test (1,4,6,11,13, = (1x0, 111, 111, 111, 111, 111, 111, 111, 111, ) detects all slow-to-fall delay faults on paths that start !?om input 1 (input numbers correspond to Figure 5). Experimental results for several C, circuits are given in Table 5 . The number of blocks is given first, followed by the number of tests applied and the total number of path delay faults and the number of path delay faults detected. Time is given in the last column (time is measured in seconds on a SUN SPARC 2 Workstation). Floating-point numbers of double-accuracy had to be used to count the number of paths and the number of path delay faults detected.
* . a )

Table 5: Results for the circuit of Figure 5 blk tsts faults detected 20 41 6.29 1,452 3,145,726 30 61 6,442,450,940 3,221,225;470 40 81 6,597,069,766,652 3,298,534,883,326 50 101 6,755,399,441,055,740 3,377,699,720,527,870 time 0.50 1.11 1.84 2.70

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.
[4] 111

* -

J U

Figure 1: Circuit c 17

[16] 1x0(8)
[3] 111

PI
[5] 111 [61 1x0(6) I101 0x1 (9) [910xl (51, [1110x1(9)D [710xl(7)

(121 111 171Ox1 (15) (151 lxO(7,

Figure 2: A test pattern for circuit c 17

I

. a

Figure 3: The number of paths for the test pattern of Figure 2

__
r - - - - - - - - - - -

. _

Figure 4 Computing the fault coverage for circuit c 17 (L, (O,l), L2 (1,O))
I

r-----------i

Figure 5: An example of an exponential number of detectable paths

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