IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO.

11, NOVEMBER 2009

3019

A 2.4-GHz Resistive Feedback LNA in 0.13-m CMOS

Sanghoon Joo, Student Member, IEEE, Tae-Young Choi, Member, IEEE, and Byunghoo Jung, Member, IEEE
AbstractA -boosted resistive feedback low-noise amplier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of -boosting as in inductively degenerated topology. The gain of the LNA increases by the -factor of the series RLC input network, and its noise gure (NF) is reduced by -boosting property, the proa similar factor. By exploiting the posed fully integrated LNA achieves a noise gure of 2.0 dB, S21 of 24 dB, and IIP3 of 11 dBm while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 mm2 in 0.13- m CMOS, which provides the best gure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB. Index Terms -boosted LNA, low-noise amplier (LNA), noise gure, resistive feedback, voltage gain boosting.

Fig. 1. Input matching network. (a) Parallel RLC. (b) Series RLC.

I. INTRODUCTION HE demand for a low-cost, high performance wireless front-end system and aggressive device scaling has triggered intensive research on CMOS radio-frequency (RF) front-end circuits. The ever increasing demands for high performance, low-cost, and constantly operating mobile devices have encouraged researchers to explore the edge of state-of-the-art radio-frequency integrated circuits (RFIC) and pursue the contradictional goal of high performance with low-power consumption. In addition to low-power, as the rst active block in the receiver chain, the performance of an LNA dictates the overall noise performance of receivers, thus various CMOS LNA topologies have been studied [1][6]. Popular LNA topologies are the inductively degenerated common-source LNA (L-CSLNA) [1], [2], the common-gate LNA (CGLNA) [3], and the resistive feedback LNA (RFLNA) [4]. Each topology has distinct advantages and limitations. To overcome the limitations and exploit the merits of each topology, many combined architectures have been investigated. For example, the L-CSLNA has been combined with an LC ladder lter or a resistive feedback scheme to achieve broadband input matching [7][11], and the CGLNA has been merged with a common source scheme to cancel noise of an input device [12][20].

This paper proposes a new low-power LNA scheme which -boosting from inductively degencombines the merits of erated topology and input impedance matching from resistive feedback topology. Section II begins with input matching networks of LNAs and compares the pros and cons of conventional topologies. Section III describes the concept of the proposed LNA, performs a small-signal noise analysis including the drain channel noise and the induced gate noise, and compares its noise performance with the traditional architectures. The implementation and experimental results of the LNA are presented in Sections IV and V, respectively. The paper concludes in Section VI. II. CONVENTIONAL LNA TOPOLOGIES The rst active front-end RF block, which is an LNA, needs to match its input impedance to an external component such as an antenna, a band select lter, or an RF switch. This matching network can be a parallel or series resonator as shown in Fig. 1. Typically, the shunt RLC easily achieves impedance matching, but it does not have any voltage gain across the ca, which is usually a gate-source capacitor , pacitor i.e., . For the LNAs with the shunt RLC matching network, a gain boosting block in front of a main stage is observed in [3], [21], [22]. They utilize capacitive coupling or a transformer as a gain booster, which increases the voltage across the gate and source of an input device and reduces the noise gure by increasing the effective transconductance. The voltage gain stage using passive devices prior to an active device should add very little noise and amplify the RF signal before the signal is corrupted by noise from active devices. It is also possible to match the input impedance using a series times of voltage gain RLC network which could generate across [1]. At a resonant frequency , the quality factor and the voltage across is given by is . Therefore, the inductively degenerated common source topology with a series RLC input network can take advantage of the increased effective transconductance of an input device to reduce the noise gure.

Manuscript received April 13, 2009; revised July 17, 2009. Current version published October 23, 2009. This paper was approved by Associate Editor Jan Craninckx. This work was supported in part by the Electronics and Telecommunications Research Institute. The authors are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA (e-mail: sjoo@purdue.edu; taeyoung@purdue.edu; jungb@purdue.edu). Digital Object Identier 10.1109/JSSC.2009.2031912

0018-9200/$26.00 2009 IEEE

3020

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 11, NOVEMBER 2009

Fig. 2. Conventional LNA topologies. (a) Inductively degenerated common-source LNA (L-CSLNA), v v ,F = g R . (c) Common-gate LNA (CGLNA), v Resistive-feedback LNA (RFLNA), v CGLNA [21], v nk v , F = = nk .

= 0 (1 + )

= 1+[ ( )] = 1 + ( )[1 (1 + )]

= 0jQ v = 0v

,F ,F

= 1 + [ =(Q g = 1 + [ =()]. (d) g

R . (b) -boosted

)]

The shunt RLC conguration has been frequently employed in the RFLNA [Fig. 2(b)] and CGLNA [Fig. 2(c)], while the series RLC has been used in the L-CSLNA [Fig. 2(a)]. The L-CSLNA is the dominating topology for narrowband systems due to its advantages such as low NF, ease of input matching, high gain, and low-power consumption. However, these benets come at the cost of large chip area due to the two inductors; one at the gate and another one at the source of the input device. For those inductors to resonate at low operating frequencies, impractically large inductance values would be required. This can be avoided by using an extra capacitor between the gate and source of the transistor, but this topology reduces the gain and degrades NF [23]. The RFLNA [Fig. 2(b)] provides wideband input and output matching and small die area because no inductor is required for input matching. However it has a poor NF and consumes a large amount of power. When the is increased to reduce the NF, it requires a shunt size of inductor to improve input matching. The CGLNA [Fig. 2(c)] can also provide wideband input matching, but suffers from poor noise performance compared with the L-CSLNA when is considerably lower than the the operating frequency [3]. Matching unity gain frequency to the source the input impedance of the CGLNA impedance limits the choice of power consumption and device size. Narrowband matching can be improved by adding a shunt inductor that resonates with the parasitic shunt capacitor of -boosted CGLNA shown in Fig. 2(d) the input device. A has been proposed to remedy the high NF issue, but still has theoretically higher NF than L-CSLNA at practical operating frequencies [21]. It is worthwhile to emphasize that the input of an L-CSLNA forms a series RLC network, whereas that of a CGLNA forms a parallel RLC network. In addition, the voltage across the capacitor of an L-CSLNA corresponds to ( , where is the source resistance) times the input voltage at the resonance frequency due to the series RLC matching network which is the key for its high gain and low NF. III. PROPOSED LNA ARCHITECTURE To take advantage of voltage gain boosting in LNA design, the proposed LNA merges a series RLC input matching network with a resistive feedback topology.

Fig. 3. Proposed LNA architecture.

Fig. 4. Equivalent input matching network of the proposed LNA.

A. Principle of Operation Fig. 3 shows the schematic of the proposed LNA. The goal is to adopt the advantages of L-CSLNA and RFLNA. Its equivalent circuit for input matching analysis is shown in Fig. 4. Since the original resistive feedback LNA has a parallel input network, the input network can be simplied to the left gure of Fig. 4. If the frequency band of interest is relatively narrow, a parallel-to-series impedance conversion can be applied to the input matching network. To use series matching for the resistive feedback topology, the input is converted into a series netimpedance at the gate of work, as shown in the right gure of Fig. 4, using series and , where is , is

JOO et al.: A 2.4-GHz RESISTIVE FEEDBACK LNA IN 0.13- m CMOS

3021

Fig. 5. Small-signal model of the g -boosted resistive feedback LNA for noise analysis.

, is the impedance at the operating frequency, and of the output load is for the frequency band of interest. The impedance can be easily matched to the source by setto the source impedance , and adding a series inting at the operating frequency. The ductor that resonates with by series matching topology boosts the voltage at the gate of , and hence the effective transconductance is boosted . Theoretically, the proposed LNA can achieve by a higher voltage gain compared to an inductively degenerated . A small-signal analysis LNA by a factor of of the input impedance shows that

and resonate at the frequency of inimpedance when terest. The noise factor of the proposed topology is

(2) where is the ratio between the device transconductance and the zero-bias drain conductance, is the factor of channel thermal noise, is the factor of induced gate noise, and is the correlation coefcient between the induced gate noise and , , the drain noise. For long channel devices, , and [1], [25]. In (2), there are three main noise contribution terms originating from the active device. The fourth term comes from the drain current noise and the fth represents the correlated portion of the drain current noise and the induced gate noise. The last term is the contribution of the uncorrelated induced gate noise. The relation that equals for the narrowband LNA in Fig. 3 under the input matching condition can be ap, it can be assumed that plied to (2). When . Then, the noise factor as a can be expressed by function of

(1) is equal to at the resonance frequency . In the proposed LNA, the inductor at the source of is removed compared with the L-CSLNA. Removing the source inductor not only reduces the chip area but also gives other benets. Typical of an integrated inductor is in the range of 520 [24]. As the target NF approaches 1 dB, the parasitics, such as inductor series resistance, substrate resistance and ESD devices, start to dominate the LNA noise performance. Because the real , , , , and imaginary terms in (1) are dependent on and , the topology provides more freedom for the choice of whose quality factor is crucial for high the single inductor noise performance design. B. Noise Analysis The small-signal model of Fig. 5 is employed to perform the is noise analysis. The gate resistance of the input transistor, ignored with the assumption that the gate impedance is mainly capacitive, and the DC blocking capacitor in the feedback path is shorted since it has a small impedance at the desired frequency. is the loss of the gate inductor . The noise contribution of the cascode transistor, is neglected due to the noise cancellation mechanism of the cascode transistor when the output impedance of the input device is much higher than the inverse is the load of the transconductance of the cascode transistor.

(3) To optimize the NF for a given specication and power condition, all design parameters need to be represented by one design value. This is discussed in Appendix. After applying the NF optimization for a xed power condition [1], the minimum NF and optimum factor are given by

(4)

3022

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 11, NOVEMBER 2009

and (5)

Assuming , channel device [1] and become

, ,

and

for a short , (4) and (5)

optimum design condition assumes no power and area limitations, as well as use of ideal passive devices and no parasitics. Indeed, the achievable minimum noise gure of each topology is determined by many other factors such as specications, applications, frequency of interest, and technology. The noise factor of the resistive feedback LNA in Fig. 2(b) is derived as

(6) (7) (11) As (11) implies, the NF can be improved by burning more power. It can be shown that the noise factor of the CGLNA in Fig. 2(a) is given by

C. Comparison of Noise Performance The following noise analysis assumes that all LNA topologies have matched input impedances. Also, the noise from passive devices, loads, and the cascode transistor are neglected to simplify the noise factor and focus on the noise contribution of the drain and induced gate noises of the input device. In [1], the optimum NF of the L-CSLNA for a xed power condition is given as (8) which was corrected later as follows [2]: (9) This optimal NF shows a smaller noise factor compared to (4). The reason for this difference can be explained by comparing the NF expressions before optimization. The NF expression of the L-CSLNA using the factor is stated as

(12) Interestingly, the noise expressions of the the CGLNA and RFLNA seem very similar but have one big difference. Because the input matching condition of the CGLNA is that equals to , the noise factors of the CGLNA and RFLNA become exactly same when the RFLNA has the condition that . It is possible to improve the noise factor of the CGLNA by drawing more current in the input device or having larger than one, which increases the transconductance of the input device [3]. Fig. 6 shows the theoretically analyzed NF plots of various LNA topologies. Plots of the L-CSLNA and the proposed LNA are minimum NFs for xed power condition. The CGLNA is not optimized for a xed power condition since its input ) matching condition determines its transconductance (or and its minimum NF. The minimum NF without a xed power limitation is used for the RFLNA by the same reason as the is assumed to be 30 mA/V. A comparison is CGLNA, and made for the short channel model ( , , ) including the drain current noise, the induced gate noise and the correlation between them. It is observed that the CGLNA and RFLNA that have a shunt input network exhibit less frequency dependency and high NF at low frequencies because of the dominant constant term in the NF equation. On the other hand, the L-CSLNA and the proposed LNA that use the series RLC input network show strong frequency dependency and a low NF at low frequencies. For the analysis excluding the parasitics of the passive components, the NF of the proposed LNA is comparable to that of the L-CSLNA and lower than that of the CGLNA or RFLNA at most practical operating frequencies. Since the NF of the L-CSLNA deviates from the theoretical minimum value because of the parasitics of inductors for typical [23], the proposed topology applications where that requires only one inductor at the gate provides a signicant advantage for NF optimization including passive parasitics. Due to the intrinsically higher NF of the CGLNA and RFLNA,

(10) which neglects the noise contribution from the loss of inductors. In (10), the second, third, and last terms are the noise contribution of the drain current noise, the correlation portion between the drain and the induced gate noises, and the uncorrelated induced gate noise, respectively. The correlation term has negative sign which cancels a portion of noise factor of the L-CSLNA. However, the correlated part between the drain noise and the induced gate noise for the proposed LNA has a positive sign and thus increases the NF. The effect of the noise cancellation by the correlated portion between the drain and the induced gate noises is also crucial in the comparison of (8) with (9), because the former is the optimized NF when the correlated portion set a false positive sign. For this reason, the inductively degenerated common-source topology shows better noise performance for the optimum design condition, theoretically. The

JOO et al.: A 2.4-GHz RESISTIVE FEEDBACK LNA IN 0.13- m CMOS

3023

Fig. 6. Comparison of noise gure versus normalized unity gain frequency (! =! ) for different LNA topologies such as inductively degenerated LNA (L-CSLNA[1] for (8), L-CSLNA[2] for (9)), proposed LNA, common-gate LNA (CGLNA), and resistive feedback LNA (RFLNA). c = j 0:395, = 2:5,  = 5, and g = 30 mA=V (for RFLNA).

those topologies have been modied and combined in real applications. A literature survey has been performed to compare recently reported CMOS LNAs for narrowband and wideband applications in Fig. 7. The LNAs are categorized into three fundamental topologies (common gate (CG), inductively degenerated common-source (L-CS), and resistive feedback (RF)) and others. CGLNAs [12][22], [26][28] include noise canceling CG using a common-source amplier or transformer, -boosted CG, and so on. L-CSLNAs [8][11], [28][38] include typical inductively degenerated LNAs, wideband input matching LC lter merged LNA, and bandwidth extended resistive feedback L-CSLNA. RFLNAs [4], [39][45] consist of mainly wideband LNAs with resistive feedback. Finally, the others [5], [6], [46][54] include NMOS shunt feedback LNAs, distributed LNAs, reactive feedback LNAs, and transformer based LNAs. Fig. 7 clearly shows that most of the L-CS topologies have NFs lower than 3 dB, but RF, CG and other schemes have higher noise gures. As expected from the NF expressions, the CG and RF architectures have similar NF distributions, and the noise performances of both LNAs are mainly determined by the power consumption of the input devices. Many L-CSLNAs have NFs lower than 2 dB. This gure shows that recently reported measurement data agrees with the theoretical noise performance analysis of Fig. 6, although measured data shows a smaller NF gap between the L-CSLNA and RF/CGLNA topologies than the theoretical analysis. D. Sensitivity to Process and Temperature Variations The reliability of LNAs over process and temperature changes is one of the main design considerations. In this subsection, the proposed LNA performance has been simulated for different process corners and temperatures at 2.4 for GHz. Table I lists ve corner simulation results at 27 the fully integrated LNA whose design details are described in Section IV. Though S21 is highly dependent on process dB, and the corners, the LNA maintains an S11 less than variation of NF is less than 0.6 dB. The main reasons for the large variation of S21 shown in Table I are the variation of the

Fig. 7. Comparison of the literatures noise gure over frequencies normalized to unity gain frequency for different LNA topologies: inductively degenerated LNA (L-CS), common-gate LNA (CG), resistive feedback LNA (RF), and others. The markers with black lling represent narrowband LNAs, while white lings represent wideband LNAs.

TABLE I CORNER SIMULATION FOR THE FULLY INTEGRATED LNA OF FIG. 8(A)

TABLE II SIMULATED VARIATION OVER TEMPERATURE FOR THE FULLY INTEGRATED LNA OF FIG. 8(A)

input device transconductance and the detuning of the LC load due to the changes in parasitics. The simulated gain and to noise gure variations over a temperature range of 100 are smaller than 1.3 dB and 0.8 dB, respectively while dB as shown in Table II. This is because keeping of the voltage gain in front of the transistor in the input stage. Equation (3) implies that if the voltage gain is stable for typical , the overall noise gure becomes applications less sensitive to the variation of the transistor. These simulation results show that the variation of noise performance of the LNA due to process and temperature variation is not signicant, and the proposed LNA is able to operate as the rst active block to deliver required noise and gain performance for the following blocks. IV. LNA IMPLEMENTATION To demonstrate the performance of the proposed LNA, two different versions, a fully integrated LNA and an LNA with

3024

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 11, NOVEMBER 2009

Fig. 8. Complete schematics of (a) fully integrated LNA, and (b) LNA having off-chip matching network.

off-chip input matching network, have been designed and fabricated in a standard 8 metal 0.13- m RF CMOS technology for 2.4 GHz operation. The complete schematics of the LNAs are shown in Fig. 8. Both ampliers have a two-stage cascaded architecture of a core amplier and an open-drain output buffer. The core amplier has cascode conguration to improve the reverse isolation and reduce the Miller capacitance between the . The size of is 200 gate and drain of the input device, m/0.13 m which gives minimum NF, when the transistor is biased at 2 mA with a 1.2 V supply. and PMOS, which have thicker gate The NMOS, oxide than normal transistors for higher threshold and breakdown voltages, are added to protect the gate of the input device from electro-static discharge (ESD) [55]. The ESD protection devices increase the noise gure by 0.1 dB due to the parasitic capacitance and the nite output resistance. The gate or is 8.8 nH. The feedinductance, is 8.4 and the load inductance, is back resistance, and 8 nH. The quality factor of the on-chip spiral inductor, is around 10 at 2.4 GHz. It is assumed that the factor of and the surface mounted exthe bondwire inductor, are 30 and 60 respectively in the LNA ternal inductor, simulation. Except for the ESD protection transistors, the LNA transistors, metal-insuhas been designed using standard lator-metal (MIM) capacitors, and standard spiral inductors. In the simulation, the LNA with off-chip matching network shows an NF of 0.9 dB, while the NF of the fully integrated LNA is 1.9 dB. Since both LNAs have the same design besides the gate inductor, the NF simulation results assure the importance of the quality of passive components for high noise performance design. The second stage of the LNA is an open-drain structure to

Fig. 9. Chip photograph of (a) fully integrated LNA, and (b) LNA with off-chip matching network.

utilize the entire output signal current and use the test equipment as a load. The load of the rst stage is tuned to 2.4 GHz using and the total capacitance of , the input capacitance of the second stage, and the parasitic capacitance of the output node. The voltage gain of the output buffer is about 3.5 dB when it is connected to a 50 load. Fig. 9 shows the chip microphoto of the proposed LNAs. The chip sizes including pads and bypass capacitors are 900 m 670 m and 850 m 680 m for the fully integrated LNA and the off-chip matched LNA, respectively. 100 pF bypass capacitors are integrated between the power supply and ground for a better ac ground. The ground of all MIM capacitors is shielded to minimize noise injection from the substrate and every transistor is protected by double guard rings including an

JOO et al.: A 2.4-GHz RESISTIVE FEEDBACK LNA IN 0.13- m CMOS

3025

Fig. 11. Measured and simulated NF of the LNA for the fully integrated (FI) and off-chip matching (PI) version.

Fig. 10. Measured S parameters of the LNA for the fully integrated and off-chip matching (partially integrated) version. (a) S11 and S22, and (b) S21 and S12.

Nwell ring. The noise of the substrate is also reduced by putting many substrate contacts between wide ground metal and the substrate. The two designs were fabricated in different batches. V. EXPERIMENTAL RESULTS AND DISCUSSION On-wafer measurement has been performed for the fully integrated LNA of Fig. 9(a). For the LNA using an off-chip matching network, a PCB has been fabricated using a low loss RF substrate. For the NF measurement, the off-chip matching LNA was tested inside of a shielding case to prevent interference from ambient interferers. Fig. 10 shows the measured scattering (S) parameters. The measured input reection coefcients, S11s of the fully integrated LNA and the LNA with off-chip matching network are dB and dB, while the gains (S21) are 28.3 dB and 32.0 dB at 2.4 GHz, respectively. The measured and simulated NFs are plotted in Fig. 11, and they show good agreement at the target frequency. The measured NF of the LNA with an off-chip inductor is 1.2 dB, while that of the fully integrated LNA is 2.0 dB. As anticipated, the LNA with a high off-chip gate inductor attains 0.8 dB better NF than the fully integrated one. The measured performances of the two versions of the proposed LNA are compared with those of reported LNAs of different

Fig. 12. Linearity of the fully integrated LNA. (a) Simulated IIP3 of the LNA core, and (b) simulated and measured IIP3 of the LNA with the output buffer.

topologies as shown in Fig. 7, and they demonstrate that the resistive feedback topology using series RLC matching overcomes the theoretical limits of the RFLNA that uses a shunt input network. The simulated and measured results of two-tone tests using 2.395 GHz and 2.4 GHz inputs show good agreement as shown in Fig. 12(b) for the fully integrated version. The measured input-referred third-order intercept point (IIP3) including the buffer is dBm and the measured 1-dB compression point dBm. The linearity of the overall LNA is limited by is

3026

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 11, NOVEMBER 2009

Fig. 13. Measured and simulated  factors of the fully integrated LNA.

the open-drain buffer stage introduced for testing purposes. dBm as shown in The simulated IIP3 of the LNA core is Fig. 12(a). The measured and simulated factors of the fully integrated LNA are shown in Fig. 13. These stability factors are calculated using the measured and simulated S parameters. Due to the open-drain output buffer, the measured factor is less than 1 from 1.4 GHz to 2.1 GHz. Fig. 14 shows the measured source and load stability circles of the fully integrated LNA from 0.5 to 2.2 GHz. The source and load stability circles stay away from the center of the smith chart and demonstrate that the LNA is source and load stable for the intended operation with 50 impedances. Furthermore, the simulation using an impedancematched output buffer shows a factor larger than 6 up to 10 GHz, which ensures unconditional stability in this frequency range. It should be noted that the stability of LNAs is essentially determined by the reverse isolation of the input and output when both terminals are matched. The negative feedback path of the core LNA also helps to stabilize the LNA. The LNA core and the buffer for the fully integrated LNA draw only 2.2 mA and 1.8 mA respectively from a 1.2 V power supply. Table III shows a performance summary and comparison with previous works. To compare the performance of the LNAs, the gure of merits (FOM1 and FOM2) dened in [28] are used. The FOM1 is a function of the operating frequency, gain, noise factor, and power consumption, and is given by

Fig. 14. Measured stability circles of the fully integrated LNA. (a) Source stability circles, and (b) load stability circles.

VI. CONCLUSION -boosted resistive feedback LNA We have presented a using a series RLC matching network at 2.4 GHz. The proposed LNA achieves easy and reliable input matching, low NF, and high gain at the same time. The complete noise analysis for the proposed LNA is performed and its optimal NF is compared with CGLNA, RFLNA, and L-CSLNA topologies. It is conrmed that the theoretical minimum NF of each topology has good agreement with those of the fabricated LNAs by a survey. Even though the inductively degenerated LNA shows the best theoretical noise performance at the same normalized operation frequency assuming ideal passive components, the proposed topology is a promising candidate for a narrowband LNA considering all design parameters including area, power, degree of design freedom, and limited quality of passive components. A fully integrtated and an off-chip matching versions of the proposed LNA have been fabricated, and they achieve an NF of 2.0 dB and 1.2 dB, S21 of 24 dB and 29 dB, while dB and dB, respectively. The providing an S11 of test results demonstrate the advantages of the proposed scheme and achieve the best gure of merit.

(13) FOM2 includes IIP3 and is given by

(14) The proposed work shows the best FOM1 and excellent FOM2. The theoretical analysis and experimental results demonstrate the effectiveness of the proposed topology in terms of gain, noise and power.

JOO et al.: A 2.4-GHz RESISTIVE FEEDBACK LNA IN 0.13- m CMOS

3027

TABLE III LNA PERFORMANCE SUMMARY & COMPARISON

APPENDIX The minimum noise factor of the proposed LNA can be found needs to be expressed by the physical using (3). First of all, parameters. Since , in Fig. 3, the quality factor, is given by

can be rewritten as On the other hand, . Applying above equality to (3) with the input impedance matching condition, the noise factor can be expressed as

(A-3) To simplify the optimization procedure of the noise factor, we have neglected the contribution of the inductor loss, to the noise factor. By substituting (A-2) and [1, (39)] into (A-3), the noise factor is expressed in terms of the relative gate overdrive, , , and , by (A-4)

(A-1) where is . For simplicity, by applying the apto (A-1), when proximation is much larger than 1, we get and from [1]. Shaeffer [1] has dened , is the power consumption of that the amplier, and , where is the saturation velocity, and is the velocity saturation eld strength. The factor can be rewritten using physical technological parameters and design specications, under the assumption that , by (A-2)

(A-5) This equation is minimized for a xed when (A-6) The solution of the equation is given by

where is the ratio of and . For 0.13- m CMOS with a 1.2 V supply, , mW, (for typical LNA designs), and K is less than 0.01. Thus, (1-K) can be considered as a constant term to simplify the following derivation.

(A-7)

3028

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 11, NOVEMBER 2009

under the assumptions that (A-7) to (A-2), an optimum achieved by

and . By inserting for a xed power condition is

(A-8) Finally, the minimum NF for a xed power condition can be evaluated using (A-8), which is given in (4). ACKNOWLEDGMENT The authors would like to thank the Electronics and Telecommunications Research Institute for the chip fabrication. REFERENCES
[1] D. K. Shaeffer and T. H. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplier, IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745759, May 1997. [2] D. K. Shaeffer and T. H. Lee, Comment on Corrections to a 1.5-V, 1.5-GHz CMOS low noise amplier, IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 23592359, Oct. 2006. [3] D. J. Allstot, X. Li, and S. Shekhar, Design considerations for CMOS low-noise ampliers, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2004, pp. 97100. [4] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, Wide-band CMOS low-noise amplier exploiting thermal noise canceling, IEEE J. SolidState Circuits, vol. 39, no. 2, pp. 275282, Feb. 2004. [5] J. Borremans, P. Wambacq, C. Soens, Y. Rolain, and M. Kuijk, Low-area active-feedback low-noise amplier design in scaled digital CMOS, IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 24222433, Nov. 2008. [6] P. Heydari, Design and analysis of a performance-optimized CMOS UWB distributed LNA, IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 18921905, Sep. 2007. [7] A. Bevilacqua and A. M. Niknejad, An ultrawideband CMOS lownoise amplier for 3.110.6-GHz wireless receivers, IEEE J. SolidState Circuits, vol. 39, no. 12, pp. 22592268, Dec. 2004. [8] T. Taris, Y. Deval, and J. B. Begueret, Current reuse CMOS LNA for UWB applications, in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2008, pp. 294297. [9] C.-W. Kim, M.-S. Kang, P. T. Anh, H.-T. Kim, and S.-G. Lee, An ultra-wideband CMOS low noise amplier for 35-GHz UWB system, IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 544547, Mar. 2005. [10] V. K. Dao, Q. D. Bui, and C. S. Park, A multi-band 900 MHz/1.8 GHz/ 5.2 GHz LNA for recongurable radio, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2007, pp. 6972. [11] Y. Gao, Y. Zheng, and B.-L. Ooi, A 0.18-m CMOS UWB LNA with 5 GHz interference rejection, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2007, pp. 4750. [12] K. Bhatia, S. Hyvonen, and E. Rosenbaum, An 8-mW, ESD-protected, CMOS LNA for ultra-wideband applications, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2006, pp. 385388. [13] S. C. Blaakemeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B. Nauta, Wideband balun-LNA with simultaneous output balancing, noise-canceling and distortion-canceling, IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 13411350, Jun. 2008. [14] S. Chehrazi, A. Mirzaei, R. Bagheri, and A. A. Abidi, A 6.5 GHz wideband CMOS low noise amplier for multi-band use, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2005, pp. 801804. [15] W.-H. Chen, G. Liu, B. Zdravko, and A. M. Niknejad, A highly linear broadband CMOS LNA employing noise and distortion cancellation, IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 11641176, May 2008. [16] D.-G. Im, S.-S. Song, H.-T. Kim, and K. Lee, A wideband CMOS variable-gain low noise amplier for multi-standard terrestrial and cable TV tuner, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2007, pp. 621624.

[17] J. Jussila and P. Sivonen, A 1.2-V highly linear balanced noise-cancelling LNA in 0.13-m CMOS, IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 579587, Mar. 2008. [18] C.-F. Liao and S.-I. Liu, A broadband noise-canceling CMOS LNA for 3.110.6-GHz UWB receivers, IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 329339, Feb. 2007. [19] T. Kihara, T. Matsuoka, and K. Taniquchi, A 1.0 V, 2.5 mW, transformer noise-canceling UWB CMOS LNA, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2008, pp. 493496. [20] A. Liscidini, C. Ghezzi, E. Depaoli, G. Albasini, I. Bietti, and R. Castello, Common gate transformer feedback LNA in a high IIP3 current mode RF CMOS front-end, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2006, pp. 2528. [21] X. Li, S. Shekhar, and D. J. Allstot, Gm-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-m CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 26092619, Dec. 2005. [22] J. S. Walling, S. Shekhar, and D. J. Allstot, A g -boosted currentreuse LNA in 0.18 m CMOS, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2007, pp. 613616. [23] H. Hashemi and A. Hajimiri, Concurrent multi-band low-noise ampliers: Theory, design, and applications, IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 288302, Jan. 2002. [24] J. R. Long and M. A. Copeland, The modeling, characterization, and design of monolithic inductors for silicon RF ICs, IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 357369, Mar. 1997. [25] A. van der Ziel, Noise in solid-state devices and lasers, Proc. IEEE, vol. 58, no. 8, pp. 11781206, Aug. 1970. [26] S. C. Blaakmeer, E. A. Klumperink, D. M. Leenaerts, and B. Nauta, A wideband noise-canceling CMOS LNA exploiting a transformer, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2006. [27] S. Lou and H. C. Luong, A 0.8 GHz-10.6 GHz SDR low-noise amplier in 0.13-m CMOS, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2008, pp. 6568. [28] D. Linten, S. Thijs, M. I. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Donnay, and S. Decoutere, A 5-GHz fully integrated ESD-protected low-noise amplier in 90-nm RF CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 14341442, Jul. 2005. [29] D. Linten, L. Aspemyr, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Thijs, R. Garcia, H. Jacobsson, P. Wambacq, S. Donnay, and S. Decoutere, Low-power 5 GHz LNA and VCO in 90 nm RF CMOS, in Proc. IEEE VLSI Circuits Symp., Jun. 2004, pp. 372375. [30] D. Linten, X. Sun, S. Thijs, M. I. Natarajan, A. Mercha, G. Carchon, P. Wambacq, T. Nakaie, and S. Decoutere, Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2005, pp. 497500. [31] X. Fan, H. Zhang, and E. Sanchez-Sinencio, A noise reduction and linearity improvement technique for a differential cascode LNA, IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 588599, Mar. 2008. [32] K. Han, J. Gil, S.-S. Song, J. Han, H. Shin, C. K. Kim, and K. Lee, Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplier, IEEE J. SolidState Circuits, vol. 40, no. 3, pp. 726735, Mar. 2005. [33] B. A. Floyd and D. Ozis, Low-noise amplier comparison at 2 GHz in 0.25-m and 0.18-m RF-CMOS and SiGe BiCMOS, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2004, pp. 185188. [34] D. Grifth, A +7.9 dBm IIP3 LNA for CDMA2000 in a 90 nm digital CMOS process, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2006. [35] Y.-W. Hsiao and M.-D. Ker, An ESD-protected 5-GHz differential low-noise amplier in a 130-nm CMOS process, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2008, pp. 233236. [36] N. Kim, V. Aparin, K. Barnett, and C. Persico, A cellular-band CDMA 0.25-m CMOS LNA linearized using active post-distortion, IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 15301534, Jul. 2006. [37] T.-S. Kim and B.-S. Kim, Linearization of differential CMOS low noise amplier using cross-coupled post distortion canceller, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2008, pp. 8386. [38] H.-J. Lee, D. S. Ha, and S. S. Choi, A 3 to 5 GHz CMOS UWB LNA with input matching using Miller effect, in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 202203. [39] R. Gharpurey, A broadband low-noise front-end amplier for ultra wideband in 0.13-m CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 19831986, Sep. 2005.

JOO et al.: A 2.4-GHz RESISTIVE FEEDBACK LNA IN 0.13- m CMOS

3029

[40] S. R. Karri, A. Arasu, K. W. Wong, Y. Zheng, and F. Lin, Low-power UWB LNA and mixer using 0.18-m CMOS technology, in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2006, pp. 259262. [41] B. G. Perumana, J.-H. C. Zhan, S. S. Taylor, and J. Laskar, A 5 GHz, 21 dBm output-IP3 resistive feedback LNA in 90-nm CMOS, in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2007, pp. 372375. [42] L. Tripodi and H. Brekelmans, Low-noise variable-gain amplier in 90-nm CMOS for TV on mobile, in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2007, pp. 368371. [43] M. Vidojkovic, M. Sanduleanu, J. van der Tang, P. Baltus, and A. van Roermund, A 1.2 V, inductorless, broadband LNA in 90 nm CMOS LP, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2007, pp. 5356. [44] C.-S. Wang and C.-K. Wang, A 90 nm CMOS low noise amplier using noise neutralizing for 3.1-10.6 GHz UWB system, in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2006, pp. 251254. [45] J.-H. C. Zhan and S. S. Taylor, A 5 GHz resistive-feedback CMOS LNA for low-cost multi-standard applications, in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 200201. [46] R. Ramzan, S. Andersson, J. Dabrowski, and C. Svensson, A 1.4 V 25 mW inductorless wideband LNA in 0.13 m CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 424425. [47] E. Adabi and A. M. Niknejad, CMOS low noise amplier with capacitive feedback matching, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2007, pp. 643646. [48] A. Bevilacqua, A. Vallese, C. Sandner, M. Tiebout, A. Gerosa, and A. Neviani, A 0.13 m CMOS LNA with integrated balun and notch lter for 3-to-5 GHz UWB receivers, in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 420421. [49] C.-T. Fu and C.-N. Kuo, 3 11 -GHz CMOS UWB LNA using dual feedback for broadband matching, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2006, pp. 6770. [50] F. Zhang and P. R. Kinget, Low-power programmable gain CMOS distributed LNA, IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 13331343, Jun. 2006. [51] M. T. Reiha and J. R. Long, A 1.2 V reactive-feedback 3.1-10.6 GHz low-noise amplier in 0.13 m CMOS, IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 10231033, May 2007. [52] S. B. T. Wang, A. M. Niknejad, and R. W. Brodersen, Design of a sub-mW 960-MHz UWB CMOS LNA, IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 24492456, Nov. 2006. [53] S. Shekhar, J. S. Walling, S. Aniruddhan, and D. J. Allstot, CMOS VCO and LNA using tuned-input tuned-output circuits, IEEE J. SolidState Circuits, vol. 43, no. 5, pp. 11771186, May 2008. [54] G. Sapone and G. Palmisano, A 90-nm CMOS two-stage low-noise amplier for 35-GHz ultra-wideband radio, in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 2008, pp. 489492. [55] B. Kleveland, T. J. Maloney, I. Morgan, L. Madden, T. H. Lee, and S. S. Wong, Distributed ESD protection for high-speed integrated circuits, IEEE Electron Device Lett., vol. 21, pp. 390392, Aug. 2000.

Sanghoon Joo (S08) received the B.S. degree from Korea University, Korea, in 2003. He is currently pursuing the Ph.D. degree in electrical and computer engineering at Purdue University, West Lafayette, IN. His research interests include RF circuit design for wireless communication in CMOS and bipolar processes. Mr. Joo was the rst place winner in Phase One and Phase Two of the 20072008 SRC/SIA IC Design Challenge.

Tae-Young Choi (S02M09) received the B.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 1999, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan at Ann Arbor in 2002 and 2007, respectively. He is currently a post-doc at Purdue University, West Lafayette, IN. His research interests are in RF integrated circuits for wireless applications.

Byunghoo Jung (S00M05) received the B.S. degree from Yonsei University, Korea, in 1990, the M.S. degree from KAIST, Korea, in 1992, and the Ph.D. degree from the University of Minnesota, Twin Cities, in 2005. From 1992 to 1999, he was with Samsung Electronics, Korea, where he was involved in the design of video signal driver circuits for at panel displays. After receiving his Ph.D. in January 2005, he was with Qualcomm in San Diego, CA, as a Senior RF IC Design Engineer until he joined the School of Electrical and Computer Engineering at Purdue University, West Lafayette, IN, as an Assistant Professor in August 2005. His research interests include high-speed analog/RF circuit design for wireless and wired communications and bio-telemetry systems. He holds 10 U.S. patents Dr. Jung is the rst place winner of the 20022003 SRC SiGe BiCMOS Design Challenge (as a lead designer) and the 20072008 SRC/SIA IC Design Challenge (as a lead faculty). He has been serving as a Co-Chair of the DAC/ISSCC Student Design Contest (SDC) since October 2006, as an Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since January 2009, and as a member of the Analog Signal Processing Technical Program Committee (ASPTPC) in the IEEE Circuits and Systems Society since May 2006.