Assignment

Batch: 2009 2013

VINAYAKA MISSIONS UNIVERSITY

Vinayaka Missions Kirupananda Variyar Engineering College

SALEM 636 308 Semeste

B.E. BIOMEDICAL ENGINEERING E347528 ANALOG AND DIGITAL ICs Mr.Mathan Kumar.S 4 27 09 2011

Programme Subject Code & Name Name of the Tutor Assignment. No. Date of Announcement

Date of Submission

31 09 2011

PART A

Two (or) Three lines explanation / Short Answer / Short Calculation

1. Define half adder. 2. What do you meant by Encoder? 3. List out the basic types of PLD. 4. Define full adder. 5. What is PLA? How its differ from ROM? 6. Define half subtractor. 7. What is meant by decoder? 8. Differentiate sum and carry. 9. What is meant by a full subtractor? Draw a full subtractor circuit. 10. Draw the logic diagram of half adder. 11. Write a design procedure of combinational circuits. 12. Differentiate decoder and encoder. 13. What is the similar between a half adder and a half subtractor? 14. What do you meant by Comparator?

Signature of the Tutor EEE

Signature of the HOD /

Assignment 15. Define Multiplier. 16. What is meant by multiple bit adders? 17. Write short notes on ROM. 18. Define propagation delay.

Batch: 2009 2013

19. What is PAL? How it differs from ROM and PLA? 20. What is meant by Combinational circuits? 21. Draw the logic diagram of BCD to Excess 3 code converter 22. Write the truth table of Full adder 23. What is meant by binary decoder? 24. What are the difference between decoder and demultiplexer? 25. Write short notes on priority encoder. PART B Descriptive ( Essay Type) (8 Marks) (4 Marks) (8 Marks) (4 Marks) (8 Marks) (4 Marks) (4 Marks) (8 Marks) (6 Marks) (6 Marks) (6 Marks) (6 Marks)

1. i) Design of half adder and full adder using gates. 2. ii) Design the logic circuit for odd parity checker. i) Design of half subtractor & full subtractor using gates.

ii) List out the design procedure of a combinational circuit. 3. i) Design a 3 to 8 Decoder using gates. ii) Draw the logic diagram of BCD to Excess 3 code converter. 4. i) Explain the various types of ROM. ii) Implement the following Boolean function using ROM. F1 ( A1 , A0 ) = m(1, 2) and F2 ( A1 , A0 ) = m(0,1,3) 5. i) Explain in detail about parallel binary adder with neat block diagram. ii) Give the comparison between PROM, PLA and PAL. 7. i) Design a BCD to 7-Segment display decoder. ii) Design a priority encoder.

6. Explain details about the design procedure of circuit 4 - bit multiplier with example. (12 Marks)

8. How will you build a full adder using two half adders and an OR gate? Explain briefly. (12 Marks) 9. Draw and explain the block diagram of n - bit parallel and binary adder subtractor. (12 Marks) 10. i) Draw and explain the block diagram of PLA. (4 Marks)

Signature of the Tutor EEE

Signature of the HOD /

Assignment

Batch: 2009 2013

ii) Implement the following Boolean function using PLA. A( x, y, z ) = m(1, 2, 4, 6) , B ( x, y, z ) = m(0,1, 6, 7) & C ( x, y, z ) = m(2, 6) 1.

(8 Marks)

Signature of the Tutor EEE

Signature of the HOD /