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A NOVEL AERONAUTICAL STATIC INVERTER WITH HIGH FREQUENCY PULSE DC LINK*


Chen Daolian Liu Zhizheng YanYangguang H u Y u w e n
Dep art ment o f Aut om at i c Co n trol,NUAA 29 Y uda o Str eet, N anji ng 210016,P.R.China Solar inverters

ABSTRACT
A n ew c o m b in e d s of t-switc h ing te c h ni qu e an d a n o v el to po lo gy of aero nautical static inverter with high frequency pulse dc link are proposed in this paper, namely an elect r ic al isol at ed c o nv erter c an realize s of t-switc hi n g of t w o-stage cas c ad e converters. It lays tech ni cal foundation for high power density, high efficiency and low cost aeronautical static inverter. The operation and design approach o f t his t opology are carefully analyzed and studied. The validity of this topology is verified by simulation and test.

soft-switching technique. The topology structure is shown in Fig. 1. The topology structure is constituted of

multifunctions integrated soft-switching DC/DC converter ( MISSC) and DC/AC inverter. The ASI has merits such as simple topology, small bulk, lower weight, high efficiency and low cost.
56)

& ^^octo.-al S rience Fom^Hon o f J mn g s u ^o^nce.

Key words: inverters; high frequency links; active clamp cir


cuits; co m b in ed s oft -swit ch ing tech ni qu es; three state discrete pulse modulation

INTRODUCTION
Aeronautical static inverter ( ASI) is a set of electrical apparatus which transfers 18~32
Vdc,

aeronautical main power supply, into 115V400Hz AC, which is used as second power supply in aircraft. ASI is normally two-stage cascade, that is electrical isolated DC/DC converter (because load shares the ground with main power supply) and DC/AC inverter. The DC/DC converter transfers the unregulated 18 ~ 32
Vdc

into the regulated 180

Vdc,

then transferred into

Supported by Aviation Basic Science Foundation of Chin a( 9 Received 5 Jan. 1999; revision received 25 Feb. 1999 regulated

115V400Hz AC by DC/AC inverter. T he effective method to realize high pow er density ASI is to raise switching frequency- With high switching frequency, the switching losses increase linearly and the efficiency reduces in conventional hard-switching PWM converters. In o rder to complete high pow er density and high efficiency simultaneously, it is necessary to use soft-switching PWM techniques which combine the merits of resonant and PWM techniques. Guichao Hua, et al propose zero-volt agetransition and zero-current-transition techniques, which lay technical foundation for soft-switching single-stage DC/DC converters 11,2] ; Resonant DC link inverter proposed by Dr. Divan lays technical foundation for soft-switching single-stage DC/ [3] AC inverters . If single-stage
,

soft-switching

technique is used in ASI the to pol ogy is very complicated and results in low efficiency, high cost and large volume and weight. Ref. [ 4] proposes a novel ASI topology with high frequency pulse dc link which uses a combined

No. 1

Chen Daolian, et al. A Novel Aeronautical Static Invert er with High Frequency

47

Th ere has been no report about this topology until now. The operation and design approach of this topology and control strategy is carefully analyzed and studied.

active clamp forward converter is introduced. In order to reduce voltage stress of power devices in the inverter bridge , the duty cycle of high frequency dc pulse waveform can be more than 0. 5. Thus the novel ASI topology is formed and shown in Fig. 2. In Fig. 2, Sc and Cc form the active clamp branch of forward converter and it is used to provide a path for recycling the magnetizing energy after the main power device S turns off. S and Sc turn on/turn off both under zero-voltage conditions. The active device Sr and the capacitor C are in

Fig. 1 A novel topology structure of ASI

series and form the branch of absorbing reactive feedback energy from ac side of the inverter. In order to realize ZVS switching of power device S r, the power device S r is quasi synchronous switch with the power device S, i. e. delaying turn-on and taking turn-off ahead of schedule.

AN ANALYSIS OF A NOVEL ASI TOPOLOGY AND CONTROL STRATEGY

1.1 A novel ASI circuit topology The functions of MISSC converter lay in three respects: ( 1) electrical isolation between input and output; (2) absorbing reactive energy from AC side of DC/AC inverter bridge; ( 3) supplying high frequency dc pulse waveform for the inverter, so the power devices turn on/off when udo gets to zero and make zero-voltage- switching possible. Push pull mode, half bridge mode, full bridge mode, and forward mode MISSC converters constitute a circuit topology family . 1994-2012 China Academic Journal Electronic Publishing House. All rights reserved, http://www.cnki.net

Fig. 2 A novel topology of ASI with high frequency pulse dc link

Considering wide input voltage of ASI (18 ~32 V ), anew MISSC converter based on an interleaving

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energy. 1. 2 Control strategy The MISSC converter and the DC/AC inverter have their separate close loop control circuit. The voltage-mode control strategy is introduced in the MISSC converter based on an interleaving active clamp forward converter, and the three state discrete pulse modulation (DPM) hysteresis current control strategy used in the inverter and its principle are shown in Fig- 3. 2.1 Design of MISSC converter The MISSC converter based on an interleaving active clamp forward converter is introduced, its key waveforms are shown in Fig.4 Instead of a reset winding, an auxiliary switch Sc is used to provide a path for recycling the magnetizing energy in a lossless manner. This provides optimal reset of the transformer as well as reduced switching loss. To minimize the capacitive turn-on loss, S should not be turned

2 DESIGN OF A NOVEL ASI TOPOLOGY

Fig. 3 Three state DPM hysteresis current control strat egy

The current of filtering inductance (if) is used as a feedback signal and compared to reference current (ig) - The difference between these two currents determines the switching state of the four power devices in the inverter. The controlling rules are as follows
uab

=
Fig. 4 Key waveforms of the MISSC based on an interleaving active clamp forward converter

+ Ud o m , + 1 state ( i g - i f > h/ 2, Si & S 4 on) U d o m , - 1 state ( i g - i f < - h/ 2, S 2 & S 3 on) 0,0state(| i g - i f | < h/2,S 1 ( S 2 or S 3 ,S 4 on)

(1) where
uab

is the input voltage of the output filter and

on until u ds decreases to Ui. One prevailing approach designed to achieve the ZVS turn-on of S is to employ the magnetizing current. By properly gapping the transformer core, the magnetizing current magnitude at the turn-off of Sc is larger than the reflected load current. The difference between these two currents is used to completely discharge Cs after u ds decreases to Ui.

h the hysteresis width of the hysteresis comparator. If voltage and current loops are both used, control characteristics of output voltage and current will be good performance. When if and uab is inverse, that is if uab< 0, the freewheeling diode of S 1, S 4 or S 2, S 3 is on, the reactive energy from the AC side of inverter feed
1

199l4r2012 China Academic Journal Electronic


add a circuit branch composed of active device Sr and Cr to absorb this part of

back to DC side. 1 herelore, it is necessary to

No. 1

To reduce the magnitude of the magnetizing current required for ZVS, a saturable reactor in series with forward diode D 1 & D 2 can be used- With the help of the saturable reactor, the magnetizing current required for the ZVS of S is small. However, The core loss of the saturable reactor is large at high frequency and the saturable core may suffer severe thermal problem. Considering the increasing conduction loss with soft-switching operation and low input voltage (18~32 V) , the efficiency improvement gained by the soft-switching is insignificant. Therefore, with the switching frequency lower than 1MHz, the so ft-switching doesn , t exhibit much advantage over hard-sw itching. The switching frequency is selected at 50 kHz, because of the efficiency requirement, thus the frequency of high frequency dc pulse waveform udo is 100 kHz. Therefore, the hard turn-on is employed in the main power device S and ZVS is employed in the clamp switch Sc. The average voltage value of the high frequency dc pulse waveform is given by 2DU i Udo, avg _ N where N = N 1/N 2 is the transformer turn ratio, and D the duty cycle of every switching signal. According to the volt-second balance on the transformer , the voltage across the clamp capa cit or is D Uc= 1-D The clamp voltage decreases as Ui voltage increases and the duty the input cycle
( 3) ( 2)

UDS= U DSc = Ui + U c _ Ui _ N Udo, avg _ 1 - D _ 2D(1 - D) N 1 is determined by DU iT s N1 _ 2Bm A c where Ac is the core cross-section area, Bm the operating flux density, and Ts the switching period. T he value of the clamp capacitance is determined by the clamp voltage ripple, A Uc, which will affect the peak voltage stress of the transistors. A large clamp capacitance leads to a smaller AU c. However, it slows down the converter dynamic response to input voltage or load changes. Assuming that AUc < Uc, the magnetizing current will decrease during the ( 1 - D) Ts interval with a constant slope Uc/Lm. Thus, the clamp voltage ripple is 1l (1 - D) T s A Uc_ ^ 4C ^ where 1l
m

(4)

(5)

(6)

is the maximum value of the magnetizing

current. In steady-state 21l m (7) (1 - D) Ts Combining Eqs. ( 6, 7) A U c _ (1 - D) T s Uc _ 8LmC The integrated U C1525 is
Uc Lm

high-speed PWM controller employed in the conventional

voltagemode control configuration. The delay time between the control pulses of S and Sc is adjusted with the delay circuit which consists of two RC integrators with diodes. T2 is the delayed time between S turn-on and Sc turn-off. According to Fig. 4 2n L m C s 4 The delayed time between Sc turn-on and S pul
tu

(8)

decreases, and vice versa. Thus, the maximum switch voltage stress, which is equal to the sum Ui+ Uc, tends to remain approximately constant over the whole range of the input voltage. In addition, due to the charge balance of the clamp capacitor , the flux of the transformer is symmetrically operated in the first and the third quadrant. Therefore, this topology features the most efficient utilization of the magnetics T he peak voltage stress of S and Sc is given . by

rn-cf . T-

has to sati fy the

co n d ition nki.net

T2 >

(9)

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(10) T2 and H are adjusted in the worst case, Uc = U cm ax . 2. 2 Design of high frequency DC pulse waveform udo DPM of inverter is to compose the high frequency pulse waveform udo of the inverter input port to the needed low frequency voltage waveform uab . The output filter is only used to eliminate high order harmonics in voltage
u u

waveform (2D) should be as large as possible, in order to reduce voltage stress of the inverter bridge ; s power devices. However, if 2D is too large, it will lead to too small zero level time of
U do.

In order to make the

inverter bridged power devices realize reliably zero voltage switching, the maximum duty cycle 2Dmax has to satisfy the condition 2D max ^ 1 - t0 2Fs where t 0 is the zero level time of udo. Generally, tu= 1 ^s for 2Fs= 100 kHz, 2Fs is the frequency of dc pulse waveform Udo.

do and to obtain output sinusoidal

with low THD. DPM pulse combination is

shown in Fig. 4. The pulse of the voltage


uab

is concentrated in the

peak voltage region, where the high frequency dc pulse waveform udo is transferred to the output port totally.

3 SIMULATION AND TEST


This novel A SI topology is verified in 1 kVA prototype. The circuit parameters of the simulation and the test are as follows: Ui= 18 32 V, Udo,avg = 180 V, Fs= 50 kHz, 2D = 0. 5 0.9, N 1/N 2= 3T/36T, AUc/U ^ 10%, Cc= 3 ^F, T2= 1 vs, 71= 1.5 ^s, L 1/L 2= 8 ^H/4 ^H, C 1/C 2 = 2 200 ^F/ 220 ^F, Rd= 0. 1 Q, Cr= 68 ^F, Lf = 10 mH, Cf= 20 ^F, Uo= 115 V, Fo = 400 Hz. The soft ferrites R2KBD PM 62* 49 core is selected for the transformer and the filtering inductance, the

Fig. 5 DPM pulse combination waveform

MOSFET device 2* IXFK170N10 ( 170 A/100 V) for the power switch S, the MOSFET device IRF540(27

Filtering inductance L f and filtering capacitor Cf are used to store and release energy and they have effect on the peak value of the output voltage ( Uom). During the period of t 1 t 2(refer to Fig. 5), in order to guarantee low THD voltage Uo, Uom has to satisfy the condition N2 Uom ^ Udo,avg = ^DUi (11)

A/ 100 V) for the power switch Sc, and the MOSFET device IXFN48N50 (48 A/500 V) for the power switch Sr & S' S4, the super fast recovery diode DSEI60-10A (60 A/1 000 V) for the rectifier D 1 & D 2, and the regulating PWM controller UC1525 for the voltage-mode control of the MISSC converter. The simulation waveforms are shown in
Publi

Fig. 6. The test

waveforms are shown in Fig. 7.

Eq. ( 11) is the certeria to design the average voltage value of high frequency dc pulse waveform. Generally, Udo,avg = 170 190 V. Thus, the input DC voltage can be used to the limit and also there is some regulating margin for circuit to ensure low THD output voltage waveform. Otherwise, if Udo is too low, it will lead to the top distortion in output voltage waveform. The duty cycle of high frequency dc pulse

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Chen Daolian, et al. A N ovel Aeronautical Static Invert er with High Frequency

Fig. 6 Simulation waveforms of 1 kVA ASI

u d o : 100 V/div t: 500 ^s/div (a) High frequency pulse dc link voltage udo uAB :

100 V/div t: 500 ^s/div (b) Modulated voltage


uab

itf : 5 A/div t: 500 ^s/div (c) Output filtering inductance current itf (d)

uo: 50 V /div t: 500 ^s/div Output sinusoidal voltage uo

Fig. 7 Test waveforms of 1 kVA ASI

1994-2012 China Academic Journal Electronic Publishing House. All rights reserved, http://www.cnki.net

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CONCLUSIONS
Research conclusions have been obtained as fo

(5) technique

This

novel and

combined deepens

soft-switching soft-switching

extends

theories in power electronics.

llow s: (1) The validity of this novel ASI topology with high frequency pulse dc link is verified by the simulation and the test, and this ASI topology is of great value to the realization of high pow er density , high efficiency and l ow co st ASI. ( 2 ) T he operational principle of this topology and control strategy is carefully analyzed and studied. ( 3) The selection rules of key parameters are obtained. (4) The voltage-mode control strategy is
4 3 2 1 Hua Guichao, Leu Chingshan, Jiang Yimin, et al. N ov el z ero - r an si t io n PW M co nv ert er s. IE E E T r an s Power Electronics, 1994, 9( 2): 213219 H u a G ui ch ao, Y an g E ri c X, Ji ang Y im i n, et al. Novel z ero -cu rr ent - r an s it io n PW M co n ver t ers. IEEE Trans Power Electronics, 1994, 9(6): 601606 Di van D M. The res on an t DC l in k co nv ert er a new concept in static converter. IEEE IAS, 1986. 648 656 C hen Daol ian. Res ear ch on s o ft sw itching PWM combined aeronautical static inverter: [dissertation]. N an ji ng U n i ver si ty of Aer on au t i cs & As t r on au t ics, Nanjing, China, 1998. 27 37

REFERENCES

employed in the MISSC converter, and the three state DPM hysteresis current control strategy is employed in the inverter.

Ifx
( ) 2 1 0 0 1 6

96F52056)

S o

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