UNIVERSITY OF PETROLEUM & ENERGY STUDIES

COURSE PLAN
SUBJECT SUBJECT CODE CREDIT POINTS PREREQUISI TE SUBJECTS

Analog and Digital Electronics

PROGRAM ME SEMESTER

M.Tech (Robotics) I Aug2010- DEC2010 (16 Weeks) 60 Minutes

3 PHY101-102,MH101-102

DURATION SESSION DURATION

Faculty Member: Mr. Rajesh Singh

APPROVED BY:

(HOD) (DEAN)

PES Campus | Energy Acres| P.O. Bidholi via Prem Nagar| Dehradun248007(UK)

Tel: +91-135-2261090/91 | Fax: +91-135-2694204 | URL: www.upes.ac.in

COURSE PLAN
1.0 1.1 LEVEL OF KNOWLEDGE REQUIRED: PREREQUISITE Students should have basic knowledge of Engineering Mathematics, Engineering Physics, and basic electronics engineering. 1.2 CO-RE REQUISITE Student should have knowledge of electrostatics, electrodynamics, basic quantum mechanics, and mathematics concepts like differentiation, integration, and algebra. Students should also have basic knowledge of electrical and electronics circuit analysis as that would be helpful in understanding the concepts of various systems.

2.0

OBJECTIVES OF COURSE: After course completion the learners will be able: a) To understand the difference between Analog and Digital Circuits. b) To understand the applications of electronics devices like diodes and transistors in various electronic circuits. c) To understand the application of number system and Boolean algebra in electronics. d) To understand difference between Sequential and Combinational Circuits. e) Counter, register design using Flip-Flop.

3.0

SYLLABUS
The syllabus consists of the following major sections

Sl. No. 1.

Unit Unit I (Diode)

Contents Transport Phenomena in semiconductor, Formation of P-N Junction, Properties of P-N Junction, P-N Junction Diodes; Semiconductor Diodes, V-I Characteristics, Effect of Temperature on V-I Characteristics, Ideal Diode, Diode equation, Diode Resistance, Diode Capacitance: Transition and Diffusion Capacitance. Load line analysis of diode circuit, Half wave, Full wave & Bridge rectifier and its voltage regulation, ripple factor, ratio of rectification, Transformer Utilization Factor. Filter circuits for power supply: Inductor filter, Capacitor filter, LC filter, CLC or pi filter, Zener diode: Break down mechanism, Characteristics, Specifications, Voltage regulator circuit using zener diode. Introduction, Construction, Types: npn and pnp, Current components. Transistor as an amplifier, Transistor Characteristics, Transistor Circuit Configuration: Common Base (CB) Configuration, Common Emitter (CE) Configuration, Common Collector Configuration (CC), Early Effect. Ebers-Moll Model, Maximum Voltage Ratings. The operating point, Bias stability, Stability factor, Emitter Bias, Collector to base bias, Voltage divider bias with emitter bias, Emitter bypass capacitor. Bias compensation. Binary codes: Introduction & usefulness, Weighted & Non-weighted codes, Sequential codes, self complementing codes, Cyclic codes, 8-4-2-1 BCD code, Excess-3 code, Gray code: Binary to Gray and Gray to Binary code conversion, Error detecting code, Error correcting code, 7-bit Hamming code, ASCII code, EBCDIC code. Realization of Boolean Expressions: Reduction of Boolean expressions using laws, theorems and axioms of Boolean Algebra, Boolean expressions and logic diagram, Converting AND/OR/Invert logic to NAND/NOR logic, SOP and POS Forms and their Realization. Expansion of a Boolean expression to SOP form, Expansion of a Boolean expression to POS form, Two, Three & Four variable KMap: Mapping and minimization of SOP and POS expressions. Completely and Incompletely Specified Functions Concept of Dont Care Terms; Quine Mc Clusky Method. Adder & Subtractor: Half adder, Full adder, half subtractor, Full subtractor, Parallel Binary adder, Look Ahead carry adder, Serial adder, BCD adder. Code converter, Parity bit generator/Checker, Comparator. Decoder: 3-line to 8-line decoder, 8-4-2-1 BCD to

2.

Unit II (Transistor, Transistor Biasing & Thermal Stabilization)

3.

Unit III (Codes & Minimization Techniques)

4.

Unit IV (Combinational Circuits)

5.

Unit V (Sequential Circuits)

Decimal decoder, BCD to Seven segment decoder. Encoder: Octal to binary and Decimal to BCD encoder. Multiplexer: 2-input multiplexer, 4-input multiplexer, 16-input multiplexer. Demultiplexer: 1-lint to 4-line & 1-line to 8-line demultiplexer, Multiplexer as Universal Logic Function Generator, Programmed Array Logic (PAL). PLA and PLD. Flip-Flops &Timing Circuit: S-R Latch; Gated S-R Latch; D Latch; J-K Flip-Flop: Edge Triggered S-R, D, J-K and T Flips-Flops; Master Slave Flip-Flops, Direct Preset and Clear Inputs. Shift Registers; PIPO, SIPO, PISO, SISO, Bi-Directional Shift Registers; Universal Shift register. Counter: Asynchronous Counters: 4-bit Synchronous up counter, 4-bit synchronous down counter, Design of synchronous counters, Ring counter, Jhonson counter, Pulse train generator using counter, Design of Sequence Generators; Digital Clock using Counters.

4.0 PEDAGOGY: This course will be taught by lectures/analytical exercises focusing on fundamental concepts like Diodes, Transistors and also exercises focusing on fundamental concepts from general to specific first ideas, and then laws, followed by equations along with related tutorials problems. As there are no tutorial sessions for this course separately so analytical problems will be done along with the lectures. Students will undergo technical projects related to the subject. These projects will enhance their technical knowledge and creativity of the subject. Adequate emphasis will be given during lab periods in order to gain practical knowledge. Students will be motivated to take assignments/quiz and solve more numerical problems. Workbooks containing analytical problems will available be on course LMS to the students for further practice.

5.0

EVALUATION OF GRADING: Students will be evaluated based on the following 3 stages. 5.1 5.2 5.3 Internal Assessment Mid term Examination End term Examination 30% 20% 50%

5.1.

INTERNAL ASSESSMENT: WEIGHTAGE 30% Internal Assessment shall be done based on the following:

Sl. No. 1 2 3

Description Class Tests/Quizzes Assignments (Problems/Presentations) General Discipline

% of Weightage out of 30%

Sole Discretion of the Teacher

Internal Assessment Record Sheet (including Mid Term Examination marks) will be displayed on LMS at the end of semester i.e. last week of regular classroom teaching.

5.1.1 CLASS TESTS/QUIZZES: Two Class Tests based on descriptive type theoretical & numerical questions and Two Quizzes based on objective type questions will be held; one class test and one quiz atleast ten days before the Mid Term Examination and second class test and second quiz atleast ten days before the End Term Examination. Those who do not appear in Viva-Voce and quiz examinations shall lose their marks.

The marks obtained by the students will be displayed on LMS a week before the start of Mid Term and End Term Examinations respectively.

5.1.2 ASSIGNMENTS: After completion of each unit or in the mid of the unit, there will be home assignments based on theory and numerical problems. Those who fail to submit the assignments by the due date shall lose their marks.

The marks obtained by the students will be displayed on LMS after each submission and subsequent evaluation.

5.1.3 GENERAL DISCIPLINE: Based on students regularity, punctuality, sincerity and behaviour in the class.

The marks obtained by the students will be displayed on LMS at the end of semester.

5.2.

MID TERM EXAMINATION: WEIGHTAGE 20% Mid Term examination shall be Two Hours duration and shall be a combination of Short and Long theory Questions.

Date of showing Mid Term Examination Answer Sheets: Oct. 26/27, 2010

5.3.

END TERM EXAMINATION: WEIGHTAGE 50% End Term Examination shall be Three Hours duration and shall be a combination of Short and Long theory/numerical Questions.

6.0

GRADING: The overall marks obtained at the end of the semester comprising all the above three mentioned shall be converted to a grade.

7.0.

ATTENDANCE: Students are required to have a minimum attendance of 75% in the subject. Students with less than the stipulated percentage shall not be allowed to appear in the End Term Examination DETAILED SESSION PLAN No. of Pedag Sessi ogy ons 08 Lectur Detail of Referen ces T1(49Coverage Pictorial Depiction(i f any) Phenomena in

8.0 S.N o

Transport

er

114) R8(113173) R9(83240)

semiconductor, Formation of P-N Junction, Properties of P-N Junction, P-N Junction Diodes; Semiconductor Diodes, V-I Characteristics, Effect of Temperature on V-I Characteristics, Ideal Diode, Diode equation, Diode Resistance, Diode Capacitance: Transition and Diffusion Capacitance. Load line analysis of diode circuit, Half wave, Full wave & Bridge rectifier and its voltage regulation, ripple factor, ratio of rectification, Transformer Utilization Factor. Filter circuits for power supply: Inductor filter, Capacitor filter, LC filter, CLC or pi filter, Zener diode: Break down mechanism, Characteristics, Specifications, Voltage regulator circuit using zener diode. Introduction, Construction, Types: npn and pnp, Current components. Transistor as an amplifier, Transistor Characteristics, Transistor Circuit Configuration: Common Base (CB) Configuration, Common Emitter (CE) Configuration, Common Collector Configuration (CC), Early Effect. Ebers-Moll Model, Maximum Voltage Ratings. The operating point, Bias stability, Stability factor, Emitter Bias, Collector to base bias, Voltage divider bias with emitter bias, Emitter bypass capacitor. Bias compensation. Binary codes: Introduction & usefulness, Weighted & Nonweighted codes, Sequential

07

Lectur er

T1(118149,282 -316) R8(174243) R9(247311)

05

Lectur er

T3 R10(199)

R11(1120)

codes, self complementing codes, Cyclic codes, 8-4-2-1 BCD code, Excess-3 code, Gray code: Binary to Gray and Gray to Binary code conversion, Error detecting code, Error correcting code, 7-bit Hamming code, ASCII code, EBCDIC code. Realization of Boolean Expressions: Reduction of Boolean expressions using laws, theorems and axioms of Boolean Algebra, Boolean expressions and logic diagram, Converting AND/OR/Invert logic to NAND/NOR logic, SOP and POS Forms and their Realization. Expansion of a Boolean expression to SOP form, Expansion of a Boolean expression to POS form, Two, Three & Four variable K-Map: Mapping and minimization of SOP and POS expressions. Completely and Incompletely Specified Functions Concept of Dont Care Terms; Quine Mc Clusky Method. Adder & Subtractor: Half adder, Full adder, half subtractor, Full subtractor, Parallel Binary adder, Look Ahead carry adder, Serial adder, BCD adder. Code converter, Parity bit generator/Checker, Comparator. Decoder: 3-line to 8-line decoder, 8-4-2-1 BCD to Decimal decoder, BCD to Seven segment decoder. Encoder: Octal to binary and Decimal to BCD encoder. Multiplexer: 2-input multiplexer, 4-input multiplexer, 16-input multiplexer. Demultiplexer: 1-lint to 4-line & 1-line to 8-line

06

Lectur er

T3 R10(111 -147) R11(131 -246)

demultiplexer, Multiplexer as Universal Logic Function Generator, Programmed Array Logic (PAL). PLA and PLD. 5 06 Lectur er T3 R10(167 -244) R11(281 -388) Flip-Flops &Timing Circuit: S-R Latch; Gated S-R Latch; D Latch; J-K Flip-Flop: Edge Triggered S-R, D, J-K and T Flips-Flops; Master Slave Flip-Flops, Direct Preset and Clear Inputs. Shift Registers; PIPO, SIPO, PISO, SISO, BiDirectional Shift Registers; Universal Shift register. Counter: Asynchronous Counters: 4-bit Synchronous up counter, 4-bit synchronous down counter, Design of synchronous counters, Ring counter, Jhonson counter, Pulse train generator using counter, Design of Sequence Generators; Digital Clock using Counters.

9.0

Suggested Reading Name of Reference Books R1. Electronic Devices & Circuit David A. Bell, PHI R2 Electronic Devices & Circuit Allen Mottershead, PHI R3 Electronic Devices & Circuit Theory Boylestad & Nashelsky, 8th Ed. PHI R4 Electronic Devices & Circuit Analysis K. Lal Kishore, BS Publications R5 Digital Fundamentals: Floyd & Jain: Pearson Education R6 Digital Electronics: A.P. Malvino:

Name of Text Books T1. Integrated Electronics Millman & Halkias, TMH. T2 Microelectronics Millman and Grabel, TMH. T3 Fundamentals of Digital Circuits A. Anand Kumar, PHI. T4 Digital Integrated Electronics: H. Taub and D. Schilling: TMH.

TMH. R7 Digital Circuits & Logic Design LEE, PHI R8.Principal of electronics-V.K MehtaS.Chand &co ltd

R9.Electronics Devices and Millman & Halkias II Ed-TMH

Circuits-

R10.Digital DesignIII -M.Morris Mano-PHI R11.Digital Principle & Application 5Leach,Malvino-PHI

10.0 OTHER RESOURCES 10.1 Video Resources 10.2 Web Resources www.allaboutcircuits.com www.electronicsfor you.com

11.0 Major and Minor Projects Design of power supply for 12V, 500mA with r.f .001. Design of BJT as an amplifier with 9V output voltage swing. Design of FET as an amplifier with 9V output voltage swing.