Q1. Write an assembly language program to find the highest among two numbers.

Program MVI B, 30H MVI C, 40H MOV A, B CMP C JZ EQU JC GRT OUT PORT1 HLT EQU: MVI A, 01H OUT PORT1 HLT GRT: MOV A, C OUT PORT1 HLT 2. Draw and explain the internal architecture of 8085. 8085 System Bus Typical system uses a number of busses, collection of wires, which transmit binary numbers, one bit per wire. A typical microprocessor communicates with memory and other devices (input and output) using three busses: Address Bus, Data Bus and Control Bus.

Address Bus One wire for each bit, therefore 16 bits = 16 wires. Binary number carried alerts memory to open the designated box. Data (binary) can then be put in or taken out. The Address Bus consists of 16 wires, therefore 16 bits. Its Width is 16 bits. A 16 bit Binary number allows 216 different numbers or 32000 different numbers, i.e. 0000000000000000 up to 1111111111111111.Because memory consists of boxes, each with a unique address, the size of the address bus determines the

size of memory, which can be used. To communicate with memory the microprocessor sends an address on the address bus, e.g. 0000000000000011 (3 in decimal), to the memory. The memory selects box number 3 for reading or writing data. Address bus is unidirectional, i.e numbers only sent from microprocessor to memory, not other way. Data Bus Data Bus: carries data, in binary form, between microprocessor and other external units, such as memory. Typical size is 8 or 16 bits. The Data Bus typically consists of 8 wires. Therefore, 28 combinations of binary digits. Data bus used to transmit data, i.e. information, results of arithmetic, etc, between memory and the microprocessor. Bus is bi-directional. Size of the data bus determines what arithmetic can be done. If only 8 bits wide then largest number is 11111111 (255 in decimal). Therefore, larger numbers have to be broken down into chunks of 255. This slows micro processor. Data Bus also carries instructions from memory to the microprocessor. Size of the bus therefore limits the number of possible instructions to 256, each specified by a separate number. Control Bus Control Bus are various lines which have specific functions for coordinating and controlling microprocessor operations. Eg: Read/Not Write line, single binary digit. Controls whether memory is being written to (data stored in mem) or read from (data taken out of mem) 1 = Read, 0 = Write. May also include clock line(s) for timing/ synchronizing, interrupts, reset etc. Typically microprocessor has 10 control lines. Cannot function correctly without these vital control signals. CPU Architecture Control Unit Generates signals within microprocessor to carry out the instruction, which has been decoded. In reality causes certain connections between blocks of the microprocessor to be opened or closed, so that data goes where it is required, and so that ALU operations occur. Arithmetic Logic Unit The ALU performs the actual numerical and logic operation such as add, subtract, AND, OR, etc. Uses data from memory and from Accumulator to perform arithmetic. Always stores result of operation in Accumulator. Registers The 8085/8080A-programming model includes six registers, one accumulator, and one flag register, as shown in Fig. 2.1 In addition, ithas two 16-bit registers: the stack pointer and the program counter. They are described briefly as follows. The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified as B,C,D,E,H and L as shown in the figure. Q3. Explain the concept of Linking and Relocation. Linking and Relocation In constructing a program some program modules may be put in the same source module and assembled together; others may be in different source modules and assembled separately. If they are assembled separately, then the main module, which has the first instruction to be executed, must be terminated by an END statement with the entry point specified, and each of the other modules must be terminated by an END statement with no operand. In any event, the resulting object modules, some of which may be grouped into libraries, must be linked together to form a load module before the program can be executed. In addition to outputting the load module, normally the linker prints a memory map that indicates where the linked object modules will be loaded into memory. After the load module has been created it is loaded into the memory of the computer by the loader and execution begins. Although the I/O can be performed by modules within the program, normally the I/O is done by I/O drivers that are part of the operating system. All that appears in the us ers program are references to the I/O drivers that cause the operating system to execute them. The general process for creating and executing a program is illustrated in Fig 5.1. The process for a particular system may not correspond exactly to the one diagrammed in the figure, but the general concepts are the same. The arrows indicate that corrections may be made after anyone of the major stages.

Fig. 5.1: Creation and Execution of a program Segment Combination In addition to the linker commands, the ASM-86 assembler provides a means of regulating the way segments in different object modules are organized by the linker. Sometimes segments with the same name are concatenated and sometimes they are overlaid. Just how the segments with the same name are joined together is determined by modifiers attached to the SEGMENT directives. A SEGMENT directive may have the form Segment name SEGMENT Combine-type where the combine-type indicates how the segment is to be located within the load module. Segments that have different names cannot be combined and segments with the same name but no combine-type will cause a linker error. The possible combine-types are: PUBLIC-If the segments in different object modules have the same name and the combine-type PUBLIC, then they are concatenated into a single segment in the load module. The ordering in the concatenation is specified by the linker command. COMMON-If the segments in different object modules have the same name and the combine-type is COMMON, then they are overlaid so that they have the same beginning address. The length of the common segment is that of the longest segment being overlaid. STACK-If segments in different object modules have the same name and the combine-type STACK, then they become one segment whose length is the sum of the lengths of the individually specified segments. In effect, they are combined to form one large stack. AT-The AT combine-type is followed by an expression that evaluates to a constant which is to be the segment address. It allows the user to specify the exact location of the segment in memory.. MEMORY-This combine-type causes the segment to be placed at the last of the load module. If more than one segment with the MEMORY combine type is being linked, only the first one will be treated as having the MEMORY combine-type; the others will be overlaid as if they had COMMON combine types. Access to External Identifiers Clearly, object modules that are being linked together must be able to refer to each other. That is, there must be a way for a module to reference at least some of the variables and/or labels in the other modules. If an identifier is defined in an object module, then it is said to be a local (or internal) identifier relative to the module, and if it is not defined in the module but is defined in one of the other modules being linked, then It is referred to as an external (or global) identifier relative to the module. For single-object module programs all identifiers that are referenced must be locally defined or an assembler error will occur. For multiple-module programs, the assembler must be informed in advance of any externally defined identifiers that appear in a module so that it will not treat them as being undefined. Also, in order to permit other object modules to reference some of the identifiers in a given module, the given module must include a list of the identifiers to which it will allow access. Therefore, each module may contain two lists, one containing the external identifiers it references and one containing the locally defined identifiers that can be referred to by other modules. These two lists are implemented by the EXTRN and PUBLIC directives, which have the forms: EXTRN Identifier: Type, . . . , Identifier: Type

and PUBLIC Identifier, . . ., Identifier where the identifiers are the variables and labels being declared as external or as being available to other modules. Because the assembler must know the type of all external identifiers before it can generate the proper machine code, a type specifier must be associated with each identifier in an EXTRN statement. For a variable the type may be BYTE, WORD, or DWORD and for a label it may be NEAR or FAR. In the statement INC VAR1 if VAR1 is external and is associated with a word, then the module containing the statement must also contain a directive such as EXTRN . . VAR1 :WORD.. . . and the module in which VARl is defined must contain a statement of the form PUBLIC .. ..VAR1. One of the primary tasks of the linker is to verify that every identifier appearing in an EXTRN statement is matched by one in a PUBLIC statement. If this is not the case, then there will be an undefined external reference and a linker error will occur. Fig. 5.2 shows three modules and how the matching is done by the linker while joining them together.

Fig. 5.2: Illustration of the matching verified by the linker As we have seen, there are two parts to every address, an offset and a segment address. The offsets for the local identifiers can be and are inserted by the assembler, but the offsets for the external identifiers and all segment addresses must be inserted by the linking process. The offsets associated with all external references can be assigned once all of the object modules have been found and their external symbol tables have been examined. The assignment of the segment addresses is called relocation and is done after the king process has determined exactly where each segment is to be put in memory. Q4. Define macros and procedures. In what way is Procedures better than macros. A macro is a group of repetitive instructions in a program which are codified only once and can be used as many times as necessary. The main difference between a macro and a procedure is that in the macro the passage of parameters is possible and in the procedure it is not, this is only applicable for the MASM - there are other programming languages which do allow it. At the moment the macro is executed each parameter is substituted by the name or value specified at the time of the call. We can say then that a procedure is an extension of a determined program, while the macro is a module with specific functions which can be used by different programs. Another difference between a macro and a procedure is the way of calling each one, to call a procedure the use of a directive is required, on the other hand the call of macros is done as if it were an assembler instruction. Example of procedure: For example, if we want a routine which adds two bytes stored in AH and AL each one, and keep the addition in the BX register:

Adding Proc Near ; Declaration of the procedure Mov Bx, 0 ; Content of the procedure Mov B1, Ah Mov Ah, 00

Add Bx, Ax Ret ; Return directive Add Endp ; End of procedure declaration and an example of Macro: Position MACRO Row, Column PUSH AX PUSH BX PUSH DX MOV AH, 02H MOV DH, Row MOV DL, Column MOV BH, 0 INT 10H POP DX POP BX POP AX ENDM Q5. Explain the function of any 3 flag of a 8086 flag register with examples. 8086 CPU has 8 general purpose registers, each register has its own name: AX - the accumulator register (divided into AH / AL): 1. Generates shortest machine code 2. Arithmetic, logic and data transfer 3. One number must be in AL or AX 4. Multiplication & Division 5. Input & Output BX - the base address register (divided into BH / BL). CX - the count register (divided into CH / CL): 1. Iterative code segments using the LOOP instruction 2. Repetitive operations on strings with the REP command 3. Count (in CL) of bits to shift and rotate DX - the data register (divided into DH / DL): 1. DX:AX concatenated into 32-bit register for some MUL and DIV operations 2. Specifying ports in some IN and OUT operations SI - source index register: 1. Can be used for pointer addressing of data 2. Used as source in some string processing instructions 3. Offset address relative to DS DI - destination index register: 1. Can be used for pointer addressing of data 2. Used as destination in some string processing instructions 3. Offset address relative to ES BP - base pointer: 1. Primarily used to access parameters passed via the stack 2. Offset address relative to SS SP - stack pointer: 1. Always points to top item on the stack 2. Offset address relative to SS 3. Always points to word (byte at even address) 4. An empty stack will had SP = FFFEh SEGMENT REGISTERS CS - points at the segment containing the current program. DS - generally points at segment where variables are defined. ES - extra segment register, it's up to a coder to define its usage. SS - points at the segment containing the stack.

Although it is possible to store any data in the segment registers, this is never a good idea. The segment registers have a very special purpose - pointing at accessible blocks of memory. Segment registers work together with general purpose register to access any memory value. For example if we would like to access memory at the physical address 12345h (hexadecimal), we could set the DS = 1230h and SI = 0045h. This way we can access much more memory than with a single register, which is limited to 16 bit values. The CPU makes a calculation of the physical address by multiplying the segment register by 10h and adding the general purpose register to it (1230h * 10h + 45h = 12345h):

The address formed with 2 registers is called an effective address. By default BX, SI and DI registers work with DS segment register; BP and SP work with SS segment register. Other general purpose registers cannot form an effective address. Also, although BX can form an effective address, BH and BL cannot. SPECIAL PURPOSE REGISTERS IP - the instruction pointer: 1. Always points to next instruction to be executed 2. Offset address relative to CS IP register always works together with CS segment register and it points to currently executing instruction. FLAGS REGISTER Flags Register - determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. Generally you cannot access these registers directly.

1. 2. 3. 4. 5. 6. 7. 8. 9.

Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow. For example when you add bytes 255 + 1 (result is not in range 0...255). When there is no overflow this flag is set to 0. Parity Flag (PF) - this flag is set to 1 when there is even number of one bits in result, and to 0 when there is odd number of one bits. Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow for low nibble (4 bits). Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this flag is set to 0. Sign Flag (SF) - set to 1 when result is negative. When result is positive it is set to 0. (This flag takes the value of the most significant bit.) Trap Flag (TF) - Used for on-chip debugging. Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to interrupts from external devices. Direction Flag (DF) - this flag is used by some instructions to process data chains, when this flag is set to 0 - the processing is done forward, when this flag is set to 1 the processing is done backward. Overflow Flag (OF) - set to 1 when there is a signed overflow. For example, when you add bytes 100 + 50 (result is not in range -128...127).

Q6. What are the advantages of the MOVS and CMPS instructions over the MOV and CMP instructions? Explain.

When working with strings, the advantages of the MOVS and CMPS instructions over the MOV and CMP instructions are: 1. They are only 1 byte long. 2. Both operands are memory operands. 3. Their auto-indexing obviates the need for separate incrementing or decrementing instructions, thus decreasing overall processing time. As an example consider the problem of moving the contents of a block of memory to another area in memory. A solution that uses only the MOV instruction, which cannot perform a memory-to-memory transfer, is shown in Fig. 6.2(a).

Fig. 6.2: Program sequences for moving a block of data A solution that employs the MOVS instruction is given in Fig. 6.2(b). Note that the second program sequence may move either bytes or words, depending on the type of STRING1 and STRING2.

Q9. Explain the 8288 Bus controller. For reasons of simplicity, flexibility, and low cost, most microcomputers, including those involving multiprocessor configurations, are built around a primary system bus which connects all of the major components in the system. In order to obtain a foundation while designing its products, a microcomputer manufacturer makes assumptions about the bus that is to be used to connect its devices together Frequently, these assumptions become formalized and constitute what is referred to as a bus standard The Intel MULTIBUS has gained wide industrial acceptance and several manufacturers offer MULTIBUS-compatible modules. This bus is designed to support both 8-bit and 16-bit devices and can be used in multiprocessor systems in which several processors can be masters. At any point in time, only two devices may communicate with each other over the bus, one being the master and the other the slave. The master/slave relationship is dynamic with bus allocation being accomplished through the bus allocation (i.e., request/grant) control signals. The MULTIBUS has been physically implemented on an etched backplane board which is connected to each module using two edge connectors, denoted PI and P2, I shown in Fig. 9.13. The connector P1 consists of 86 pins which provide-the major bus signals, and P2 is an optional connector consisting of 60 auxiliary lines, primarily used for power failure detection and handling.

Fig. 9.13: Illustration of a module being plugged into MULTIBUS The P1 lines can be divided into the following groups according to their functions: 1. Address lines. 2. Data lines. 3. Command and handshaking lines. 4. Bus access control lines. 5. Utility lines. The MULTIBUS has 20 address lines, labeled through , where the numeric suffix represents the address bit in hexadecimal. The address lines are driven by the bus master to specify the memory location or I/O port being accessed.. The MULTIBUS standard calls for all single bytes to be communicated over only the lower 8 bits of the bus; therefore, any 16-bit interface must include a swap byte buffer so that only the lower data lines are used for all byte transfers. (It should be pointed out that because an 8086 expects a byte to be put on the high-order byte of the bus when is active, one may want to permit nonstandard MULTIBUS transfers between memory and an 8086.) The two inhibit signals are provided for overlaying RAM, ROM, and auxiliary ROM in a common address space. For example, a bootstrap loader may be stored in an auxiliary ROM and a monitor in a ROM. Because the loader is needed only after a reset, and could both be activated while the loader is executing. Then, when the monitor is in control, and could be

raised while remains low. If control is passed to the user, RAM to fill the entire memory space during normal operation.

could both be deactivated, thus allowing the

There are 16 bidirectional data lines ( ), only eight of which are used in an 8-bit system. Data transfers on the MULTIBUS bus are accomplished by handshaking signals in a manner similar to that described in the preceding sections. The memory read ( ), memory write ( ), I/O read ( ), and I/O write ( ) lines are defined to be the same as

they were in the discussion of the 8288 bus controller. There is an acknowledge ( ) signal which serves the same purpose as the READY signal in the discussion of the bus control logic, i.e., to verify the end of a transfer. In a general setting it may be received by bus master. Because a master must wait to be notified of the completion transfer, the duration of a bus cycle varies depending on the speed of the bus master and the slave. This asynchronous nature enables the system to handle slow devices without penalizing fast devices