Code No: NR320404

NR

Set No. 2

III B.Tech II Semester Examinations,APRIL 2011 VLSI TECHNOLOGY Common to Electronics And Telematics, Electronics And Communication Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) What is Moores Law? Explain its relevance with respect to evolution of IC technology. (b) What is the size of Silicon wafer currently used for the manufacture of ICs? (c) What is the current commercial device feature size? 2. Write short note on: (a) MOS transistor gure of merit (b) Delays in Bi CMOS inverters (c) Super buers
(d) CMOS latch susceptibility. [4 4]

[12+2+2]

3. (a) Explain Test vector generation pertaining to VSLI design. (b) Explain about Built in Self test (BIST). 4. (a) Discuss in detail semi-custom layout styles. (b) Explain in detail about the congurable logic blocks. [8+8] [8+8]

5. Briey explain circuit synthesis in ASIC design ow. What are pre and post layout simulations? [16] 6. List the classes of circuits for which standard cell libraries are created. Give a typical standard cell structure and explain its features . [16]

7. (a) Prove that the combination of BJT and MOS technology oers the best performance in Analog VLSI design. (b) Draw the block diagram of D/A converter suitable for VLSI Analog Circuits and explain. [8+8] 8. (a) What types of materials are used for high power applications of ceramic based package. (b) Explain the dierent types of packages in detail. [6+10]

Code No: NR320404

NR

Set No. 4

III B.Tech II Semester Examinations,APRIL 2011 VLSI TECHNOLOGY Common to Electronics And Telematics, Electronics And Communication Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Explain Test vector generation pertaining to VSLI design. (b) Explain about Built in Self test (BIST). 2. (a) Discuss in detail semi-custom layout styles. (b) Explain in detail about the congurable logic blocks. [8+8] [8+8]

3. (a) What types of materials are used for high power applications of ceramic based package.

(b) Explain the dierent types of packages in detail. 4. Write short note on:
(a) MOS transistor gure of merit (b) Delays in Bi CMOS inverters

[6+10]

(c) Super buers (d) CMOS latch susceptibility. [4 4]

5. List the classes of circuits for which standard cell libraries are created. Give a typical standard cell structure and explain its features . [16] 6. Briey explain circuit synthesis in ASIC design ow. What are pre and post layout simulations? [16]

7. (a) Prove that the combination of BJT and MOS technology oers the best performance in Analog VLSI design. (b) Draw the block diagram of D/A converter suitable for VLSI Analog Circuits and explain. [8+8] 8. (a) What is Moores Law? Explain its relevance with respect to evolution of IC technology. (b) What is the size of Silicon wafer currently used for the manufacture of ICs? (c) What is the current commercial device feature size? [12+2+2]

Code No: NR320404

NR

Set No. 1

III B.Tech II Semester Examinations,APRIL 2011 VLSI TECHNOLOGY Common to Electronics And Telematics, Electronics And Communication Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. List the classes of circuits for which standard cell libraries are created. Give a typical standard cell structure and explain its features . [16] 2. Write short note on: (a) MOS transistor gure of merit (b) Delays in Bi CMOS inverters (c) Super buers (d) CMOS latch susceptibility. [4 4]

3. (a) Prove that the combination of BJT and MOS technology oers the best performance in Analog VLSI design. (b) Draw the block diagram of D/A converter suitable for VLSI Analog Circuits and explain. [8+8] 4. (a) Explain Test vector generation pertaining to VSLI design. (b) Explain about Built in Self test (BIST). [8+8]

5. Briey explain circuit synthesis in ASIC design ow. What are pre and post layout simulations? [16] 6. (a) What types of materials are used for high power applications of ceramic based package. (b) Explain the dierent types of packages in detail. [6+10]

7. (a) What is Moores Law? Explain its relevance with respect to evolution of IC technology. (b) What is the size of Silicon wafer currently used for the manufacture of ICs? (c) What is the current commercial device feature size? 8. (a) Discuss in detail semi-custom layout styles. (b) Explain in detail about the congurable logic blocks. [8+8] [12+2+2]

Code No: NR320404

NR

Set No. 3

III B.Tech II Semester Examinations,APRIL 2011 VLSI TECHNOLOGY Common to Electronics And Telematics, Electronics And Communication Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) What types of materials are used for high power applications of ceramic based package. (b) Explain the dierent types of packages in detail. [6+10]

2. Briey explain circuit synthesis in ASIC design ow. What are pre and post layout simulations? [16] 3. Write short note on: (a) MOS transistor gure of merit (b) Delays in Bi CMOS inverters
(c) Super buers

(d) CMOS latch susceptibility. 4. (a) Discuss in detail semi-custom layout styles. (b) Explain in detail about the congurable logic blocks.

[4 4]

[8+8]

5. List the classes of circuits for which standard cell libraries are created. Give a typical standard cell structure and explain its features . [16] 6. (a) What is Moores Law? Explain its relevance with respect to evolution of IC technology. (b) What is the size of Silicon wafer currently used for the manufacture of ICs? (c) What is the current commercial device feature size? 7. (a) Explain Test vector generation pertaining to VSLI design. (b) Explain about Built in Self test (BIST). [8+8] [12+2+2]

8. (a) Prove that the combination of BJT and MOS technology oers the best performance in Analog VLSI design. (b) Draw the block diagram of D/A converter suitable for VLSI Analog Circuits and explain. [8+8]