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12-1-1997

A model for leakage control by MOS transistlor stacking

Mark C. Johnson
Purdue University School of Electrical and Computer Engineering

Dinesh Somasekhar
Purdue University School of Electrical and Computer Engineering

Kaushik Roy
Purdue University School of Electrical and Computer Engineering

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Johnson, Mark C.; Somasekhar, Dinesh; and Roy, Kaushik, "A model for leakage control by MOS transistlor stacking" (1997). ECE Technical Reports. Paper 79. http://docs.lib.purdue.edu/ecetr/79

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A MODEL FOR LEAKAGE CONTI~OL BY MOS TRANSISTOR STACKING

TR-ECE 97-12 DECEMBER 1997

A model for leakage control by MOS transistlor

stacking
Mark C. Johnson, Dinesh Somasekhar, and Iiaushik Roy School of Electrical and Computer Engineering Purdue University, West Lafayette, Indiana, 47907-1285, USA Phone: (765)494-3372, (765)494-3372, (765)494-2361 Ernail: {mcjohnso. somasekh. kaushik:Qecn.purdue.edu}

'This research was supported in part by ARPA (F33615-95-C-162.5), NSF CAREER award (950 1869-MIP) , IBhl, Rockwell, .Tk?'/Lucent, and ASSERT program I DAAH0496-1-0222).

Abstract
Prevailing CMOS design practice has been very conservative with regard t o choice of transistor threshold voltage, s o a s t o avoid t h e difficult problems of threshold variations and high leakage currclnts. It is becoming necessary t o scale threshold voltages more aggress~vely in order t o obtain further power reduction, performance improven~ent, and integration density. Substantial leakage reduction can be a c h i ~ v e d in single V t designs by stacking low \.'t transistors. We have derived a simplified theoretical model which predicts t h e quiescent leakage current and t h e worst case time required t o settle t o quiescent levels in a single stack of transistors. This model can be used in a design environment t o make quick estimation of leakage with respect t o design changes. Model results are compared t o circuit sirnulation. Leakage current predictions were found t o rnatch simulation results very closely for a wide random selection of design parameter values and temperatures. Transistor stacks with mt~ltipletransistors turned off were found t o have anywhere from 2 t o 30 times lower leakage current than stack with only one transistor turned off. The time requirecl for a transistor stack t o settle t o quiescent current levels varied from a few microseconds up t o tens of milliseconds.

1 Introduction

1.1 1.2

Sources of leakage . . . . . . . . . . . . . . . . . . . . . . . . . Simple example of leakage behavior . . . . . . . . . . . . . . .

1 2
5 5

2 Effect of stack height on quiescent leakage

2.1

Theoretical h.Zoclel . . . . . . . . . . . . . . . . . . . . . . . . . Sensitivity to process and other variations

2.2 2.3

. . . . . . . . . . .

8
9

Simulation a11cl theoretical model results . . . . . . . . . . . .

2.4 Sensitivity of model to transistor characterization . . . . . . . 10

3 Leakage transients
12

3.1 3.2

Theoretical model . . . . . . . . . . . . . . . . . . . . . . . . .

13

Simulation and theoretical model results . . . . . . . . . . . . 17

3.3 Sensitivity to process and other parameters . . . . . . . . . . . 19 3.4 Energy cost associated with leakage transients . . . . . . . . . 19 3 ..5 Exploiting the stacking effect
4 Conclusions

. . . . . . . . . . . . . . . . . . 20
21

List of Figures
1
SimpleSANDgate . . . . . . . . . . . . . . . . . . . . . . . . Leakage behavior of pull down network in S A N D gate 2

. . . .

3
4
5

Schematic and notatmion for stacking effect analysis . . . . . . .

Correlation of simulated and estimated leakage . . . . . . . . . 11 Correlation of simulated and estimated leakage savings . . . . 12 Transistors ancl capacitarlces affecting internal node i . . . . . 15 Discharge of internal node capacitances . . . . . . . . . . . . . 16 Correlation of simulated and estimated settling time . . . . . . 18

6
" I

Introduction

,411accurate estimate of standby leakage power must consider circuit topology as well as signal levels when t h e circuit is idle. Kawahara [5] clemonstrated this in the design of a low power decoded-dri~rers for a DRAM. ,4n evtra transi~tor was placed between the supply line ancl the pull-up t r a n s i s t ~ r for the driver. This causes a slight reverse bias between the gate and source of the pt~ll-up transistor when both transistors are turned off. Because subthreshold current is exponentially dependent on gate bias, a substantial current reduction was obtained. This phenorllenon is referred to as the "stacking eflect ". In this paper we derive a more general model of t h e stacking effect with respect t o subthreshold current reduction and the time required to settle t o quiescent current levels. This model considers the general case of transistor stacks with an arbitrary number of transistors. It takes into account both body effect and drain induced barrier lowering (DIBL). DIBL (retluction of threshold voltage as IfDs increases) is especially significant for sub-micron devices. T h e leakage of a transistor stack is shown t o be directly tlependent on t h e magnitude of t h e DIBL effect.

Sources of leakage

In current and near future hlOS technologies, t h e dominant component of leakage current is subthreshold current [6]. Shrinking transistoi. size has greatly irlcreased subthreshold current while reducing junction diotle leakage which was a dominant leakage component in earlier technologies. As di-

n~ensions continue to shrink. other causes of leakage may become significant. At present, gate induced drain leakage (GIDL) poses the greatest threat t o leakage control by means of transistor stacking. GIDL is largest when VDs is largest and is strongly reverse biased. The stacking effect relies on

reverse biasing of VGsto achieve leakage savings. Conseyuently, GIDL may become a lower bound on leakage in the future.

1. 2

Simple example of leakage behavior

VDD

Figure 1: Simple NAND gate Before presenting the leakage model in detail, let us exanline a very simple ca:;e where the stacking effect becomes significant. Figure 1 depicts a simple static two input NAND gate. We would like t o understand the leakage llehavior of this gate for various inputs. In the case where both Phl OS transistors are turned off, the leakage is simply t h e sun1 of the off c ~ ~ r r e n of ts each P hlOS device. However, the situation for series connected transistors

is more cornplex. Figure 2 d e m ~ n s t r a t ~ what es happens t,o the internal node vc)ltages ancl currents when only the bottom NMOS transistor is initially off and then the upper NMOS transistor is turned off.

h logarit'hmic time axis

is used t'o make it ea,sier to compa,re initial a,nd final conditions which are separa,ted by a wide time interval. Initially, the supply ancl ground line leakag;e current's are equal t o the off current of a sirigle transistor. As soon as the gate of the top transistor is switched off, there is an imn1ediai;e drop
i11

internal node voltage due to capacitive coupling (bootstrapping). After bootsti:apping, the internal node voltage is discharged only very slowly since the only discharge mechanism is the off c u r r e ~ ~ through t the bottom t,ransistor. Notice that while the internal node is discharging, leakage from tlhe supply voltage line is negiligible. This is due t o t h e strong reverse bias between the gatme and source of the t'op transistor. Once the internal node voltcagereaches its quiescent level, then the supply and ground
current,^

reach equilibrium

a t a reduced quiescent current level. In the remainder of this paper, we will derive expressions which model t h e leakage behavior of stacks consisting of an arbitra.ry number of transistors. The model will predict quiescerit current' and voltage levels and the worst case "settling" time required t o 1:ransition to new quiescent levels aft,er switching off one or more transistors.

Gate voltage to top transista~

Internal node voltage

Bmtstrapp~ng

D~schargtng of ~nternal node

I 1

200m

Quiescent Volt,lge

56mV

1n

1On

1O O n lu T~me (log) (TIME) VDD and Ground Currents

1O u

1O O L

W a v e Symbol D O A0 x~gnd D O A0 xtvdd

1u 1om

1O P

I (VDD)

-"--"

1n

1On

..

..

loon lu Time (log) (TIME)

1O u

1001

""""

..

.....

...

Figure

2: Leakage behavior of pull down network in N A N D gate

2
2.1

Effect of stack height on quiescent leakage

Theoretical Model
Vdd

vgi

Isubth

Figure 3: Schematic and notation for stacking effect analysis Let Figure 3 depict a transistor stack to be analyzed. Steady stal e leakage values can be estimated as a function of the number of transistor; that are turned off. Details of the derivation can be found in the appendix. The general approach is t o equate the subthreshold current through each transi:,tor and then solve for the quiescent voltage

(I.bs,,)across each transistor.

Throughout this paper, a "q" in a subscript indicates a quiescent value. Tliese voltages can then be used estimate the magnitude of the leakage cur-

rent. T h e following analysis is done for an NMOS pull down stalzk, but is ecually applicable to a PMOS stack. The subthreshold current of the ith MOS transistor in a stack can be modeled as

W k where A = poCL,G(T)

T 2 1 8

-a v

nu:H.

Equation 1 is adapted from the

BSIM 2 MOS transistor model [8, 31. VTHois the zero bias threshold voltage.
v.1, is

the thermal voltage

.:

The body effect for small values of lls is very

nearly linear. It is represented by the term ylVs, where y ' is the linearized body effect coefficient. 77 is the DIBL coefficient, representing the effect of

Kls

(VDs = VD - Vs) on threshold voltage. C,, is the gate oxicle capaci-

tance. po is the zero bias mobility. n is the subthreshold swing coefficient of the transistor. AVTH accounts for variations in threshold voltage from one transistor to another. For the conditions illustrated in figure 3, all transistors are turned off with VG = 0. First we equate the currents of the first and second transistors in the stack.
V C e obtain equation 2 by solving for VDs2 in terms of VDD, as described in

the appendix. It is assumed here that VDD >> Vsql so that we can calculate

KJSq2 using

VDD rather than VDsql.

One can similarly equate the current through the (i - l ) t hand ith transistors, solving for VDs,, in terms of VDsq,-, . This results in equation 3. Equation 3 can be used iteratively to find VDs, for each transistor, starting with the third in the stack. Finally, VDsql can be determined by subtracting thse sum of VDsq, through VDsqN from VDD.

The voltage offset at the source of each transistor is given by V S =

x:z,+, VDsj. If we are only interested in the magnitude of the leakage current,
we can use VDsq, in equation 1 to compute the leakage through the bottom

transistor. To verify this computation, one could compute the leakage of other transistors in the stack. Once we have VDs, for each transistor, the voltage offset at the source of each transistor is given by Vs,
=

xr!i+l VDsq,.

VDsq, and Vsq, are now

known for each transistor, so we can compute the steady state leakage current using equation 1. Now let us determine the leakage savings obtained by tul-ning off multiple transistors in a stack rather than a single transistor turned off. Dividing the leakage of a single transistor by the leakage of a stack of transistors turned off, we find the savings ratio as a function of the number of transistors (N) t o be:

Take note that this analysis only considers transistors that are turned off. Transistors that turned on can be treated as if they were a short circuit.

Tl~anks to the very small currents involved (on the order of nL4or smaller), the voltage drop across transi~t~ors that are turned on will he orders of magnitude smaller than the voltage drop across transistors in the suhtlireshold

2.2 Sensitivity t o process and other variations

Tlle magnitude of subthreshold current is sensitive to many parameters. but threshold voltage and temperature variation are of particular interest because the dependence is exponential or greater. Inspection of the subthreshold current equation reveals that a small relative change in other piirameters (length, width,

Cox) will

cause an equal relative change in subthreshold

current. Device climensions variations can also indirectly affect leakage by influencing t hresholcl voltage. In the subthreshold current equation, one might not initially expect an exponential increase with respect to temperature since T appears as a

$ term

in the exponent. However, for typical operating temperatures (on the order of 300 or 4001<) the current approximately doubles for every 8 " h Fincrease in temperature. This is the same as the temperature sensitivity of silicon bipolar devices. Sensitivity with respect to threshold voltage variation (due t o variations in doping and channel length) is equal to the subthreshold slope, for which current increases by a factor of 10 given a change in threshold voltage on the order of 80 to 100mV. Supply xroltage only indirectly affects leakage slope d ~ ) can he obtained through the DIBL effect, for which the L ~ D / l ~ g ( I

v
a'S subthreshold

slope

[Vyclecade].

The leakage savings ra,tio, given in ecjuation 4, exhibits very litt'le sensitivit,y to varia.tions in threshold voltage or diniensions dimensions, provided t'hi1.t the variations are uniform for all transistors in a stack. In our model, the effect of a uniform shift in t'hreshold voltage or dimension disappears in the derivation of the predicted sa.vings ratio. For a stack of two 3u/O.5u transistors? HSPICE simulations showed only a 5% drop in savings ra.tio if threshold voltage was swept from approximately 0.6V down t,o 0.3.V. Temperature variation has a significant effect on the leakage sa,vingsratio, however substantial savings are still observed for a wide range of temperatures. For a stack of two :3u/0.5u transistors, equation 4 predicts that the 1eitka.gesavings ratio will drop from 14.8 t o 3.8 for a t e ~ n p e r a t u r e sweep from -.j0 to 1,50C. HSPICE simulation predicts a drop in savings ratio fro111 10.8 to 4.2, over the sanie temperature range.

2..3 Sirnulatioil and theoretical model results

In this section. ive will compare theoretical rnodel predictions to simulation results for steady state leakage conditions. The siniulation result:; were obtained using HSPICE with the BSIRl 1 model for a 0.511MOSIS process. The available hiZOSIS rnodels tlo not include measured subthreshold clmracteristics, so we have estimated the subthreshold swing and related parameters from threshold voltage parameters, using the technique derived by I k n g et. al. [4]. A subthreshold slope of approximately SOmV/clecade was estimated and incorporated into the 0 . 5 ~ BSIM model. In order to approxi~nitte the be-

hxcior of low threshold high leaka,gedevices, we modify t,he fla,t hand voltage parameter (VFBO). Each of the follo\ving figures compare model predictions to simulation re:ult's for 64 sets of randomly select,ed design pa,rameters that describe a tramistor stack. The parameters that were allowed t,o vary were t'ile following: temperature (--50 t o 1.50C),number of transist,ors in the stack turned off (2 to 4 t,ransistors), VTH,(from approximat'ely 0.26V t,o 0.56V)? supply voltage (from 1.217 t,o 1.8V), and transist,or width (from 3p to 10,u). Each transistor in the stack was t,reat,edas having identical charact,eristicsfor purposes of validating our simplified leakage model. The horizontal a.xis of each graph corresponds to a range of model predictions. The vertical axis corresponds to tile range of values extracted from simula.tion results. Ehch data point identifies a model prediction and the corresponding simulation result. leakage to s'imulation Figure 4 compares moclel predictions of steady st,at,e results. Figure 5 compares model predictions of lea,kage saving ratios to

sirnula.t'ion results. The savings ratio was obtained by dividing the leakage of a single transistor by the leaka,ge of t,he transistor stack. In both graphs, a very close correlat,ion is observed.

2.4

Sensitivity of model to transistor characterization

Subthreshold slope, the DIBI, coefficient ( r l ) , and the linearized body effect coefficient (7') are by far the most critical parameters to the estimation of leakage current and leakage savings. Zero bias threshold voltage is critical to leakage estimation, but has no effect on the savings ratio unless threshold

+
10-l4
1 0-l4
1
1

llll.ll

1 1 1 1 1 1 1

1 . 5 5 . m 1

l l i l l l l

i c G L 8

1 0-l3

1 0-l2

10-l1

1 0-lo
Model ldsq [A]

1o '

1o

-~

1 0-7

lo-=

Figure 4: Correlation of simulat,ed and estimated leakage variations from one t r a n ~ i s t ~ o to r the next are considered. These parameters all have an exponerltial influence on leakage and savings estimate:;. Other parameters (dimensions. Cox, and carrier mobilities) only have a proportiorla1 effect on leakage estimates. and no effect at all o11 savings estimates except for variations from one transistor to another.

Random design parameters

30

2!5-

++

g 20 C .>

+ +

+ +

+
-

cn

8
Y, 1 5 J w

+
++ +

4 + +++ ++

'k

+ +
-

0)

= ID+++
5+

++++

+%

+ i

k+

++

0 0

10

15
Model Leakage Savings

20

25

30

Figure 5: Correlation of simulated and e s t i ~ n a t e d leakage savings

Leakage transients

In previous sections. we have shown t h a t leakage can h e greatly reduced by

stacking transistors t o h e turned off when a circuit is idle. T h e time for
a circuit t o reach this quiescent low leakage s t a t e call be several orders of

magnitude greater t h a n the clock period or latency of most digital logic. This delay is a result of cha,rges trapped on internal nodes which can only cha,rge or discharge t o cluiescent levels by means of leakage currents that are very

srnall in comparison t o normal switching currents. A long settling time is not necessarily a disadvantage to the use of transistor stacking. However, let
us first examine the behavior of a transistor st,ack for best and worst case

settling time and the11 consider implications of the long settling time.

3 .1

Theoretical model

Consider again the transistor stack illustrated in figure 3. A rea1i:;tic worst case settling time corresponds t o the case where all internal nodes are initially cl~argedto the maximum possible voltage ( l a D - V T H just ) before tlie node is completely isolated by transistors that are turned off. This n~axiniizes the a ~ n o u ~ of l t charge that rriust be dissipated by means of leakage hefore the can he achieved by circuit settles t o quicsccnt levels. The worst case co~ldition the following sequence of events. ,411 but thc bottom transistor are initially on so that all internal nodes can charge t o LbD-VTII. Now turn off the transistor ne:it to the bottom. Because the gate of this transistor is capaciti\el;; couplcd to nodes above and below (due to gate overlap capacitance), the Loltage of bo1,h nodes are pulled down somewhat (referred t o as "bootstrapping"). .Just after bootstrapping, the voltage at the i t h internal node can be estimated as

where C,, is the gate-source overlap capacitance of transistor i. Internal node i corresponds to the source of transistor i and the drain of transit;tor i + l .

C: is the value of the internal node capacitance just before bootstrapping,

including the gate-drain overlap capacitance of transistor i

+ 1.

C'y is the

vitlue of the internal node capacit'ance just aft,er bootstrapping, including the ga'te-source overlap capacitance of transistor 2 and the gabe-drain overlap cz~pacit~ance of transistor i $ I . Figure 6 identifies the capacitimces and

transistors directly affecting internal node i. Typica.11~ each irlternal node cclnsists entirely of the diffusion that is shared by the source a,ntl drain of acljacent transistors. Kotice that only overlap capacitance is inclutled in the ga.te t o diffusion coupling. One might expect that gate to channel capacitance

(Cr,

1j1)' L) would produce additional coupling. However, the t,ransi:;tor being

s\vit,checl is already on the edge of cut.off (VLs = l.'TH). Sinlulation results incrlicate that the degree of bootstrapping is close t o that indicated by overlap ca,pacitance alone. This ana,lysis assunles that all tran~ist~ors in the sta'ck are being t,ur~led off.

If we wished t o consider a ca,se where an internal transistor is not switched off,

we must consider that transislor in determining t h e total node ca,pacitances for boot,strapping and set.tling time calcula.tions. Unlike the quiescer~t current an;zlysis, transistors that remain on can not be ignored. When deterrniiling node capacitances, a t,ra.nsistor t,ha.t remains t'urned on can he viewed as a piece of interconnect. Gat,e and diffusion capacihnces must then be included as a part, of the internal node capacitance. Within rlanoseconds after bootstra,pping, the node above the transist'or being switched will charge hack up to

I,,bD-

If the next t ra,nsistor

up is then turned off, the bootst'rapping process will repea,t itself. Once all t,rainsistors in the stack are off, we find a,ll the internal nodes charged up t o a,pproximately as given in equation 5.

Now if the circuit is idle for a sufficiently long time, the internal nodes will

-r
"above node i"
'

VDD

Gate

,__---\

/ \ \ \ \ / /

Gate i+

i+l

"below node i"

Node # i

Figure 6: Transistors and capacitances affecting internal node i begin t o discharge and eventually reach quiescent levels as illustrated for a stack of four transistors in figure 7. Initially only the node closest t o ground will discharge through the bottom transistor. All of the other tran4stors in the stack are strongly reverse biased (VGS < 0) and will have leakage currents that are orders of magnitude smaller than the bottom transistor. T h e next notle in the stack will not start to discharge significantly until tht> bottom notie has nearly reached the quiescent level given in section 2.1. 1 he third notle from ground will not discharge until the second node has near1~reached its quiescent level. This process is repeated until all nodes in the stack reach quiescent levels. This is ill~istratecl in figure 7 where the current discharge is displayed for each internal node in a stack of four transistors. Each current wal-eform was obtained as the difference between the channel curreiits of the

transistors a,bove and below t,he node being discha.rged.

I\

Bottom Node Middle Node

2u

4u

6u

Settling time [sec]

Figure 7: Discha,rge of internal node ca,pa,cita.nces We estimate the time for each node to discharge as follows. During discharge, the rate by which node voltage (T;;) drops can be determined as a function of the node voltage.

Id,,(Vl/;)is the magnitude of the discharge current as a functioil of node

volt,age. C,(I/,) represents the node capacitance formed by the shijred cliffusion of the transistors above and below.

C', could include interconnect

stack is not implemented in a single coiitiguous capacitance if the tra~lsistor strip of diffusion. C, may also include gate and diffusion capacitances of transistors which are not switched off. The inverse of equation 6,
dt z, enables us

t o est'irnate the ela,psecl time corresporlding to an incremental decrea,se of I.,':. 1ni;egra.ting over the range by which the volt,age drops, we find t,he time taken for the node ~ o l t ~ a g t,o e discharge from

I'ioot, clown

to t'he quiescent volta,ge

level, V,,. To make the integral tracta.ble, it was necessary t o assume tha,t ca,pacitance remains const,ant. Details of the derivation are deferred t o the appendix. Equation 7 gives the resulting expression for the discharge time of internal node

i.

v 7 is the thermal voltage

y. \Lot,is the voltage at the internal node just

after switching of t h e transistor above. taking into account boota;trapping.

l'iz is the quiescent level for the internal node voltage, as determii~ecl by the
leakage model in section 2.1. C, is the total capacitance of the internal node. Since C, decreases with voltage. ive conservatively choose

C,= C',(T/j,).

All

other terms have the same definition as given in section 2.1.

3.2

Sinlulation and theoretical model results

In this section, bye will compare theoretical model predictions to t.;imulation

results for the settling time of leakage transients once t,wo or more t,ransistors in a stack have been turned off. The simulation results were obt,ained in t,he same manner as described in sectiori 2.3.

Figure 8 uses a scatter diagram to compare settling time estimates for random selections of transistor parameters and transistor stacks of various heights. The vertical axis indicates simulation measurements of the time required for supply voltage current to settle to within 10% of its quiescent level. The horizontal axis indicates settling time derived from the theoretical model. Correlation between the simulated and estimated leakage can be o1)served by the clustering of points along the diagonal.

1 0-6 1 o4

-1

. . .A
-~
10-1

1o

-~

1o - ~ 1o - ~ Model Settling Time [sec]

1o

Figure 8: Correlation of simulated and estimated settling time

3.3

Sensitivity to process and other parameters

Settling time va.ries by orders of magnitude in inverse proportion tc, the ma.gnitude of the 1eaka.ge current which is a.lso subject t o wide variation. Consequently, it is strongly dependent on the same parameters as di:icussed in section 2.2 for leakage current. Settling time is proportiona.1 t o t h e size of the internal node ca,pacita.nce since node ca,pa.cit.ancemultiplied by voltage is wha,t det'ermines how much ck.arge needs to be discharged. Consecluently, it is essentia.1 t o have a.n accurate measure of nocle capacitance t'hat includes t h e volta.ge dependence of diffusion junction ca.pa.cit,ance.

3.,4 Energy cost associated with leakage transients

Circuit, level estimation of tra,nsient leakage current costs is a. complex task. However, our preceding analysis offers some insight into the problem. In the worst case settling time analysis we see that very little 1ea.ka.gecurrent is clsa.wn from t h e supply unt,il t h e node furthest from ground (in a.n NMOS stack) has almost completely clischa,rgetl. If the next set of inputs t o the circuit were t'o discharge t h e pull down network, then 1ea.kage t o ground did nclt cost us anything. Charges on t h e interna.1 nodes woulcl b e djscha.rged t o ground regardless of whether or not leaka,ge occurred. O n t h e other hand,

if t h e next set of circuit inputs ca.use the int'erna.1 nodes t o be charged up

aga.in, then t.he energy dissipated clue t o leaka,ge is a complete 10s:;. In general, 1ea.kage does not cost us anything if cha,rge is being moved in t h e sa.me direction as it woulcl during t h e next switching event. Conversel.~, 1ea.kage

energy is completely lost if it flows opposite the direction of current in the next swit,ching event.

3.5

Exploiting the stacking effect

Several options are ava.ilable t o exploit the st.acking effect for purposes of leakage control. One obvious approach is to use a similar circuit topology to that of MTCMOS [l, 71. Insert leakage cont,rol transistors bet,ween the pa'wer supply rails and the rest of the circuitry, but rely on the stacking effect, rather than an elevated threshold voltage to limit leakage current. Another opt'ion is t o select. some individual t,ransist,ors a,nd replace them by a pair of transistors with the gates tied toget,her. Whenever such a t,ra.nsistor is t,urned off for a sufficiently long time, we will obtain a leakage reduction due t o stacking effect. A t,hird and perhaps the most attractive option is to rnake use of existing transistor stacks. Area penalties, performance loss, and increased switching capacita,nceare a,voided since this does not involve adding transistors or increasing the size of pull up or pull down network;;. Except for inverters and pass gates, primitive CMOS logic gates already possess a transistor stack in either t h e pull down net,work, the pull up network, or both. R'henever a circuit is going t o be idle for some length of time. it should be possible t o select an input vector tha,t maximizes the number of t'ransistors which are turned off in each a,vailable transistor stack. If a suititble "lo~vleakage" input vector is not available, it may be worthwhile t o alter t,he circuit design slightly t o fa,cilit,ateselect,ion of an input vector. Recently, I-Ialter and Najm

I'[

proposed the use of standby mode input vectors t o control leakage,

but they did not identify t h e stacking effect as the mechanism making the leakage savings possible.

Conclusions

M1e have present,ed a theoretical model that predicts the quiescent leakage current and the settling time required t o reach quiescent levels in transistor stack. T h e model is shown to correlate well with more detailed :,imulation results for a wide range of randomly selected design parameters. 'We anticipitte that the model will b e useful in leakage power estimation as well as for optimizing the design of low leakage circuits.

dicknowledgements
Thanks go t o R,lamoon Hamid who performed countless simulations which were very useful in coming t o an understanding of leakage behavior in ChIOS circuits.

Appendix: derivations
Leakage of a stack of N transistors
In the steady state, the current is t h e same through each transistor of a stack.
This assumes that other leakage currents (excluding subthreshold current) are negligible in comparison to subthreshold current. The subthreshold cur-

rent through the top transistor (furthest from ground, denoted wit11 t,he subscript 1) can be expressed by equation 8.

A; represents the following expression.

\THO

is t h e zero bias threshold voltage. vy is the thermal voltage

y.

Tlie body effect for small values of

I.2 is very nearly linear. It is represented

bl- the term 7'Tfl>, where y' is the linearized body effect coefficient. 7 is the

D [BL coefficient, representing the effect of I/os (VDs = 1 b - 1 >) on threshold

voltage. C,, is the gate oxide capacitance. po is the zero bias mobility.
71

is the subthreshold swing coefficient of the transistor. A I T H accounts for variations in thresholcl voltage from one transistor to another. T h e subthresholcl current through t h e ith transistor in the stalzk (where

:> 1) is expressed by ecluation 10. T h e only difference between ecluations

and 10 is in the expression for 1bsq,. For the top transistor, l/DC..yl can b e expressed as t h e difference between the supply voltage and the total voltage drop across transistors lower in the stack.

We can det,ernline the voltage across the second t'ra.nsist'or bj- equaking t,he expressions for IDS,, ant1 IDS,,. I..'+Ho and all bbs,, terms for ollt,. We are left with the following expression for I,bs,,.
I

> 2 drop

This derivation

assumes that VDD >> I;,, which proved t'o he true for the va.riety of t,est, cases studied in t'his report. The derivation also takes advantage of the fact that

l!bSql >>

VT S O

that the (1 -

euT

~ ~ ) ' term can he ignored.

The steady statme voltage drop (Vbs) across the i t" transistor can be expi-essed in terms of the ( i -

lit" voltage drop.

Equate Ins,, to

and

solve for VDsql. In so doing, we obtain equation 12.

Equat,ion 12 can he used iteratively t o find the voltage drop a,cross each t~ansistorin the stack. l,'osqlcan then be obtained as kbD -N t,j=2 V's,,.

Each internal node voltage ca.n be found as the sum of voltage drops across tr.a.nsistors lo~ver in the stack. If Vsq, were to become large enough to invalidate the assurnpticln in equation 11, then the VDD term in equation 11 must be replaced by I/bsql. In this case, an iterative successive approximation approach would he required to obtain a consist,ent solution for I/osq, through V D ~ , , ~ . The magnitude of the steady stat,e current can be det'ermined using the quiescent voltage levels and the subthreshold current equation for any tra'nsistor in the stack. 13Je choose t,he Wt" transistor (bottom) for this calculation.

For the bottom transistor, I > is equal to 0, so the current depends only upon VDSq,v.This makes the calculation simpler. Furthermore, the suht hresholcl current is relatively insensitive to l/os (in cornparis011 t,o I:;,).

Leakage savings ratio

If one is considering the use of a transistor stack, it may be interesting to
coinpare the leakage current of a single transistor to the leakage c u i ~ e n of t a stack of transistors turned off. It is convenient to express this as a ratio:

IDs,,(l) represents the quiescent leakage current of the transi~torstack

if only the top most transistor is turned off.
I11

this ca,se I.,'&s, = 0. IDs,,(iV)

represents t'he quiescent. leakage through the top transistor if all

N t~ransistors

in the stack are turned off. I/G = 0 for each transistor, but 6% may 1)e greater than zero due to the stacking effect. Mire use equation 8 t,o express and IDS,, (121') and then plug the expressions into equation 113 t'o give us the savings ratio equation 14. For the transistor stJack as well a:< a. single transistor, VUSql >>
VT.
1

Clonseq~ent~ly: the (1 - e F

I . '
DS1)

is very nearly

equal to one and can be dropped from the expressions for IDS,. Also: since 110th current expressio~ls refer to the same transistor, the

Ai t'erm:; drop out

(assuming that the temperature is t'he same in both cases).

Settling t inle of leakage transients

Section 3.1 describes the conditions for estimating the settling timeof leakage t r ~ ~ n s i e n t s111 . the current section, w e will clarify some of the details and assumptio~ls made in the derivation. bl'e estimate t h e time for each node to discharge as follows. During discharge, t h e rate by which node voltage (I/;) drops can be determined as a function of the node voltage.

Idis(l/::) is the magnitude of the discharge current a,s a filnctioin of node

voltage. Ci(K) represents the node capacitance formed by the shared diffu:;ion of the transistors a,bove and below.

C; could include interconnect

capacitance if the transistor st,ack is not implemented in a single c~o~itiguous strip of diffusion.

Cimay also include gate and cliffusion capacitances of tran-

sistors which are not switched off. The inverse of equation 15,

-&,enables us

to an i n ~ r e m e n t ~clecrease al of b : . to est'inlate the elapsed time correspo~~ding Integmting over t,he range by which the volta,ge drops, we find the time taken

I&,,fc down to the ql~iesceiltvolt,age for the node voltage t o discharge f r o ~ n

level, Vq,.

Inserting expressions for C,(I/;) and Id,,, (I/;), the last integral for t d z s , takes the form,

To make this integral tractable, some s i ~ l l ~ l i f y i n assumptions g are needed. M'e assume that the node capacitance is constant with respect to the node voltage 1.;. In reality, the node capacitance (made up of diffusion or diffusion capacitance) increases as the voltage on the node drops. To and i~it~erconnect be conservative in our settling time estimate, we compute the capacitance
-IV,-Lrq,',

cc-)rresponding to quiescent voltage levels. Lie ignore the (1 - e tel-111. The value of this term is almost exactly one until ( 1 . : v : ~T . h e integral for td;,, now simplifies t,o:

w~

C'i,+,) approaches

Evaluation of the integral in equation 18 leads to equation 19 for the time it takes to discharge node i.

I/T

is the thermal voltage

y.

is the voltage at internal r~ode i just

after switching of the transistor above, taking into account bootstrapping.

V,, is the ciuiescent level for the internal node voltage, as determined by the
leakage model in section 2.1. C, is the total capacitance of the internal nocle.

Since C, decreases with voltage, we conservatively choose C, = C,(Vqt). All oiher t,erms have the same definition as given in section 2.1. T h e total settling time is the sum of the discharge times for each of the internal nodes of the t,ransistor stack.

[:I] S. Shigernatsu et. al. A 1-V high-speed MTCMOS circuit scherlie for

power-down applications. In IEEE ,Symposiunz on VLSI Circuits Digest of Technical Papers, pages 125-126, 1995. ['I] J . P. Halter and F. Najm. A gate-level leakage power reduction g net hod for ultra-low-power CMOS circuits. In Proceedings, IEEE Cu.stom Integrated Circuits Conference, pages 475-478, 1997.

[3;] M.C. Jeng. Design ancl modeling of deep-sub-micro~neterbIIOSFETS.

Technical Report ERL-M90/90, University of California, Berkeley, Electronics Research Laboratory, 1990.

[4] S.-LV. I<ang, I<.-S. Min, and I<. Lee.

Parametric expression of sub-

threshold slope using threshold voltage parameters for hlOSFET statistical modeling. IEEE Trcln.sactiorzs on Electron Dtvicts, 43(9):1:382-1386, 1996.

[5: Takayuki Kaivahara et al. Subthreshold current reduction for decodeddriver by self-reverse biasing.

I E E E Journal of Solid-State Circuits,

28(11):1136-1143, Kov. 1993. [ 6 .A. I<esha\.arzi, I<. Roy, and C. Hawkins. Intrinsic IDDQ: Origins, reduct,ion, and applications in deep sub-p low-power ChIOS IC's. 111 Proceedzngs I E E E International Test Conference, 1997.

[71 S. hlutoh et al. 1-V power supply high-speed digital circuit tc-ch~lology
with multithreshold-voltage CILZOS. IEEE Journal of Solid-State Cir-

cuits, 30(8):547-853, Aug. 1995.

[ S ] B.J. Sheu, D.L. S ~ h a r f e t ~ t eP.I<. r, I<o, and M.C. Jeng. BSIM: Berkeley
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State Circuits. SC-22. 1987.