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IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 5, MAY 2007

Detection of Border Trap Density and Energy Distribution Along the Gate Dielectric Bulk of High- Gated MOS Devices
Chun-Yuan Lu, Kuei-Shu Chang-Liao, Senior Member, IEEE, Chun-Chang Lu, Ping-Hung Tsai, and Tien-Ko Wang

AbstractA novel charge-pumping (CP) technique is demonstrated to extract border-trap distribution for high- gated MOSFETs. The varying-frequency CP method is shown to be more effective than the varying-amplitude one for probing border traps and extending the tunneling depth. A linear relationship of the Qcp versus ln(Tr Tf )1/ 2 plot can only be maintained at the CP frequency of 1 MHz, while not below 1 MHz, due to the inuence of border traps near HfOx Ny /Si interface. The proposed technique, which takes into consideration the effect of carrier tunneling in slow oxide traps, is used successfully to obtain the spatial and energy dependence of bulk trap density in high- bulk. Index TermsBorder traps, charge pumped per cycle (Qcp ), charge pumping (CP), depth prole, HfOx Ny dielectric, nearinterface traps.

of MOS devices [6], [8], [10]. In this letter, the comparison of varying frequency and varying amplitude in CP methods was carried out to assess the ways of probing the border traps and the maximum tunneling depth. Furthermore, a novel CP technique, including the effect of carrier tunneling in slow oxide traps (border traps) was proposed to obtain the bulk trap prole with both energy and tunneling depth in the gate dielectric of high- gated MOSFETs. II. D EVICE F ABRICATION AND M EASUREMENT T ECHNIQUES Poly-Si/HfOx Ny gate stack was deposited on (100) oriented p-type silicon wafers for fabricating MOSFET. After the Radio Corporation of America (RCA) cleaning, HF dips for all samples were performed within approximately 15 min prior to HfN deposition. A Hfx Ny lm of approximately 3 nm was rst deposited onto the Si wafer by a reactive dc magnetron cosputtering, and a postdeposition anneal using rapid thermal annealing was then carried out at 850 C in N2 for 60 s to form a HfOx Ny lm of approximately 6 nm. The thickness of the interfacial layer of the nal high- gate dielectric is about 78 . The channel length (L) and width (W ) of the high- gated MOSFETs are 1.0 and 20 m, respectively. For MOSFETs with SiO2 gate, the gate oxide thickness is 100 and L/W is 5.0/5.0 m. The CP measurement was performed with both source/drain regions grounded while sweeping the base (Vb ) level of a constant voltage-swing (Vsw ) (i.e., amplitude) gate pulse from inversion to accumulation. By measuring the conventional CP current (Icp ) versus Vb curve, the average interface trap density (Nit ) can be obtained. A CP technique based on the variation of the charge recombined per cycle (Qcp ) with frequency was applied to extract the depth prole of border trap density (Nbt ) [6], [10]. Meanwhile, a CP theory used to extract the energy distribution of interface trap density Dit (E ) [11] was also modied, by introducing the effect of carrier tunneling in border traps, to obtain the near-interface trap (NIT ) distribution with the energy and spatial dependence. Details are described in the succeeding text. Fig. 1 illustrates the energy band diagrams of the border traps and the interface traps responding to CP signals in a SiO2 /HfOx Ny gate stack during the [Fig. 1(a)] inversion status (or charging status) and [Fig. 1(b)] accumulation status (or

I. I NTRODUCTION IGH- material has been proposed to replace the conventional silicon dioxide (SiO2 ) as gate dielectrics of MOS devices in the near future. However, the characteristic and extent of charge trapping in the interfacial layer between high- dielectric and silicon have been reported to affect strongly on the electrical characteristics of high- MOS devices, such as gate leakage, degraded channel mobility, as well as Vth instability [1], [2]. Charge-pumping (CP) technique is known to be a very efcient tool for studying the interface traps in high- gated MOSFETs. Recently, the CP technique has been used to determine the mean capture cross section and the energy distribution of the interface trap density in high- gated MOS devices [3][5]. It has also been reported that when border traps exist within tunneling distance of the high-/Si interface, the reduction of frequency results in the increase of charges recombined per cycle (Qcp ) [6]. The increase of Qcp is resulted from electrical communication via an interface trap to border-trap tunneling mechanism [7][9]. Some reports have proposed an effective CP extraction method to detect the depth prole of border traps situated in the conventional gate oxide

Manuscript received January 8, 2007; revised February 20, 2007. This work was supported by the National Science Council of China under Contract NSC 95-2221-E-007-225. The review of this letter was arranged by Editor M. Ostling. The authors are with the Department of Engineering and System Science, National Tsing Hua University, Hsinchu 30013, Taiwan, R.O.C. (e-mail: lkschang@ess.nthu.edu.tw). Digital Object Identier 10.1109/LED.2007.895379

0741-3106/$25.00 2007 IEEE

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Fig. 1. Energy band diagrams of the border and the interface traps responding to CP signals in a SiO2 /HfOx Ny gate stack during the (a) inversion status (or charging status) and (b) accumulation status (or discharging status) [18].

discharging status). In Fig. 1, the border traps lie within the HfOx Ny stack and are considered to have similar energy dependence to the interface traps [12], [13]. In general, these border traps lie below the conduction band of Si (Ec ) and within the range of Si bandgap [14][16]. The maximum tunneling depth (xcp n ) reached by the inversion charges, as shown in Fig. 1, can be estimated as [17] xcp n = n ln (n (0)th ninv tinv ) (1)

where th is the thermal velocity, ninv is the electron concentration in inversion, and tinv is the hold time of a trapezoidal pulse in inversion. The value of xcp n increases with decreasing CP frequency. For different barrier heights between 1 to 3 eV, the attenuation coefcient n remains at around 0.1 nm [6], [17]. The n (0) stands for the electron capture cross section at the Si/SiO2 interface. Since the carrier type sets a limit to the recombination, the distance of lled trap centers from the cp cp interface can be dened as xcp = min(xcp p , xn ) [10]. The xp is the maximum tunneling depth of holes. According to [12], the space-dependent electron emission energy level Eem,e (x) can cp be replaced with the average value Eem ,e taken at x = x /2. Thus, one can write 1 Eem ,e = Ei kB T ln(n (0)th ni tf ) ln(n (0)th ninv tinv ) 2 (2) with tinv = tf + ( 1)tr + W, = |Vh Vth | Vsw

where NIT (E ) is the energy distribution of near-interface trap density in the region from the interface to the maximum tunneling depth (xcp ), q is the elementary charge, and A is the gate area. Similar derivation can also be applied to describe the near interface trap density NIT (Eem ,h ) and the hole emission energy level Eem below midgap [12]. Furthermore, it is not necessary ,h to divide clearly the near-interface trap density into border traps and interface traps because the near-interface density is an average value for a particular distance from the Si/SiO2 interface to xcp . III. R ESULTS AND D ISCUSSION Fig. 2(a) shows the interface trap densities as a function of the voltage swing (Vsw ) for HfOx Ny and SiO2 -gated MOSFETs. It is clear that interface trap densities increase signicantly with increasing Vsw in high- devices, while the increase is less signicant in SiO2 devices. In general, the increase shown in a high- device can be attributed to the inuence of border traps near HfOx Ny /Si interface [1]. A similar behavior can also be observed by decreasing CP frequency, as shown in Fig. 2(b). Thus, either the varying-Vsw or varying-frequency method can be applied to probe border traps in high- dielectric. However, the former has the shortcoming of causing stressing effects, which would result in Icp curve shift for high- gated MOS devices. The varying-frequency way is more appropriate for probing border traps because it adopts a large range of frequencies from 10 Hz to 1 MHz and a constant Vsw . In this letter, the varying-frequency method is applied to detect the spatial and energy distribution of bulk trap density in high- bulk. Fig. 3(a) shows Qcp as a function of CP frequency ranging from 10 Hz to 1 MHz. In order to suppress the effect of the rise/fall time (tr /tf ) of the gate pulse, the frequency was limited to below 1 MHz. The rise/fall time (tr /tf ) was held at a constant value of 100 ns. The results exhibit that the Qcp is strongly inuenced by border traps at high frequency, and this effect increases with decreasing CP frequency. An approximate depth prole of border traps Nbt (x) can be obtained by adopting the derivative dQcp /d log(f ) and the related physical parameter; results are shown in the insert of Fig. 3(a). Fig. 3(b) shows the plot of Qcp versus ln(tr tf )1/2 with

where Ei is the midgap energy, kB is the Boltzmann constant, ni is the intrinsic carrier concentration, tr/f is the rise/fall time, W is the gate pulse width, Vh is the high voltage level, Vth is the threshold voltage, and Vsw is the voltage swing of gate pulse. In order to estimate the energy and spatial distributions of near-interface traps (NIT ), the NIT (E, x) NIT (E ) should be assumed [12]. Hence, the near-interface trap density is derived to be
NIT (Eem ,e ) =

1 xcp qAkB T

dQcp /dtf [1/tf (/2tinv )]

(3)

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IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 5, MAY 2007

Fig. 2.

(a) Interface trap density as a function of gate voltage swing. (b) Interface trap density as a function of 1/f for HfOx Ny -gated and SiO2 -gated MOSFETs.

Fig. 3. (a) Qcp as a function of CP frequency ranging from 10 Hz to 1 MHz. The inset shows the depth prole of border traps (Nbt ) in gate dielectric, which is extracted by adopting the derivative dQcp /d log(f ) and the related physical parameter. (b) Plot of Qcp versus ln(tr tf )1/2 with various CP frequencies.

various CP frequencies. It can be found that only the Qcp at the CP frequency of 1 MHz maintains a linear relationship with ln(tr tf )1/2 , and thus, it is used to estimate the mean capture cross sections of electrons n (0) and holes p (0). The CP frequencies below 1 MHz cannot be applied to calculate the mean capture cross sections due to the nonlinearity [3], [4]. Fig. 4 shows the prole of near-interface traps (NIT ) with both energy and tunneling depth in the [Fig. 4(a)] lower half and [Fig. 4(b)] upper half of the Si bandgap of high- gated MOSFETs. It can be found that the distribution prole of NIT at 1 MHz (from 0 to 7.16 ) is similar to that of the conventional Dit (E ) [11]. This may suggest that the Dit (E ) in high- gated MOSFET calculated by the conventional CP technique [4] is not only the interface trap density but also the average value of all traps from Si/SiO2 interface to a particular tunneling depth (i.e., interface traps plus border traps). On the other hand, from Fig. 4(a), the depth prole of near-interface traps in the lower

half of the bandgap is similar to the distribution of border trap density shown in the insert of Fig. 3(a). In general, the bonding formed in HfSiON layer (i.e., at the HfOx Ny /SiO2 interface) is more complete which results in the decrease of the volume trap density in the high- bulk. Besides, the results in Fig. 4(b) exhibit that the NIT distributions of 100 and 10 KHz differ slightly from those of 1 MHz and 500 Hz in the upper half of the Si bandgap, which may suggest that the material bonding located at the depth from 9 to 11 is probably distinct from that in the interfacial layer and high- bulk. Also, the total amount of near-interface traps in the upper half is higher than that in the lower half of the bandgap. This situation illustrates that HfOx Ny -gated n-MOSFETs has severer mobility degradation than p-MOSFETs [5]. The degradation is due to the Coulomb scattering resulted from the high density of interface-trapped charges and the xed oxide charges near the high- dielectric/Si interface [2].

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Fig. 4.

Prole of near-interface traps (NIT ) with energy and tunneling depth in the (a) lower half and (b) upper half of the Si bandgap of high- gated MOSFETs.

IV. C ONCLUSION A novel CP technique was proposed to obtain a clear observation on the spatial and energy distribution of the nearinterface traps in the gate dielectric of high- gated MOSFETs. The CP method with varying frequency has been shown to be more effective for probing border traps than that with varying amplitude. Relatively lower border trap density is found in the HfSiON layer due to its better bonding. ACKNOWLEDGMENT The authors would like to thank National Nano Device Laboratories of China for the technical support. R EFERENCES
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