Solid-State Electronics 49 (2005) 545553 www.elsevier.

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Interface trap properties of thermally oxidized n-type 4HSiC and 6HSiC

T.E. Rudenko
a b

a,*

lafsson b, E.O . O . Sveinbjo , I.N. Osiyuk a, I.P. Tyagulski a, H.O rnsson

Institute of Semiconductor Physics, National Academy of Sciences of Ukraine, 03 028 Prospect Nauki 45, Kyiv, Ukraine Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, Chalmers University of Technology, SE-412 96 Go teborg, Sweden Received 1 March 2004; received in revised form 10 December 2004; accepted 10 December 2004 Available online 2 February 2005

The review of this paper was arranged by Prof. S. Cristoloveanu

Abstract This work presents detailed investigations of interface traps at the Si-face 4H and 6HSiC/SiO2 interfaces using thermally stimulated current (TSC) and capacitancevoltage (CV) techniques. Using n-type material we focus on the interface traps near the SiC conduction band edge which, in the case of 4HSiC, severely suppress the eective mobility in n-channel metal-oxide-silicon carbide transistors. Our TSC measurements demonstrate that electron traps at the 4HSiC/SiO2 interface consist of two groups of trap levels displayed as two distinguishable TSC signatures and diering by their trapping/detrapping behavior. One of them, chargeable at low temperatures, is displayed as a well-dened TSC peak assigned to a trapping level with an activation energy of 0.11 eV. Another is displayed as a wide TSC hump, and its charging mechanism strongly depends on temperature, indicating that these traps are not conventional fast interface states but border traps. A near-continuous distribution of activation energies ranging from 0.1 to 0.7 eV is obtained for these traps. The above two groups are observed in dierently prepared thermal oxides on Si-face 4HSiC. We hypothesize that both groups are due to the same interfacial defects but diering by their spatial closeness to the interface: the rst is located in immediate proximity to the interface, while the second is composed of defects distributed within the oxycarbide transition layer, which explains their range of ionization energies and the thermally activated capture mechanism. No distinct interface traps are observed on 6HSiC samples. In general, the electrical characteristics of the 6HSiC/SiO2 interface can be satisfactorily explained in terms of conventional fast interface states. 2005 Elsevier Ltd. All rights reserved.
Keywords: SiC/SiO2-interface; MOS-structure; Interface states; Thermally stimulated current

1. Introduction The excellent electrical and physical properties of silicon carbide (SiC) and its ability to form insulating silicon dioxide (SiO2) layers by thermal oxidation make it a very attractive material for high temperature, high power and high frequency metal-oxide-semiconductor
Corresponding author. Tel.: +380 44 265 70 22; fax: +380 44 265 61 77. E-mail address: tamara@lab15.kiev.ua (T.E. Rudenko). 0038-1101/$ - see front matter 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.12.006
*

(MOS) devices. However, it turns out that both 6Hand 4HSiC MOS eld-eect transistors (MOSFETs) suer from low electron mobility in n-channel inversion layers [13]. The problem is especially evident in 4HSiC MOSFETs where the eective channel mobility is of the order of one percent of the bulk mobility when using a gate oxide made in either pure oxygen or pyrogenic steam. In the past few years, many studies have been made to clear up the nature of the defects responsible for the low electron mobility and nd technological methods to eliminate and/or passivate these defects

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[410]. Several research groups pointed out that severe degradation of the surface electron mobility in 6HSiC and 4HSiC MOS devices is due to the high density of interface electron traps close to the conduction band edge [1,38]. The highest density of such traps is found at the 4HSiC/SiO2 interface [1,49]. These electron traps are believed to be near-interface traps and are ascribed to distinct intrinsic defects in the interfacial region of the thermally grown SiO2 [4,7,9]. However, the exact nature of these defects remains unclear and so far not much is known about their electrical properties. To a large extent this is related to the fact that it is difcult to use and interpret the conventional small-signal steady-state MOS characterization methods, such as conductance or highlow frequency capacitancevoltage (CV) techniques, in the region near the majority carrier band edge [11]. In this paper, we present detailed investigations on the interfacial electron traps near the conduction band edge on Si-face 4HSiC/SiO2 and 6HSiC/SiO2 interfaces using a combination of CV and the thermally stimulated current (TSC) techniques. The TSC technique diers from small-signal steady-state techniques in several respects. Firstly, being a non-equilibrium method based on measuring the emission current from lled traps, the TSC technique allows extraction of the trap parameters without knowledge of the band bending at the interface. Secondly, TSC is less sensitive to lateral surface potential non-uniformities. Thus the TSC technique should have better accuracy and better resolution than small-signal steady-state techniques in the region close to the band edge. The third dierence is that the TSC method is sensitive to traps distributed into the oxide. This can provide additional information, not available by conventional interface trap characterization techniques. Here, we demonstrate how the TSC technique in conjunction with CV measurements provides information about the electronic properties of interface traps, in particular, at the 4HSiC/SiO2 interface.

Ar/H2 ambient. Circular aluminum gate pads with radius of 100 or 150 lm were prepared by thermal evaporation, photolithography and wet chemical etching of the metal. The backside contact was formed using an AlGa eutectic.

3. Measurement techniques The interface traps were studied using TSC measurements conducted in the low temperature range. Most of our TSC measurements were performed in the range from 28 to 250 K using a gaseous helium cooling system, but to study the very shallow traps some measurements were performed in the range from 7300 K using a liquid-helium cooling system. Additionally, the MOS structures were characterized using CV measurements at various temperatures and also by measuring room temperature high frequency (1 MHz) and low frequency (1 kHz) CV curves. The TSC technique is presently a well-established tool to study mobile ions and traps within silicon dioxide in MOS structures [12]. However, as has been shown in the past, in MOS systems the TSC technique is also applicable to study majority carrier interface traps [13 16]. The technique is particularly applicable when the interface state density is high. For this reason it has lost its actuality for the silicon MOS technology, when the density of interface states at the Si/SiO2 interface became extremely low. However, for the case of SiC/SiO2 interfaces, at which interface state density is typically essentially higher, the technique turns out to be very useful and informative. The TSC measurement procedure is as follows. A charging voltage Vch is applied to the gate at a charging temperature Tch to bring the interface into accumulation, thereby lling the traps with majority carriers (in our case, with electrons). Then the sample is cooled down to a temperature T0 with the charging voltage Vch kept constant, so that the trapped charge becomes frozen in. At a low temperature T0 the gate bias is then switched from Vch to the discharging voltage, Vd driving the MOS structure into deep depletion, in which traps remain lled because the temperature is too low to allow thermal emission of the electrons. After a short waiting period the temperature of the device is raised at a constant heating rate b: T = T0 + bt. During heating, the trapped electrons are gradually released by thermal emission, and the trap discharge displacement current is monitored as a TSC signal. The measured IT characteristic is shown to be the near-direct image of the trap energy distribution [1315]. Generally the measured TSC current may be due to both interface traps and bulk traps in the depletion region of the semiconductor. However, bulk and surface-related contributions are easily separated by varying the charging voltage, as we demonstrate below.

2. Samples MOS capacitors were fabricated on commercially available nitrogen doped 4HSiC and 6HSiC epitaxial layers grown on (0 0 0 1) Si face o axis SiC substrates. The doping concentration in the epitaxial layer was (13) 1016 cm3. A variety of dierently prepared thermal oxides have been studied. The results presented in this paper are for a 50-nm thick oxide grown at 1150 C in dry O2 for 4 h and 15 min. However, the general properties being discussed were also observed in samples with dry oxide grown at 1100 C, wet oxides, and oxides that received an additional re-oxidation anneal at a temperature of 950 C for 90 min in pyrogenic steam, or received a post-oxidation anneal in an N2 or

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Several methods are available for analyzing the TSC spectra to determine the trap parameters [17]. In this study, we employed three of them, namely, the heating rate variation method [18], fractional cleaning method [19], and the analysis of Simmons et al. [14,15].

4. Results 4.1. Eect of the charging voltage on TSC and highlow temperature CV measurements Fig. 1(a) shows typical TSC spectra of an n-type 4H SiC MOS capacitor measured for various charging voltages applied at Tch = 250 K. The discharging voltage for all the curves is 5 V. In Fig. 1(a) the TSC signal recorded below 50 K (not shown) is due to nitrogen donors in the SiC depletion layer, while the signal above 50 K is due to interface states. The assignment of the signal is veried by cooling the device to the low temperature under a depletion bias so that the interface states in the upper part of the bandgap are empty. In this case, no TSC signal is detected in the temperature range 50 250 K. On the contrary, when the sample is cooled under accumulation bias, the signal appears. This demonstrates that the TSC signal is due to interface traps and is not due to traps in the bulk of the SiC. This interfacerelated signal increases gradually with the accumulation charging voltage without any sign of saturation. Integrating the area under TSC curves yields the total density of the occupied traps released during TSC scan, NTSC [1315].

Typical TSC spectra of an n-type 6HSiC MOS capacitor measured for various charging voltages are shown in Fig. 1(b). The TSC signal, which increases sharply at temperatures below 55 K, is related to the nitrogen donor in the cubic lattice sites [20]. Above 60 K the TSC signal is due to interface states. This signal is featureless, signicantly lower than that in the 4HSiC sample, and grows only slightly with the charging voltage. The inset in Fig. 1(b) shows TSC spectra on a 6HSiC MOS capacitor at lower temperatures. The two peaks at about 29 K and 47 K are related to the nitrogen donor in the hexagonal site (h) and cubic sites (k1, k2) [20]. At temperatures below 25 K, we detect a TSC signal whose behavior as a function of the charging voltage is similar to the one seen for the interface state signal in Fig. 1(a) above 50 K. The signal below 25 K grows with the charging voltage, while no current is measured in this temperature range if the charging voltage is insucient for electrons to accumulate at the SiC/ SiO2 interface. Therefore, we conclude that the signal below 25 K in 6HSiC is due to interface states. It should be noted that no such interface-related signal is observed in 4HSiC in this temperature range (not shown). Below we will mainly consider interface states displayed in TSC measurements at temperatures higher than 50 K. The interface state related signal below 25 K in 6HSiC has been investigated in detail in our previous publication [21]. The interface traps revealed in the TSC spectra in Fig. 1 can also be seen as a shift in the at-band voltage in CV curves that are measured at high and low temperatures. At a temperature of 250 K the traps capable

Fig. 1. TSC spectra of a dry oxidized n-type: (a) 4HSiC and (b) 6HSiC sample for various charging voltages applied at Tch = 250 K. The discharging voltage is the same for all curves Vd = 5 V. Heating rate is 0.333 K/s. In the inset in gure (b) are shown the measurements of the 6H SiC sample made in the lower temperature range (the heating rate is 0.2 K/s).

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of emptying their charge by thermal emission in the temperature range 50250 K are fast enough to follow the gate voltage sweep. In contrast, at 50 K the same traps are unable to thermally emit their captured electrons within the time frame of the measurement, so that the trapped charge is frozen in. This is seen in CV measurements as an additional negative xed charge and the corresponding at-band voltage (VFB) shift of the CV curve, DVFB provides an estimate of the density of the eective trapped charge at the SiC/SiO2 interface. Such CV measurements for the 4HSiC sample are presented in Fig. 2(a). To avoid distortions due to series resistance eects at low temperatures, we used quasi-static CV measurements, i.e. measuring the gate current while sweeping the gate voltage at a constant rate. The measurements made at 250 K, are shown for both voltage sweep directions to illustrate the absence of signicant hysteresis. In the measurements made at 50 K the gate voltage is swept from depletion to accumulation but prior to measuring each curve, the interface traps were lled using the charging voltage Vch indicated in the gure, which was applied at the temperature Tch = 250 K and kept constant while the sample was cooled, similar to trap lling in TSC measurements. It can be seen that in the 4HSiC sample the at-band voltage shift increases linearly with charging voltage, being in agreement with the rise of the TSC signal in Fig. 1(a). Similar CV measurements for the n-type 6HSiC sample are shown in Fig. 2(b). The 6HSiC sample displays a considerably smaller shift of the CV curves than the 4HSiC sample. Also, the shift depends only slightly on the applied voltage during cooling. This agrees with the TSC measurements in Fig. 1(b). In Fig. 3 we compare the density of the charge trapped in interface states extracted from TSC and CV

Fig. 3. The trapped charge density evaluated from TSC measurements NTSC (triangular symbols) and CV measurements NCV (square symbols) of 4HSiC and 6HSiC MOS capacitors plotted as a function of the charging voltage. The solid line shows the accumulation charge density at the charging temperature (T = 250 K).

analysis as a function of the charging voltage applied at Tch = 250 K. NTSC (triangular symbols) denotes the number density of trapped charge derived from TSC and NCV (square symbols) is the number density derived from the CV analysis. The solid line shows the number density of the accumulation charge given by Nacc = Cox(Vch VFB(Tch))/q, where Cox is the gate oxide capacitance, q is the electron charge, and VFB(Tch) is the at-band voltage at the charging temperature. The number density of trapped charge increases linearly with charging voltage up to 1013 cm2 and corresponds to about 90% of the total available accumulation charge in the capacitor. This means that most of the accumulation charge in the 4HSiC sample is captured by the traps displayed in the TSC spectrum in the temperature range 50250 K. It should be noted that TSC measurements give the total trapped charge, while CV measurements give

Fig. 2. CV curves for (a) 4HSiC and (b) 6HSiC MOS capacitors at temperatures of 250 K and 50 K measured after cooling with various charging voltages Vch in 2 V steps. The measurements at temperature of 50 K are recorded when the voltage is swept from depletion to accumulation.

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the eective trapped charge at the SiC/SiO2 interface. Since there is very good agreement between the two techniques it is clear that the trapped charge centroid lies very close to the interface. It should be mentioned that the TSC measurements give the density of occupied traps, thus the absence of saturation in Figs. 1(a), 2(a) and 3 shows that the true total density of interfacial traps in the 4HSiC sample must be signicantly higher than 1013 cm2. The density of the trapped charge extracted from the measurements in the same temperature range (50250 K) for 6HSiC sample is considerably lower (about 6 1011 cm2) and saturates with increasing charging voltage. 4.2. Eect of the charging temperature on the TSC spectra If the interface traps are located exactly at the SiO2/ SiC interface they communicate directly with the underlying semiconductor and the trap lling is expected to be essentially unaected by temperature. The TSC spectrum should then be independent of the charging temperature. However, for the case of the traps distributed into oxide, which can capture electrons from the semiconductor by both tunneling and by a thermally activated process, one might expect a TSC spectrum to be dependent on the charging temperature. Fig. 4(a) shows TSC spectra of the 4HSiC sample when the charging voltage is applied at dierent temperatures keeping all other measurement conditions identical. When the charging temperature is lowered, the hump in the range 100250 K decreases while a wellpronounced peak appears at around 70 K. This peak is even observed when the charging temperature is lowered to 7 K. This result suggests the presence of two groups of traps diering by their lling mechanisms. One group is chargeable at low temperatures giving rise to a well-dened TSC peak at 70 K, indicating that its lling mechanism depends only slightly on temperature. For the second group the TSC spectrum depends strongly upon the charging temperature, and these traps are not able to capture electrons at low temperatures (below 50 K). This observation shows that the electron capture mechanism of these traps is thermally activated. For comparison Fig. 4(b) shows the TSC spectra for various charging temperatures on 6HSiC samples. As can be seen, the spectra of 6HSiC samples are essentially unaected by the charging temperature. One might suspect that at low temperatures the lling of interface states could be aected by the reduction in the majority carrier concentration. However, the quasi-static CV measurements in Fig. 2 show clearly that at 50 K in both 6H and 4HSiC samples there are enough majority carriers available to form an accumulation layer at the interface. This is evident since the

Fig. 4. TSC spectra recorded for various charging temperatures for (a) 4HSiC sample and (b) 6HSiC sample: (a) charging voltage Vch = 15 V, discharging voltage Vd = 5 V; (b) charging voltage Vch = 10 V, discharging voltage Vd = 3 V. Heating rate b = 0.2 K/s.

quasi-static accumulation capacitance in Fig. 2 is the same at room temperature and at 50 K. 4.3. Eect of the discharging voltage on the TSC spectra It turns out that the two sets of interface traps found in 4HSiC MOS structures, having dierent capture mechanisms described above, also dier in terms of the eect of the electric eld on the emptying process. This is evident from Fig. 5, which shows the TSC spectra recorded for various discharging voltages ranging from 0 to 50 V. The charging voltage is the same for all the curves. In Fig. 5(a) the charging voltage is applied at a suciently high temperature, so that both types of traps are involved, while in Fig. 5(b) it is applied at a low temperature so that only traps chargeable at low temperatures contribute to the TSC spectrum, giving rise to the 70 K TSC peak. Fig. 5(a) shows that the variation of the discharging voltage from 0 to 50 V has little eect on the emptying process of the high-temperature traps (traps whose lling is strongly dependent on temperature), while the TSC signal from the low-temperature traps (traps

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Fig. 6. TSC curves of the 4HSiC sample measured at dierent heating rates using charging temperature Tch = 27 K, Vch = 20 V, Vd = 1 V. The inset shows an Arrhenius plot where Tp is the peak temperature.

Fig. 5. TSC spectra of the 4HSiC sample for various discharging voltages varied from 0 to 50 V with the charging voltage Vch = 15 V: (a) the charging voltage is applied at Tch = 250 K, the discharging voltage is varied in 10 V steps; (b) the charging voltage is applied at T = 27 K, the discharging voltage is varied in 5 V steps. Heating rate b = 0.333 K/s.

chargeable at low temperatures) decreases with increasing depletion voltage. This is more evident in Fig. 5(b) where only low-temperature traps are present in the spectra, showing that the 70 K TSC peak progressively reduces with discharging voltage. This is explained by the emptying of the associated traps by a eld-enhanced emission process during the short waiting period prior to the start of heating, so that they do not contribute to the TSC signal. It should be noted that in n-type 6HSiC samples, the interface-related TSC signal, observed at temperatures above 50 K, is unaected by the discharging depletion voltage (not shown). 4.4. An analysis of the trap energy distributions In this section we focus on the interface traps in 4H SiC MOS capacitors. In order to determine the trap ionization energies from TSC spectra, we applied several methods. The parameters of traps responsible for the 70 K TSC peak were found using TSC measurements at various heating rates b as shown in Fig. 6. The heating rate variation method is usually applied when there

is a well-pronounced TSC peak [18]. In this method, an activation energy and a capture cross-section are obtained from a plot of logT 4 p =b versus 1/Tp where Tp is the peak temperature [17,18]. The linear t of such a plot, shown in the inset in Fig. 6, gives an activation energy Ea of 0.11 eV, and an electron capture cross-section (rn) of about 1017 cm2. The energy distribution of traps of the second group responsible for the wide TSC spectrum in the temperature range 100250 K was found using the standard fractional cleaning procedure and the initial rise method as shown in Fig. 7 [17,19]. The initial rise method assumes that at the initial stage of thermal emission the current varies as I(T) / exp(Ea/kT), thus the activation energy Ea can be calculated from the slope of log(I) versus 1/T. In the fractional cleaning procedure, linear heating is

Fig. 7. Thermal fractional cleaning of the 4HSiC TSC spectrum performed after high-temperature trap lling at Tch = 250 K (Vch = 20 V, Vd = 1 V, b = 0.333 K/s). The dashed line shows the TSC curve measured without cleaning. The right inset shows schematically variation of the sample temperature with time in the regime of the fractional cleaning heating. The left inset shows the activation energy extracted from the Arrhenius plot of the initial rise of each TSC scan.

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replaced by saw-tooth heating regime as shown in the right inset in Fig. 7 [19], so that the part of the traps with higher emission rates are sequentially removed from the TSC spectra. This is performed as follows. The TSC spectrum is recorded up to a certain temperature, then the temperature is lowered by a denite value (in our case, by 20 K) with the depletion bias on and a new TSC spectrum is recorded. By these means traps emitting below a certain temperature are removed or cleaned from the spectrum and only traps emitting at higher temperatures contribute to the TSC signal. As a result, the TSC spectrum is splitted into series of initial rise regions as shown in Fig. 7. The activation energies extracted from an Arrhenius plot of the initial rise of each TSC scan are plotted in the left inset in Fig. 7. The extracted trap activation energies increase monotonically from 0.1 to 0.7 eV over the temperature range from 70 to 170 K. We also used the method by Simmons et al. which is applicable for the treatment of TSC spectra of systems containing arbitrary trap distributions [14,15]. This method is based on an approximate closed-form solution of the TSC equations showing that the TSC curve is a direct image of the energy distribution of the occupied traps, which only depends slightly on the capture cross-section. The trap energy distribution obtained by the direct transformation of the 4HSiC TSC curves measured for high-temperature (Tch = 250 K) trap lling (not shown) agrees well with results of the fractional thermal cleaning, namely, it shows a very high density (>1013 cm2 eV1) in a wide energy range (from 0.15 to 0.5 eV) with a maximum of 2.2 1013 cm2 eV1 (for Vch = 24 V) at 0.3 eV [22]. It should be noted that the interpretation of TSC spectra is based on the assumption of a thermal excitation of carriers into the allowed band, and hence the reference level for the extracted trap ionization energy is usually assumed to be the edge of the corresponding allowed band. Therefore, for the SiO2 traps the reference level for the trap ionization energy is expected to be the SiO2 conduction band edge, while for the interface states positioned immediately at the interface, it should be the SiC conduction band edge. Thus if the traps involved are located immediately at the interface, the trap ionization energy extracted by the TSC analysis should reect the trap energy position in the SiC bandgap relative to the SiC conduction band edge, just as in the highlow frequency CV techniques. Therefore, the trap energy distribution given by the TSC and CV techniques for the traps located immediately at the interface is expected to be approximately the same. Such correlation between TSC and CV results is actually observed for 6HSiC, however, it is not observed for 4HSiC [22]. The interface state density extracted from the highlow frequency CV measurements of the 4HSiC sample increases rapidly towards to the conduction band edge, in agreement with previous CV observations [1,410]. However, in

the CV data there is no peak visible at 0.3 eV and the density of interface states in the energy range 0.15 0.5 eV is not as high [22]. In other words, the vast majority of the traps revealed by the TSC measurements in 4HSiC MOS structures are not detected by room-temperature CV measurements. We will turn back to this dierence between TSC and CV results in 4HSiC samples in the discussion section. For 6HSiC, the interface trap energy distributions extracted from both TSC and CV measurements are monotonic with the density slowly increasing towards the conduction band edge (from approximately 3 1011 to 1012 cm2 eV1 in the energy range 0.70.1 eV) [22]. Thus for 6HSiC, there is a fair correlation between TSC and CV results, as is expected for traps located at the interface.

5. Discussion Before proceeding we point out that the electrical properties discussed above are found to be essentially the same for a variety of dierently prepared thermal oxides on o-axis n-type Si face 4HSiC. The TSC spectra are more or less identical. All samples clearly show the presence of two groups of traps with the same charge carrier dynamics as described above [23]. This applies to dry oxides, wet oxides and oxides that received post-oxidation anneal in pyrogenic steam, Ar/H2 or N2. All the trap properties of the 4HSiC/SiO2 interfaces, that are described in the previous sections, cannot be assigned to the conventional fast interface states which reside immediately at the interface. However, they are attributable to near-interfacial oxide defects. The traps revealed as the 70 K TSC peak, whose lling mechanism depends only slightly on the temperature while the emptying process depends strongly on the electric eld at the SiC/SiO2 interface, are most likely located suciently close to the interface for tunneling to occur. The traps of the second group, whose charging process is thermally activated and discharging is almost insensitive to the electric eld at the interface, are presumably located deeper in the oxide. Both groups of traps are acceptor-type (initially neutral), because no signicant interface charge is revealed by room-temperature CV measurements. The fact that we always observe both groups together in all our thermal oxides indicates a common origin of the associated defects. It is reasonable to assume a defect of a particular chemical or structural origin that has a well-dened trap energy level. This leads us to suggest that traps of both groups are due to the same defect which is energetically located near the 4HSiC conduction band edge and spatially distributed from the interface into the oxide. The proposed model is schematically shown in Fig. 8.

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Fig. 8. Schematic representation of the proposed model of the traps at the 4HSiC/SiO2 interface displayed in TSC measurements.

In this model, the well-resolved 70 K TSC peak stems from traps located in the immediate proximity to the interface, whereas the remaining spectrum is due to traps located farther away from the interface. The trap ionization energy extracted from the analysis of the 70 K TSC peak (Ea = 0.11 eV) should then reect the energy position of the trap level in respect to the 4HSiC conduction band edge, and the extracted value of the capture cross-section should be close to its true microscopic value. Indeed, the above energy position of the trap level is in a good agreement with the reported value of about 0.1 eV below the SiC conduction band edge obtained using internal photoemission [4], photon-stimulated electron tunneling spectroscopy and temperaturedependent admittance spectroscopy [7,9]. The estimated electron capture cross-section (r = 1017 cm2) is reasonable for an acceptor-type center. The assumption that traps of the second group originate from the same defect but are located deeper in the oxide is consistent with the thermally activated capture mechanism observed for these traps. This agrees with observations of the large capture time constants reported in Ref. [9] and anomalously low eective capture cross-sections obtained by CC-DLTS in Ref. [24]. However, certain diculties emerge explaining the range of the ionization energies obtained for these traps. The problem is that the obtained ionization energies (0.1 0.7 eV) are too small to be assigned to a thermal excitation from a level that is energetically located near the 4HSiC conduction band edge to the SiO2 conduction band, because the conduction band oset at the 4H SiC/SiO2 interface is known to be 2.7 eV [4,7,9]. On the other hand, these trapping levels also cannot be attributed to conventional fast interface states, because no interface states of such a high density as revealed by TSC measurements (>1013 cm2 eV1) were detected in the range 0.10.7 eV below the SiC conduction band edge by room-temperature CV measurements [22]. It is possible to explain the obtained range

of trap ionization energies by the presence of a silicon oxycarbide (SiCxOy) transition layer at the thermal oxideSiC interface. The existence of such a layer has been deduced from recent X-ray photoelectron spectroscopic and optical studies [25,26]. Within the transition layer one can expect a continuous (or local) variation in the bandgap and the conduction band oset ranging from SiC to SiO2. Electron emission from traps within this transition layer could explain the range of activation energies obtained by the TSC analysis as indicated in Fig. 8. On the other hand, it is reasonable to expect that lling of these traps should be thermally activated. Though this model is currently rather speculative, it allows us to explain all our results on 4HSiC/SiO2 interfaces, and at the same time it is consistent with all previously published observations. In the case of 6HSiC/SiO2 interfaces, most of our observations can be explained in the framework of conventional fast interface states. However, if the defects seen in 4HSiC exist also in 6HSiC, it is expected that due to the bandgap dierence between 4H and 6HSiC of about 0.2 eV they should be displayed in the TSC measurements at lower temperatures. It is possible that the interface-related TSC signal observed in the 6H SiC samples below 25 K (see inset in Fig. 1(b)) is a signature of the same defects found at the 4HSiC/SiO2 interface. More experimental data is needed to conclude on this matter.

6. Conclusions Using TSC measurements we demonstrate that electron traps at the 4HSiC/SiO2 interface near the 4H SiC conduction band edge are composed of two groups of trapping centers with dierent properties. The lling mechanism of traps in the rst group is only slightly dependent on the temperature, and their emptying process depends strongly on the electric eld at the interface, suggesting that these traps are located very close to the interface. The activation energy of these traps is found to be 0.11 eV. The lling process of traps in the second group is thermally activated, and their emptying process is unaected by the electric eld at the SiC/SiO2 interface. A wide distribution of trap activation energies ranging from 0.1 to 0.7 eV is obtained by the TSC analysis for these traps. The same TSC signature was observed for dierently processed thermal oxides grown on 4HSiC. We propose that both groups of traps at the 4HSiC/SiO2 interface stem from the same intrinsic interfacial defect energetically located near the 4HSiC conduction band edge and spatially distributed from the interface into the oxycarbide transition region. This intrinsic interface defect is not observed in 6H SiC samples in the temperature range 50300 K. The density of interface states near the SiC conduction band

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edge is order of magnitude lower in 6HSiC than in 4H SiC. Between temperatures of 50300 K, the interfacial electrical characteristics of 6HSiC samples are explained in terms of conventional fast interface states. However, it is possible that the TSC signal in 6HSiC samples below 25 K is a signature of the same intrinsic interfacial traps discussed above for 4HSiC samples.

Acknowledgment This work was nancially supported by the Swedish Institute Visby Program and the Swedish Foundation for Strategic Research as part of the Silicon Carbide Electronics Program (SiCEP).

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