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Module 1.

Introduction to ASIC Design

Introduction to ASIC Design The semiconductor industry is different from every other industry in the world in a fundamental way. This fundamental difference presents to you, a participant in this industry, both enormous opportunities and challenges. The first part of this lesson focuses on that key difference that the underlying engine that fuels this growth increases in capability at an exponential rate. You most likely have some familiarity with the types of chips used in the semiconductor industry and the types of design and implementation styles used. The second part of this lesson starts classifying those from the sole perspective of an ASIC designer. Objectives Understand Moores Law and its impact on the semiconductor industry. Identify the defining attributes of full custom, standard cell and gate ASICs from a design and fabrication cost perspective. Identify the key steps in designing an ASIC Identify the challenges facing the semiconductor industry Key Points Exponential scaling permits fundamentally new products to be introduced on a regular cycle. ASICs are used when software is not adequate for the task from a performance or cost perspective.. Full custom ICs. Complex, expensive design, so only used for parts requiring specific circuits. They also have the highest performance. Cell based ASICs are assembled from pre-designed standard cells, using synthesis. Thus they take orders of magnitude less design effort than full custom ICs but still require a full mask set and thus take 4-8 weeks to fab. Gate array chips are built by defining just some wiring layers on already fabricated wafers containing an array of logic gates. They are designed much like cell based ICs but only a smaller mask set is required for fab, and thus take only 1-2 weeks to make. Their performance level is much lower than that of a cell based IC. FPGAs are used when the performance requirement is sufficiently low to be mapped onto an FPGA and reducing per-unit price is not imperative The major steps in the ASIC design flow are: 1. System specification 2. Logic design (RTL) 3. Logic verification 4. Physical design 5. Final verification

The Non Recurring Engineering (NRE or up-front cost) of designing a standard cell ASIC is increasing at a fast rate. The business case for this style has to be well established in order to justify the investment.

Further Reading Ciletti: Ch. 1. (Design and CAD flow) Section 8.9.1 (FPGA market) S&F: None for this section Other: EE Times Electronic Design Electronic Products Deep Chip