Introduction To ASIC Design: Dr. Paul D. Franzon Genreal Outline

Digital ASIC Design
1. Introduction to ASIC Design

Dr. Paul D. Franzon Genreal Outline
1. The wonderful world of Silicon 2. Application Specific Integrated Circuits (ASICs)
Typical applications, types, decision making
3. ASIC Design Flow 4. Trends
2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
Digital ASIC Design
Module Objectives and Motivation

Objectives:

Understand Moores Law and its impact on the semiconductor industry. Identify the defining attributes of full custom, standard cell and gate ASICs from a design and fabrication cost perspective. Identify the key steps in designing an ASIC Identify the challenges facing the semiconductor industry
Reasons for module:

Relate to global context of the course, alternative technologies, and underlying trends Put this class in context of entire design flow
Digital ASIC Design
References
Ciletti:

Ch. 1. (Design and CAD flow) Section 8.9.1 (FPGA market) None for this section EE Times Electronic Design Electronic Products Deep Chip www.eetimes.com www.electronicdesign.com www2.electronicproducts.com www.deepchip.com
S&F:
Other:

Digital ASIC Design
Topical Outline
1. Engineered Systems - Complexity 2. The wonderful world of Silicon Moores Law 3. ASIC vs what?; ASIC styles 4. Example of an ASIC dominated product 5. ASIC Design Flow 6. Future trends and issues
Digital ASIC Design
Which is more complex?
NASA Saturn V Rocket
nVidia GX 280 Graphics Engine
Digital ASIC Design
The Wonderful World of Silicon Moores Law About every eighteen months, the number of transistors on a CMOS silicon chip and the gate delay improves

Transistors/Chip increasing by 50% per year (by 4 in 3.5 years) Cost per transistor decreasing at same rate Gate Delay decreasing by 13% per year (by in 5 years but this rate is slowing down)
This rate of improvement will continue until about 2025 at least.
Digital ASIC Design
Technology Drivers Decreasing lithographic feature size, e.g. measured by the transistor gate length:
90 nm, 65 nm, 45 nm, 28 nm, 22 nm, 14 nm, 5 nm, ?? 8 inch (200 mm) diameter.. 12 in (300 mm), 18 in (450 mm)?
Increasing wafer size:
Increasing number of metal interconnect layers:
6 .. 8 9 .
c/- Intel
Source: Intel
Digital ASIC Design
Cost Scaling Cost per transistor scales down:
Approximately constant cost per wafer to manufacture (in volume): About $1,000 - $2,000 per wafer Increasing IC yields for large (> 1 sq. cm.chips): 60% . 90% Design cost increases with transistor count Mask cost increases with each new family
But cost to first chip scales up!

Digital ASIC Design
Semiconductor Roadmap
ITRS 2009
2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 9
Digital ASIC Design
pitch = Technology node ITRS 2009

Digital ASIC Design
ITRS 2009
Digital ASIC Design
Sub-module Summary
Silicon chips represent a crowning technology achievement, that create new capabilities with each new generation, enabling the digital revolution Transistor density has increased exponentially with time since the first integrated circuit this is referred to as Moores Law
Moores Law has profound implications on the growth of digital processing capability Quiz Next sub-module
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Digital ASIC Design
Introduction - Topical Outline

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Digital ASIC Design
ASICs vs. What? Application Specific Integrated Circuit

A chip designed to perform a particular operation as opposed to General Purpose integrated circuits An ASIC is generally NOT software programmable to perform a wide variety of different tasks
An ASIC will often have an embedded CPU to manage suitable tasks An ASIC may be implemented as an FPGA (see later)
Sometimes considered a separate category
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Digital ASIC Design
ASICs vs. What? (contd) General Purpose Integrated Circuits: Examples:
Programmable microprocessors (e.g. Intel Processor, ARM M0, Motorola HC-11, etc.) Used in washing machines to PCs Programmable Digital Signal Processors (e.g. TI TMS 430 Series) Used in many multimedia, sensor processing and communications applications Graphics Computation Unit (GPU) Very good at parallel arithmetic Volatile Memory (DRAM, SRAM, etc.) Non Volatile Memory (Flash, PCM. STT, etc.)
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Digital ASIC Design
Examples of ASICs

Video processor to decode or encode MPEG-2 digital TV signals Graphics processor Low power dedicated DSP/controller / CODECs / convergence device for mobile phones Encryption processor for security Network processor for managing packets, traffic flow, etc. Most CPUs are designed using an ASIC (RTL-based) design methodology
ASIC implementation outperforms software by many (2-3) orders of magnitude in terms of performance, power efficiency but requires many more engineers to implement.
Digital ASIC Design
ASIC Styles Full Custom ASICs

Every transistor is designed and drawn by hand Typically only way to design analog and ultra high speed portions of ASICs Gives the highest performance but the longest design time Full set of masks required for fabrication
Source: NCSU.
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Digital ASIC Design
ASIC Styles (contd)

Standard-Cell-Based ASICs

or Cell Based IC (CBIC) or semi-custom Standard Cells are custom designed and then inserted into a library These cells are then used in the design by being placed in rows and wired together using place and route CAD tools Some standard cells, such as RAM and ROM cells, and some datapath cells (e.g. a multiplier) are tiled together to create macrocells
D-flip-flop:
NOR gate:
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Digital ASIC Design
Standard Cell ASICs (contd)

Sample ASIC floorplan:
CPU core ROM
Standard Cell rows Datapath RAM
Standard Cell designs are usually synthesized from an RTL (Register Transfer Language) description of the design Full set of masks (22+) still required
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Digital ASIC Design
Chip Fabrication
Chip is made by successive imaging and processing of a silicon wafer through a set of masks
Layout
2 8 inch wafers
c/- NASA
Digital ASIC Design
Cell based ASICs (contd) Fabless semiconductor company model
Company does design only. Fab performed by another company (e.g. TSMC, UMC, Global Semiconductor, IBM). Back-end (place and route, etc.) might be performed at that company or with their assistance
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Digital ASIC Design
ASIC Styles (contd) Gate-Array Based ASICs
In a gate array, the transistors level masks are fully defined (as a sea of logic gates) and the designer can not change them The designer instead defines some of the wiring and vias to implement the desired function Gate array designs are slower than cell-based designs but the implementation time is faster as less time must be spent in the factory RTL-based methods and synthesis, together with other CAD tools, are often used for gate arrays.
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Digital ASIC Design
Gate Array (contd) Examples: Chip Express

Wafers built with sea of macros + 4 metal layers 2 metal layers customized for application Only 4 masks!
Triad Semiconductor

Analog and Digital Macros 1 metal layer for customization (2 week turnaround)
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Digital ASIC Design
ASIC Styles (contd) Programmable Logic Devices (PLDs and FPGAs)

FPGA= Field Programmable Gate Array Are off-the-shelf ICs that can be programmed by the user to capture the logic There are no custom mask layers so final design implementation is a few hours instead of a few weeks Simple PLDs are used for simple functions. FPGAs are increasingly displacing standard cell designs. Capable of capturing 100,000+ designed gates High power consumption High per-unit cost FPGAs are also slow (< 100 MHz)
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Digital ASIC Design
FPGA (contd) Sample internal architecture:

Store logic in look-up table (RAM) Programmable interconnect Configurable Logic Block (CLB):
Programmable Interconnect Array:
Source: XILINX Application notes 2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
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Digital ASIC Design
Standard Cell ASIC Positives Highest performance: >1 Billion transistors at multi-GHz rates. Often only way to meet a spec. Lowest power consumption Lowest high volume cost (sometimes few $ per die) High design, CAD and wafer costs Long time to firstproduct to market (long design time + >4 weeks for fab)
Gate Array Fairly Low design, CAD and up-front costs Time from design ready to first part 12 weeks Lowest midvolume price Power closer to SC ASIC Performance not a lot more than FPGA
FPGA Low design, CAD and up-front costs Time from design ready to first part almost zero
Negatives
Low performance (<1 million implemented logic gates @ 10s to 100s of MHz, power 10x ASIC) High unit cost ($10s to $1,000s) Especially useful in markets that change fast or have low volumes
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Comments
Digital ASIC Design
Example
Example of total cost calculation:
NRE = Non Recurring Enginnering (cost) (cost of design, masks, etc.)
(Average Selling Price)
Source: AMI
27
Digital ASIC Design
Comments
Market currently dominated by standard cell ASICs and FPGAs
Ideally standard cell designs would be used for higher volume applications that justify the NRE
Many consider FPGAs separate from ASICs Why?

Different level of design skills required, especially in back end (place and route or physical design) Reduced level of verification required before sending to factory Again reduces sophistication required of team Low-cost (barrier) of entry to FPGAs Often different, lower cost Design Automation (CAD) tools Lower performance of FPGAs
However, front-end design (RTL coding) is virtually identical for each implementation style
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Digital ASIC Design
Sub-module Summary
ASICs can be built in different styles
Full-custom in which every transistor is designed usually only analog or specialized portions of a chip Standard Cell design in which a full set of masks gets specified from predesigned logic cells Gate Array in which the transistor logic gate array is fixed but the wiring is specified from the design Field Programmable Gate Array in which a programmable switch matrix and logic as look up tables are programmed to become a set of logic gates
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Digital ASIC Design
Sub-module Summary
Each has different end capabilities
Custom Design Capture Design Cost Design Cycle Verification Effort # logic-gates/ chip Clock Frequency Power Consumption Transistor Very High* Long High Std Cell RTL Highest Long High Highest Highest Lowest Gate Array RTL Low Short Modest Modest Modest Modest FPGA RTL Lowest Shortest Low Lowest Lowest Highest
* Very high per transistor so not used for large functional units
Digital ASIC Design
Transition
Please do the sub-module quiz before transitioning to the next sub-module
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Digital ASIC Design
Topical Outline
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Digital ASIC Design
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Digital ASIC Design
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Digital ASIC Design
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Digital ASIC Design
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Digital ASIC Design
Topical Outline
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Digital ASIC Design
ASIC Design Flow

Major Steps:
1. High Level Design Specification Capture Design Capture in C, C++, SystemC or SystemVerilog (etc.) HW/SW partitioning IP selection (choose from pre-existing designs or Intellectual Property) 2. RTL Design Major topic of this course 3. System, Timing and Logic Verification Front end Is the logic working correctly? 4. Physical Design Floorplanning, Place and Route, Clock insertion Back end 5. Performance and Manufacturability Verification Extraction of Physical View Verification of timing and signal integrity Design Rule Checking
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Digital ASIC Design
ASIC Design Methodology Most ASICs are designed using a RTL/Synthesis based methodology Design details captured in a simulatable description of the hardware

Captured as Register Transfer Language (RTL) Simulations done to verify design
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Digital ASIC Design
Methodology (contd) Automatic synthesis is used to turn the RTL into a gate-level description

ie. AND and OR gates, etc. Chip-test features are usually inserted at this point
Gate level design verified for correctness Output of synthesis is a net-list
i.e. List of logic gates and their implied connections
NOR2 U36 ( .Y(n107), .A0(n109), .A1(\value[2] ) ); NAND2 U37 ( .Y(n109), .A0(n105), .A1(n103) ); NAND2 U38 ( .Y(n114), .A0(\value[1] ), .A1(\value[0] ) ); NOR2 U39 ( .Y(n115), .A0(\value[3] ), .A1(\value[2] ) );
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Digital ASIC Design
Methodology (contd) Physical Design tools used to turn the gate-level design into a set of chip masks (for photolithography) or a configuration file for downloading to an FPGA Floorplanning
Power Rings
CPU 1
Wishbone Traffic Cop
SRAM Address Pins
2520 m
Instruction SRAM
Data Memory Controller
CPU 2
Power Stripe
Placement
Positioning of major functions Gates arranged in rows
2524 m
CPU 1
Wishbone Traffic Cop
Instruction SRAM
Data Memory Controller
CPU 2
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Digital ASIC Design
Methodology (contd)
Clock and buffer Insertion
Distribute clocks to cells and locate buffers for use as amplifiers in long wires
Routing Logic Cells wired together
(Figures c/- Schoenfloss, Davis, Rao)
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Digital ASIC Design
Methodology (contd) Subflow example: Timing Closure:
Start
Front end of design process = Design capture, simulation and synthesis Assumes abstract information about impact of wires Back end of design process Place and route Requires accurate wiring models
Load, link, and constrain design in Primetime
Verilog structural description of design (post clock tree synthesis)
Back-annotate wiring parasitics in Primetime
Post-route SPEF file from SoC Encoutner
Report timing in Primetime
Finish
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Digital ASIC Design
Transition
1. 2. Sub-module quiz. Proceed to next sub-module
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Digital ASIC Design
Topical Outline
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Digital ASIC Design
Future Issues
Increased cost of custom fab
Cost to first chip rising ~60% with every generation Design Cost + Cost of making masks Design cost see in 2 pages Mask making - $4M or more! Time-to-market pressures increasing, so design teams are trying to reduce design time Number of gates in design Impact of interconnect increasing Increasing process variations leading to timing variation Sub-wavelength lithography complicating mask design Building 10 nm scale features using 192 nm light!
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Globalization
Increased complexity of design

Digital ASIC Design
Future Issues (contd) Trends

Increased use of FPGA and Gate Arrays Increased use of platform solutions Multi-core embedded CPU + ASIC accelerators Increased use of existing designs (IP or Intellectual Property) Increased use of SystemVerilog, SystemC and other system modeling tools Complexity shifting from design to logical and performance verification Logical verification = function; Performance = speed Cost to first silicon getting so high that the total addressable market must be very large and product risk low
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Digital ASIC Design
Design Cost
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Digital ASIC Design
System On a Chip (SOC)
ITRS 2009
Digital ASIC Design
Example: Mobile System On a Chip (SOC)
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Digital ASIC Design
Other Scaling Trends

The impact of the wiring increases with each generation
C same R higher
Wires in previous generation
RC delay worse!
Source: Sakurai, IEEE
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Digital ASIC Design
Employment Trends
US Employment Growth

US employment growth in chip design is still strong, esp. system on chip integration, verification Skill set largely in design, verification and test side, not layout and backend
Source: EDN Global Survey 2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 52
Digital ASIC Design
Systems Perspective
Roughly 15% of engineers are systems engineers Likely to grow (in US)
Digital ASIC Design
Introduction - Summary
Moores Law predicts that the number of transistors per chip increases exponentially with time
Which in turn impacts cost/function and circuit speed
RTL is used as the design entry for each main implementation style (standard cell, gate array, FPGA)
Choice depends on performance, power and product iteration requirements, together with the NRE investment that can be justified by the market Synthesis, place& route, timing verification, performance and manufacturability verification Due to growing complexity driven by gate count, process variations and subwavelength lithography Platform based design, IP reuse and spiral design helps but does not solve the problem
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Many CAD tools are used in the design process, including
Standard cell design cost increases dramatically at advanced nodes

Introduction To ASIC Design: Dr. Paul D. Franzon Genreal Outline

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Digital ASIC Design

1. Introduction to ASIC Design

Typical applications, types, decision making

3. ASIC Design Flow 4. Trends

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

Module Objectives and Motivation

Reasons for module:

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

Which is more complex?

NASA Saturn V Rocket

nVidia GX 280 Graphics Engine

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

This rate of improvement will continue until about 2025 at least.

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

Increasing wafer size:

Increasing number of metal interconnect layers:

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

Cost Scaling Cost per transistor scales down:

But cost to first chip scales up!

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

Digital ASIC Design

pitch = Technology node ITRS 2009

Digital ASIC Design

Digital ASIC Design

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

Introduction - Topical Outline

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

ASICs vs. What? Application Specific Integrated Circuit

Sometimes considered a separate category

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

ASICs vs. What? (contd) General Purpose Integrated Circuits: Examples:

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

Digital ASIC Design

ASIC Styles Full Custom ASICs

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

ASIC Styles (contd)

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

Standard Cell ASICs (contd)

Standard Cell rows Datapath RAM

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

Digital ASIC Design

Cell based ASICs (contd) Fabless semiconductor company model

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html

Digital ASIC Design

ASIC Styles (contd) Gate-Array Based ASICs

2013 Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html