Computer Architecture (CS-213)

Main Objectives
Introduction to MIPS Architecture MIPS Architecture Based Single Cycle Processor Datapath Design Control Unit Design

Revision
Remember these Names ? Register File ALU Instruction Memory Data Memory Program Counter Instruction Set Architecture (ISA)

Design of Processor
1. Analyze the instruction set architecture 2. Select the datapath elements each instruction needs 3. Assemble the datapath 4. determine the controls required 5. Assemble the control logic

A Basic MIPS Implementation

MIPS 32-bit architecture has 32-bit instruction size and 32-bit data bus width. We will implement the following subset of MIPS core instructions
lw, sw add, sub, and, or, slt beq, j

A Basic MIPS Implementation

Instruction lw sw add sub and slt Function Load Word Store Add Subtract AND Set Less Than Description Similar to LD (load). It copies data from memory and loads into a register. Similar to ST (store). It copies data from a register into a memory location Adds Two Registers and Stores the result in third. Subtracts Two Registers and Stores the result in third. ANDs Two Registers and Stores the result in third. Similar to CMP (compare) , Compares to see if one register is less than the other and Stores the value 1 in third if true and 0 if false. Similar to BEQ, compares to register if the result is equal, than it branches the PC to new address calculated by adding a register and offset address Makes the PC Jump unconditionally to new value.
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beq

Branch Equal

Jump

Registers in MIPS

Instruction Formats
R-Type Instruction Fromat(add,sub,or)
31-26 25-21 20-16 15-11 Write reg. 10-6 Not Used 5-0 To ALU Control

Opcode
To ctrl logic

RS
Read reg. A

RT
Read reg. B

RD ShAmt Function

Branch Type and Memory Format(beq,lw,sw)

31-26 25-21 20-16 15-0

Opcode
To ctrl logic

RS
Read reg. A

RT
Write reg./ Read reg. B

Immediate Data
Memory address or Branch Offset

Steps in executing add instruction

add $t0, $t1, $t2 Send PC to memory that contains the code and fetch instruction PC = PC+4 Read $t1 and $t2 from register file Perform $t1 + $t2 Store result in $t0
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Steps in executing lw instruction

lw $t0, offset($t1) Send PC to memory that contains the code and fetch instruction PC = PC+4 Read $t1 from register file Perform $t1 + sign-extend(offset) Read value at Mem[$t1 + sign-extend(offset)] Store result in $t0
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Steps in executing lw instruction

sw $t0, offset($t1) Send PC to memory that contains the code and fetch instruction PC = PC+4 Read $t1 from register file Perform $t1 + sign-extend(offset) Store contents of $t0 at Mem[$t1 + signextend(offset)]
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Steps in executing beq instruction

beq $t0, $t1, Label Send PC to memory that contains the code and fetch instruction PC = PC+4 Read $t0 and $t1 from register file Perform $t0 - $t1 If result = 0, set PC=Label
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Steps in implementing these instructions

Common steps
Send PC to memory that contains the code and fetch the instruction Set PC = PC+4 Read one or two registers Use ALU

Steps dependent on instruction class

Update memory or registers

Arithmetic/logical instr for operation execution lw/sw for address calculation beq for comparison lw/sw read or write to memory Arithmetic/logical instr write to register beq updates PC

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Components needed for Fetching and Incrementing PC

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Datapath for Fetching and Incrementing PC

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Components needed for R-format Instructions

add $t0, $t1, $t2: $t0= $t1 + $t2 and $t0, $t1, $t2: $t0= $t1 AND $t2

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Register File
Consists of a set of 32 registers that can be read and written has two read ports and one write port Register number are 5 bit long To write, you need three inputs:
a register number, the data to write, and a clock (not shown explicitly) that controls the writing into the register The register content will change on clock edge

5 5 5

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Portion of datapath for R-format instruction

4 rs rt rd

R-format

31-26 opcode

25-21 rs

20-16 rt

15-11 rd

10-6 shamt

5-0 funct
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Components needed for load and store instructions

lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)] sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0

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Memory Unit
MemRead to be asserted to read MemWrite to be asserted to write Both MemRead and MemWrite not to be asserted in same clock cycle Memory is edge triggered for writes
Address

MemRead

ReadData

Write Data

MemWrite
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Load/Store instruction Datapath

lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)] sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0
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I-format

31-26

25-21 20-16 15-0 rt offset

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opcode rs

Load instruction datapath

lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)] rs
4

rt

offset

I-format

31-26

25-21 20-16 15-0 rt offset

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opcode rs

Store instruction datapath

sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0 rs rt
4

offset

I-format

31-26

25-21 20-16 15-0 rt offset

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opcode rs

Branch Instruction Datapath

rs rt

31-26
C

25-21 rs

20-16 rt

15-0 C
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opcode

If ($rs-$rt)=0, PC=PC+4+(C.4)

Creating a single Datapath

Simplest Design: Single Cycle Implementation Any instruction takes one clock cycle to execute
This means no datapath elements can be used more than once per instruction But datapath elements can be shared by different instruction flows

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Composite Datapath for R-format and load/store instructions

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Composite Datapath for R-format and load/store instructions

4 +

P C

Instruction Memory

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Composite datapath for R-format, load/store, and branch instructions

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Composite datapath for R-format, load/store, and branch instructions

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Datapath for for R-format, load/store, and branch instructions

ALU Operation

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Instruction

RegDst

RegWrite

ALUSrc

MemRead

MemWrite

MemToReg

PCSrc

ALU operation

R-format

0000(and) 0001(or) 0010(add) 0110(sub) 0010 (add) 0010 (add) 0110 (sub)

lw sw beq

0 X x

1 0 0

1 1 0

1 0 0

0 1 0

1 X X

0 0 1 or 0

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Control
We next add the control unit that generates
write signal for each state element control signals for each multiplexer ALU control signal

Input to control unit: instruction opcode and function code

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Control Unit
Divided into two parts
Main Control Unit
Input: 6-bit opcode Output: all control signals for Muxes, RegWrite, MemRead, MemWrite and a 2-bit ALUOp signal

ALU Control Unit

Input: 2-bit ALUOp signal generated from Main Control Unit and 6-bit instruction function code Output: 4-bit ALU control signal

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What do we need to control?

4
Result

Mux - are we branching or not?

RegistersShould we write data?

0 Result Sh. Left 2 1

Add

Add
Read reg. num A A reg num Read reg data A Read reg num B

Mux - Result from ALU or Memory?

Read address

PC

Read address Instruction [31-0]

Registers

Instruction Memory

Write reg num Read reg data B Write reg data

Zero Result 0 1

Data Memory

Read data Write address

1 0

Write data

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32 sign Mux - Where extend

does 2nd ALU operand come from?

ALU What is the Operation?

MemoryRead/Write/neither?

Almost all of the information we need is in the instruction!

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Control Signals
1. RegDst = 0 => Register destination number for the Write register comes from the rt field (bits 20-16) RegDst = 1 => Register destination number for the Write register comes from the rd field (bits 15-11) 2. RegWrite = 1 => The register on the Write register input is written with the data on the Write data input (at the next clock edge) 3. ALUSrc = 0 => The second ALU operand comes from Read data 2 ALUSrc = 1 => The second ALU operand comes from the signextension unit 4. PCSrc = 0 => The PC is replaced with PC+4 PCSrc = 1 => The PC is replaced with the branch target address 5. MemtoReg = 0 => The value fed to the register write data input comes from the ALU MemtoReg = 1 => The value fed to the register write data input comes from the data memory 6. MemRead = 1 => Read data memory 7. MemWrite = 1 => Write data memory

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Truth Table for Main Control Unit

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Main Control Unit

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ALU Control Unit

Must describe hardware to compute 4-bit ALU control input given 2-bit ALUOp signal from Main Control Unit function code for arithmetic Describe it using a truth table (can turn into gates):

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ALU Control bits

0010 0010 0110 0010 0110 0000 0001 0111

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